From nobody Fri Jun 19 14:37:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09091C433EF for ; Sat, 2 Apr 2022 07:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351683AbiDBHvb (ORCPT ); Sat, 2 Apr 2022 03:51:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242803AbiDBHvU (ORCPT ); Sat, 2 Apr 2022 03:51:20 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57BAD35DF6; Sat, 2 Apr 2022 00:49:29 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Sat, 2 Apr 2022 15:49:27 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v4 1/2] mtd: rawnand: meson: discard the common MMC sub clock framework Date: Sat, 2 Apr 2022 15:49:19 +0800 Message-ID: <20220402074921.13316-2-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220402074921.13316-1-liang.yang@amlogic.com> References: <20220402074921.13316-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' wh= ich is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider a= nd bit6~7 is the mux for fix pll and xtal.A common MMC and NAND sub-clock has = been implemented and can be used by the eMMC and NAND controller (which are mutu= ally exclusive anyway). Let's use this new clock. Signed-off-by: Liang Yang Reported-by: kernel test robot --- drivers/mtd/nand/raw/meson_nand.c | 89 +++++++++++++++---------------- 1 file changed, 42 insertions(+), 47 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson= _nand.c index ac3be92872d0..1b1a9407fb2f 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include =20 #define NFC_REG_CMD 0x00 @@ -104,6 +106,9 @@ =20 #define PER_INFO_BYTE 8 =20 +#define CLK_DIV_SHIFT 0 +#define CLK_DIV_WIDTH 6 + struct meson_nfc_nand_chip { struct list_head node; struct nand_chip nand; @@ -151,15 +156,15 @@ struct meson_nfc { struct nand_controller controller; struct clk *core_clk; struct clk *device_clk; - struct clk *phase_tx; - struct clk *phase_rx; + struct clk *nand_clk; + struct clk_divider nand_divider; =20 unsigned long clk_rate; u32 bus_timing; =20 struct device *dev; void __iomem *reg_base; - struct regmap *reg_clk; + void __iomem *sd_emmc_clock; struct completion completion; struct list_head chips; const struct meson_nfc_data *data; @@ -235,7 +240,7 @@ static void meson_nfc_select_chip(struct nand_chip *nan= d, int chip) nfc->timing.tbers_max =3D meson_chip->tbers_max; =20 if (nfc->clk_rate !=3D meson_chip->clk_rate) { - ret =3D clk_set_rate(nfc->device_clk, meson_chip->clk_rate); + ret =3D clk_set_rate(nfc->nand_clk, meson_chip->clk_rate); if (ret) { dev_err(nfc->dev, "failed to set clock rate\n"); return; @@ -406,7 +411,6 @@ static int meson_nfc_queue_rb(struct meson_nfc *nfc, in= t timeout_ms) cmd =3D NFC_CMD_RB | NFC_CMD_RB_INT | nfc->param.chip_select | nfc->timing.tbers_max; writel(cmd, nfc->reg_base + NFC_REG_CMD); - ret =3D wait_for_completion_timeout(&nfc->completion, msecs_to_jiffies(timeout_ms)); if (ret =3D=3D 0) @@ -985,9 +989,11 @@ static const struct mtd_ooblayout_ops meson_ooblayout_= ops =3D { .free =3D meson_ooblayout_free, }; =20 +struct clk_parent_data nfc_divider_parent_data[1]; static int meson_nfc_clk_init(struct meson_nfc *nfc) { int ret; + struct clk_init_data init =3D {0}; =20 /* request core clock */ nfc->core_clk =3D devm_clk_get(nfc->dev, "core"); @@ -1002,21 +1008,26 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) return PTR_ERR(nfc->device_clk); } =20 - nfc->phase_tx =3D devm_clk_get(nfc->dev, "tx"); - if (IS_ERR(nfc->phase_tx)) { - dev_err(nfc->dev, "failed to get TX clk\n"); - return PTR_ERR(nfc->phase_tx); - } - - nfc->phase_rx =3D devm_clk_get(nfc->dev, "rx"); - if (IS_ERR(nfc->phase_rx)) { - dev_err(nfc->dev, "failed to get RX clk\n"); - return PTR_ERR(nfc->phase_rx); - } + init.name =3D devm_kstrdup(nfc->dev, "nfc#div", GFP_KERNEL); + init.ops =3D &clk_divider_ops; + nfc_divider_parent_data[0].fw_name =3D "device"; + init.parent_data =3D nfc_divider_parent_data; + init.num_parents =3D 1; + nfc->nand_divider.reg =3D nfc->sd_emmc_clock; + nfc->nand_divider.shift =3D CLK_DIV_SHIFT; + nfc->nand_divider.width =3D CLK_DIV_WIDTH; + nfc->nand_divider.hw.init =3D &init; + nfc->nand_divider.flags =3D CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ALLOW_ZERO; + + nfc->nand_clk =3D devm_clk_register(nfc->dev, &nfc->nand_divider.hw); + if (IS_ERR(nfc->nand_clk)) + return PTR_ERR(nfc->nand_clk); =20 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - regmap_update_bits(nfc->reg_clk, - 0, CLK_SELECT_NAND, CLK_SELECT_NAND); + writel(CLK_SELECT_NAND | readl(nfc->sd_emmc_clock), + nfc->sd_emmc_clock); =20 ret =3D clk_prepare_enable(nfc->core_clk); if (ret) { @@ -1030,29 +1041,21 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) goto err_device_clk; } =20 - ret =3D clk_prepare_enable(nfc->phase_tx); + ret =3D clk_prepare_enable(nfc->nand_clk); if (ret) { - dev_err(nfc->dev, "failed to enable TX clock\n"); - goto err_phase_tx; + dev_err(nfc->dev, "pre enable NFC divider fail\n"); + goto err_nand_clk; } =20 - ret =3D clk_prepare_enable(nfc->phase_rx); - if (ret) { - dev_err(nfc->dev, "failed to enable RX clock\n"); - goto err_phase_rx; - } - - ret =3D clk_set_rate(nfc->device_clk, 24000000); + ret =3D clk_set_rate(nfc->nand_clk, 24000000); if (ret) - goto err_disable_rx; + goto err_disable_clk; =20 return 0; =20 -err_disable_rx: - clk_disable_unprepare(nfc->phase_rx); -err_phase_rx: - clk_disable_unprepare(nfc->phase_tx); -err_phase_tx: +err_disable_clk: + clk_disable_unprepare(nfc->nand_clk); +err_nand_clk: clk_disable_unprepare(nfc->device_clk); err_device_clk: clk_disable_unprepare(nfc->core_clk); @@ -1061,8 +1064,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) =20 static void meson_nfc_disable_clk(struct meson_nfc *nfc) { - clk_disable_unprepare(nfc->phase_rx); - clk_disable_unprepare(nfc->phase_tx); + clk_disable_unprepare(nfc->nand_clk); clk_disable_unprepare(nfc->device_clk); clk_disable_unprepare(nfc->core_clk); } @@ -1374,7 +1376,6 @@ static int meson_nfc_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct meson_nfc *nfc; - struct resource *res; int ret, irq; =20 nfc =3D devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); @@ -1388,21 +1389,15 @@ static int meson_nfc_probe(struct platform_device *= pdev) nand_controller_init(&nfc->controller); INIT_LIST_HEAD(&nfc->chips); init_completion(&nfc->completion); - nfc->dev =3D dev; =20 - res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - nfc->reg_base =3D devm_ioremap_resource(dev, res); + nfc->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "nfc"); if (IS_ERR(nfc->reg_base)) return PTR_ERR(nfc->reg_base); =20 - nfc->reg_clk =3D - syscon_regmap_lookup_by_phandle(dev->of_node, - "amlogic,mmc-syscon"); - if (IS_ERR(nfc->reg_clk)) { - dev_err(dev, "Failed to lookup clock base\n"); - return PTR_ERR(nfc->reg_clk); - } + nfc->sd_emmc_clock =3D devm_platform_ioremap_resource_byname(pdev, "emmc"= ); + if (IS_ERR(nfc->sd_emmc_clock)) + return PTR_ERR(nfc->sd_emmc_clock); =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) --=20 2.34.1 From nobody Fri Jun 19 14:37:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3A04C433EF for ; Sat, 2 Apr 2022 07:49:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353884AbiDBHvf (ORCPT ); Sat, 2 Apr 2022 03:51:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244824AbiDBHvV (ORCPT ); Sat, 2 Apr 2022 03:51:21 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A01B3369FB for ; Sat, 2 Apr 2022 00:49:30 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Sat, 2 Apr 2022 15:49:30 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , Subject: [PATCH v4 2/2] dt-bindings: nand: meson: refine Amlogic NAND controller driver Date: Sat, 2 Apr 2022 15:49:20 +0800 Message-ID: <20220402074921.13316-3-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220402074921.13316-1-liang.yang@amlogic.com> References: <20220402074921.13316-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" convert txt to yaml and refine the meson NFC clock document. Signed-off-by: Liang Yang --- .../bindings/mtd/amlogic,meson-nand.txt | 60 -------------- .../bindings/mtd/amlogic,meson-nand.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nan= d.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nan= d.yaml diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b= /Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5794ab1147c1..000000000000 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,60 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic= bindings. - -Example demonstrate on AXG SoC: - - sd_emmc_c_clkc: mmc@7000 { - compatible =3D "amlogic,meson-axg-mmc-clkc", "syscon"; - reg =3D <0x0 0x7000 0x0 0x800>; - }; - - nand-controller@7800 { - compatible =3D "amlogic,meson-axg-nfc"; - reg =3D <0x0 0x7800 0x0 0x100>; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - - clocks =3D <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names =3D "core", "device", "rx", "tx"; - amlogic,mmc-syscon =3D <&sd_emmc_c_clkc>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins>; - - nand@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml = b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 000000000000..965a2dd20645 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - "amlogic,meson-gxl-nfc" + - "amlogic,meson-axg-nfc" + + reg: + maxItems: 2 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg-names: + items: + - const: nfc + - const: emmc + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: device + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - reg-names + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + nand-controller@7800 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "amlogic,meson-axg-nfc"; + reg =3D <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names =3D "nfc", "emmc"; + + interrupts =3D ; + clocks =3D <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_FCLK_DIV2>; + clock-names =3D "core", "device"; + + }; + }; +... --=20 2.34.1