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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id c69-20020a633548000000b0038554192b91sm3179858pga.38.2022.04.01.13.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 13:08:08 -0700 (PDT) Subject: [PATCH v2] dt-bindings: Fix phandle-array issues in the idle-states bindings Date: Fri, 1 Apr 2022 12:59:19 -0700 Message-Id: <20220401195919.17493-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: robh+dt@kernel.org, Palmer Dabbelt , anup@brainfault.org, guoren@kernel.org, lorenzo.pieralisi@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: Rob Herring Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Palmer Dabbelt As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new RISC-V idle-states bindings to comply with the schema. Signed-off-by: Palmer Dabbelt --- Changes since v1: * Only fix the RISC-V bindings, to avoid a merge conflict. --- .../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Docum= entation/devicetree/bindings/cpu/idle-states.yaml index 95506ffb816c..0e89c469d0fc 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -719,8 +719,8 @@ examples: reg =3D <0x0>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states =3D <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; =20 cpu_intc0: interrupt-controller { #interrupt-cells =3D <1>; @@ -735,8 +735,8 @@ examples: reg =3D <0x1>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states =3D <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; =20 cpu_intc1: interrupt-controller { #interrupt-cells =3D <1>; @@ -751,8 +751,8 @@ examples: reg =3D <0x10>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states =3D <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; =20 cpu_intc10: interrupt-controller { #interrupt-cells =3D <1>; @@ -767,8 +767,8 @@ examples: reg =3D <0x11>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states =3D <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; =20 cpu_intc11: interrupt-controller { #interrupt-cells =3D <1>; --=20 2.34.1