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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id o22-20020a056a0015d600b004fb03c903c3sm4212080pfu.71.2022.04.01.12.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 12:32:42 -0700 (PDT) Subject: [PATCH] dt-bindings: Fix phandle-array issues in the idle-states bindings Date: Fri, 1 Apr 2022 12:31:08 -0700 Message-Id: <20220401193108.12490-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: robh+dt@kernel.org, Palmer Dabbelt , anup@brainfault.org, guoren@kernel.org, lorenzo.pieralisi@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: Rob Herring Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Palmer Dabbelt As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new generic idle-states bindings to comply with the schema. Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V i= dle states") Signed-off-by: Palmer Dabbelt --- .../devicetree/bindings/cpu/idle-states.yaml | 96 +++++++++---------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Docum= entation/devicetree/bindings/cpu/idle-states.yaml index 95506ffb816c..6f5223659950 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -385,8 +385,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x0>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@1 { @@ -394,8 +394,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x1>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@100 { @@ -403,8 +403,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@101 { @@ -412,8 +412,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@10000 { @@ -421,8 +421,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x10000>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@10001 { @@ -430,8 +430,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x10001>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@10100 { @@ -439,8 +439,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x10100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@10101 { @@ -448,8 +448,8 @@ examples: compatible =3D "arm,cortex-a57"; reg =3D <0x0 0x10101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; }; =20 cpu@100000000 { @@ -457,8 +457,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x0>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100000001 { @@ -466,8 +466,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x1>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100000100 { @@ -475,8 +475,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100000101 { @@ -484,8 +484,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100010000 { @@ -493,8 +493,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x10000>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100010001 { @@ -502,8 +502,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x10001>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100010100 { @@ -511,8 +511,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x10100>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 cpu@100010101 { @@ -520,8 +520,8 @@ examples: compatible =3D "arm,cortex-a53"; reg =3D <0x1 0x10101>; enable-method =3D "psci"; - cpu-idle-states =3D <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; + cpu-idle-states =3D <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; }; =20 idle-states { @@ -615,56 +615,56 @@ examples: device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0x0>; - cpu-idle-states =3D <&cpu_sleep_0_0 &cluster_sleep_0>; + cpu-idle-states =3D <&cpu_sleep_0_0>, <&cluster_sleep_0>; }; =20 cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0x1>; - cpu-idle-states =3D <&cpu_sleep_0_0 &cluster_sleep_0>; + cpu-idle-states =3D <&cpu_sleep_0_0>, <&cluster_sleep_0>; }; =20 cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0x2>; - cpu-idle-states =3D <&cpu_sleep_0_0 &cluster_sleep_0>; + cpu-idle-states =3D <&cpu_sleep_0_0>, <&cluster_sleep_0>; }; =20 cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0x3>; - cpu-idle-states =3D <&cpu_sleep_0_0 &cluster_sleep_0>; + cpu-idle-states =3D <&cpu_sleep_0_0>, <&cluster_sleep_0>; }; =20 cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x100>; - cpu-idle-states =3D <&cpu_sleep_1_0 &cluster_sleep_1>; + cpu-idle-states =3D <&cpu_sleep_1_0>, <&cluster_sleep_1>; }; =20 cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x101>; - cpu-idle-states =3D <&cpu_sleep_1_0 &cluster_sleep_1>; + cpu-idle-states =3D <&cpu_sleep_1_0>, <&cluster_sleep_1>; }; =20 cpu@102 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x102>; - cpu-idle-states =3D <&cpu_sleep_1_0 &cluster_sleep_1>; + cpu-idle-states =3D <&cpu_sleep_1_0>, <&cluster_sleep_1>; }; =20 cpu@103 { device_type =3D "cpu"; compatible =3D "arm,cortex-a7"; reg =3D <0x103>; - cpu-idle-states =3D <&cpu_sleep_1_0 &cluster_sleep_1>; + cpu-idle-states =3D <&cpu_sleep_1_0>, <&cluster_sleep_1>; }; =20 idle-states { @@ -719,8 +719,8 @@ examples: reg =3D <0x0>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states =3D <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; =20 cpu_intc0: interrupt-controller { #interrupt-cells =3D <1>; @@ -735,8 +735,8 @@ examples: reg =3D <0x1>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states =3D <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; =20 cpu_intc1: interrupt-controller { #interrupt-cells =3D <1>; @@ -751,8 +751,8 @@ examples: reg =3D <0x10>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states =3D <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; =20 cpu_intc10: interrupt-controller { #interrupt-cells =3D <1>; @@ -767,8 +767,8 @@ examples: reg =3D <0x11>; riscv,isa =3D "rv64imafdc"; mmu-type =3D "riscv,sv48"; - cpu-idle-states =3D <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states =3D <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; =20 cpu_intc11: interrupt-controller { #interrupt-cells =3D <1>; --=20 2.34.1