From nobody Sun Sep 22 06:26:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9A03C4332F for ; Fri, 1 Apr 2022 05:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245102AbiDAFcz (ORCPT ); Fri, 1 Apr 2022 01:32:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234998AbiDAFcx (ORCPT ); Fri, 1 Apr 2022 01:32:53 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 327E93A1B5; Thu, 31 Mar 2022 22:31:00 -0700 (PDT) X-UUID: ce8d35dc7fbf46308f63b481d3a9c5fc-20220401 X-UUID: ce8d35dc7fbf46308f63b481d3a9c5fc-20220401 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 594310020; Fri, 01 Apr 2022 13:30:55 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 1 Apr 2022 13:30:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 1 Apr 2022 13:30:54 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH 1/1] arm64: dts: mt8192: Add mmc device nodes Date: Fri, 1 Apr 2022 13:30:52 +0800 Message-ID: <20220401053052.2160-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220401053052.2160-1-allen-kh.cheng@mediatek.com> References: <20220401053052.2160-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mmc nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a6da7b04b9d4..23eb92057cb9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -989,6 +989,39 @@ compatible =3D "mediatek,mt8192-msdc"; reg =3D <0 0x11f60000 0 0x1000>; #clock-cells =3D <1>; + status =3D "disabled"; + }; + + mmc0: mmc@11f60000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status =3D "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status =3D "disabled"; }; =20 mfgcfg: clock-controller@13fbf000 { --=20 2.18.0