From nobody Fri Jun 19 17:04:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 747BDC433EF for ; Thu, 31 Mar 2022 14:11:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237369AbiCaONn (ORCPT ); Thu, 31 Mar 2022 10:13:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233212AbiCaONl (ORCPT ); Thu, 31 Mar 2022 10:13:41 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBD9F214043 for ; Thu, 31 Mar 2022 07:11:52 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 22VEBVBK020022; Thu, 31 Mar 2022 09:11:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1648735891; bh=ZDdSKsPCwWPCWqcIz0i8RFY6FrZTU5tHLq0iTroiyhg=; h=From:To:CC:Subject:Date; b=bGqElQVSJtbwIzkzitM96B3StQlVSVMx2R+YBnvUzw2Wy2qwzXQGiaWF4oCeKHxIt cz1VTA659gAR3+mns/hIs7xBYkGsFtNftmrRjCdSAAb3g85SGgS/+i2L5w22oWvIRA afmcDPyKeoYRjc38fuXwfkLufnARhVrSoT1MU1WI= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 22VEBV61004507 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 31 Mar 2022 09:11:31 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 31 Mar 2022 09:11:30 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 31 Mar 2022 09:11:30 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 22VEBTru097691; Thu, 31 Mar 2022 09:11:30 -0500 From: Rahul T R To: , , , , , , CC: , , , , , , , , Subject: [PATCH v3] arm64: defconfig: Enable configs for DisplayPort on J721e Date: Thu, 31 Mar 2022 19:41:13 +0530 Message-ID: <20220331141113.15747-1-r-ravikumar@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable DRM and PHY configs required for supporting DisplayPort on J721e Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- Notes: v2: Fixed the places using savedefconfig Added more info in notes v3: rebased to next-20220330 No change in vmlinux: add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Function old new delta Total: Before=3D24042991, After=3D24042991, chg +0.00% boot logs: https://gist.githubusercontent.com/ravi-rahul/1bdbc3f77ab381e486c83= 94650c2e85d/raw/f04584c30181821c4ee83aee7781a9ba143cd3f3/j7_DP_upstream.log arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 813e644b6af1..b5f9fbb054fa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -742,6 +742,7 @@ CONFIG_DRM_THINE_THC63LVD1024=3Dm CONFIG_DRM_TI_SN65DSI86=3Dm CONFIG_DRM_I2C_ADV7511=3Dm CONFIG_DRM_I2C_ADV7511_AUDIO=3Dy +CONFIG_DRM_CDNS_MHDP8546=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm CONFIG_DRM_IMX_DCSS=3Dm @@ -756,6 +757,7 @@ CONFIG_DRM_MESON=3Dm CONFIG_DRM_PL111=3Dm CONFIG_DRM_LIMA=3Dm CONFIG_DRM_PANFROST=3Dm +CONFIG_DRM_TIDSS=3Dm CONFIG_FB=3Dy CONFIG_FB_MODE_HELPERS=3Dy CONFIG_FB_EFI=3Dy @@ -1162,6 +1164,7 @@ CONFIG_RESET_RZG2L_USBPHY_CTRL=3Dy CONFIG_RESET_TI_SCI=3Dy CONFIG_PHY_XGENE=3Dy CONFIG_PHY_SUN4I_USB=3Dy +CONFIG_PHY_CADENCE_TORRENT=3Dm CONFIG_PHY_CADENCE_SIERRA=3Dm CONFIG_PHY_MIXEL_MIPI_DPHY=3Dm CONFIG_PHY_FSL_IMX8M_PCIE=3Dy --=20 2.17.1