From nobody Sun Sep 22 07:31:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C26FC433F5 for ; Wed, 30 Mar 2022 13:39:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346205AbiC3Nkm (ORCPT ); Wed, 30 Mar 2022 09:40:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346138AbiC3NkT (ORCPT ); Wed, 30 Mar 2022 09:40:19 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6EB815FD0; Wed, 30 Mar 2022 06:38:33 -0700 (PDT) X-UUID: 706d24e3b87c450687c2a0842ac145b6-20220330 X-UUID: 706d24e3b87c450687c2a0842ac145b6-20220330 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1649239239; Wed, 30 Mar 2022 21:38:29 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 30 Mar 2022 21:38:28 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Mar 2022 21:38:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Mar 2022 21:38:27 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v5 4/4] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Wed, 30 Mar 2022 21:38:16 +0800 Message-ID: <20220330133816.30806-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220330133816.30806-1-allen-kh.cheng@mediatek.com> References: <20220330133816.30806-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 3d61238fb102..0b2b52a8f5ed 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1115,6 +1115,66 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: vcodec-dec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x16000000 0 0x26000>; + + vcodec_lat: vcodec-lat@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0x0 0x10000 0 0x800>; /* VDEC_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec-core@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0