From nobody Sun Sep 22 06:38:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFA7EC433FE for ; Wed, 30 Mar 2022 09:45:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244996AbiC3Jrj (ORCPT ); Wed, 30 Mar 2022 05:47:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234740AbiC3Jrh (ORCPT ); Wed, 30 Mar 2022 05:47:37 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FBEA2662F5; Wed, 30 Mar 2022 02:45:47 -0700 (PDT) X-UUID: 589ab17707314a6b8f0e9d25b48e3de7-20220330 X-UUID: 589ab17707314a6b8f0e9d25b48e3de7-20220330 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 935325934; Wed, 30 Mar 2022 17:45:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Mar 2022 17:45:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Mar 2022 17:45:40 +0800 From: Tinghan Shen To: Chaotian Jing , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Wenbin Mei CC: , , , , , , , , , Tinghan Shen Subject: [PATCH v13 1/2] dt-bindings: mmc: mtk-sd: increase reg items Date: Wed, 30 Mar 2022 17:45:31 +0800 Message-ID: <20220330094532.21721-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20220330094532.21721-1-tinghan.shen@mediatek.com> References: <20220330094532.21721-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek has a new version of mmc IP since mt8183. Some IO registers are moved to top to improve hardware design and named as "host top registers". Add host top register in the reg binding description for mt8183 and successors. Signed-off-by: Wenbin Mei Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentat= ion/devicetree/bindings/mmc/mtk-sd.yaml index 297ada03e3de..2a2e9fa8c188 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -40,7 +40,10 @@ properties: - const: mediatek,mt8183-mmc =20 reg: - maxItems: 1 + minItems: 1 + items: + - description: base register (required). + - description: top base register (required for MT8183). =20 clocks: description: @@ -168,6 +171,16 @@ required: - vmmc-supply - vqmmc-supply =20 +if: + properties: + compatible: + contains: + const: mediatek,mt8183-mmc +then: + properties: + reg: + minItems: 2 + unevaluatedProperties: false =20 examples: --=20 2.18.0 From nobody Sun Sep 22 06:38:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEC31C4321E for ; Wed, 30 Mar 2022 09:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245019AbiC3Jrq (ORCPT ); Wed, 30 Mar 2022 05:47:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244997AbiC3Jrl (ORCPT ); Wed, 30 Mar 2022 05:47:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C86F2662EF; Wed, 30 Mar 2022 02:45:48 -0700 (PDT) X-UUID: b05007d62c244e2185ee16e89a4a19e2-20220330 X-UUID: b05007d62c244e2185ee16e89a4a19e2-20220330 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1768894978; Wed, 30 Mar 2022 17:45:42 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 30 Mar 2022 17:45:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Mar 2022 17:45:40 +0800 From: Tinghan Shen To: Chaotian Jing , Ulf Hansson , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , AngeloGioacchino Del Regno , Wenbin Mei CC: , , , , , , , , , Tinghan Shen , Seiya Wang Subject: [PATCH v13 2/2] arm64: dts: Add mediatek SoC mt8195 and evaluation board Date: Wed, 30 Mar 2022 17:45:32 +0800 Message-ID: <20220330094532.21721-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20220330094532.21721-1-tinghan.shen@mediatek.com> References: <20220330094532.21721-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add basic chip support for mediatek mt8195. Signed-off-by: Seiya Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++ 3 files changed, 1219 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 8c1e18032f9f..5da29e7223e4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000000..76b5aaad7263 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model =3D "MediaTek MT8195 evaluation board"; + compatible =3D "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; +}; + +&auxadc { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pin>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pin>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pin>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pin>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&nor_flash { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + }; +}; + +&pio { + i2c0_pin: i2c0-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + mediatek,drive-strength-adv =3D <0>; + drive-strength =3D <6>; + }; + }; + + i2c1_pin: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + mediatek,drive-strength-adv =3D <0>; + drive-strength =3D <6>; + }; + }; + + i2c4_pin: i2c4-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + mediatek,drive-strength-adv =3D <7>; + }; + }; + + i2c6_pin: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c7_pin: i2c7-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + nor_pins_default: nor-pins { + pins0 { + pinmux =3D , + , + ; + bias-pull-down; + }; + + pins1 { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + uart0_pin: uart0-pins { + pins { + pinmux =3D , + ; + }; + }; +}; + +&u3phy0 { + status=3D"okay"; +}; + +&u3phy1 { + status=3D"okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pin>; + status =3D "okay"; +}; + +&xhci0 { + status =3D "okay"; +}; + +&xhci1 { + status =3D "okay"; +}; + +&xhci2 { + status =3D "okay"; +}; + +&xhci3 { + /* This controller is connected with a BT device. + * Disable usb2 lpm to prevent known issues. + */ + usb2-lpm-disable; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi new file mode 100644 index 000000000000..b57e620c2c72 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,1045 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8195"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + clock-frequency =3D <1701000000>; + capacity-dmips-mhz =3D <578>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + clock-frequency =3D <1701000000>; + capacity-dmips-mhz =3D <578>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + clock-frequency =3D <1701000000>; + capacity-dmips-mhz =3D <578>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + clock-frequency =3D <1701000000>; + capacity-dmips-mhz =3D <578>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x400>; + enable-method =3D "psci"; + clock-frequency =3D <2171000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x500>; + enable-method =3D "psci"; + clock-frequency =3D <2171000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + clock-frequency =3D <2171000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + clock-frequency =3D <2171000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <95>; + min-residency-us =3D <580>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <45>; + exit-latency-us =3D <140>; + min-residency-us =3D <740>; + }; + + cluster_off_l: cluster-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010002>; + local-timer-stop; + entry-latency-us =3D <55>; + exit-latency-us =3D <155>; + min-residency-us =3D <840>; + }; + + cluster_off_b: cluster-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010002>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <200>; + min-residency-us =3D <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + }; + }; + + dsu-pmu { + compatible =3D "arm,dsu-pmu"; + interrupts =3D ; + cpus =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + clk26m: oscillator-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk32k: oscillator-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "clk32k"; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + #redistributor-regions =3D <1>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8195-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible =3D "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + + infracfg_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + ti,reset-bits =3D < + 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pc= ie */ + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ + 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* sv= s gpu */ + >; + }; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8195-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8195-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11eb0000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names =3D "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 144>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + watchdog: watchdog@10007000 { + compatible =3D "mediatek,mt8195-wdt", + "mediatek,mt6589-wdt"; + reg =3D <0 0x10007000 0 0x100>; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8195-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + systimer: timer@10017000 { + compatible =3D "mediatek,mt8195-timer", + "mediatek,mt6765-timer"; + reg =3D <0 0x10017000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_CLK26M_D2>; + }; + + pwrap: pwrap@10024000 { + compatible =3D "mediatek,mt8195-pwrap", "syscon"; + reg =3D <0 0x10024000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names =3D "spi", "wrap"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + + scp_adsp: clock-controller@10720000 { + compatible =3D "mediatek,mt8195-scp_adsp"; + reg =3D <0 0x10720000 0 0x1000>; + #clock-cells =3D <1>; + }; + + uart0: serial@11001100 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001100 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart1: serial@11001200 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001200 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart2: serial@11001300 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001300 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart3: serial@11001400 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001400 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart4: serial@11001500 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001500 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart5: serial@11001600 { + compatible =3D "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11001600 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible =3D "mediatek,mt8195-auxadc", + "mediatek,mt8173-auxadc"; + reg =3D <0 0x11002000 0 0x1000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + pericfg_ao: syscon@11003000 { + compatible =3D "mediatek,mt8195-pericfg_ao", "syscon"; + reg =3D <0 0x11003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + spi0: spi@1100a000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100a000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi1: spi@11010000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi2: spi@11012000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11012000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi3: spi@11013000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11013000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi4: spi@11018000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11018000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi5: spi@11019000 { + compatible =3D "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11019000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spis0: spi@1101d000 { + compatible =3D "mediatek,mt8195-spi-slave"; + reg =3D <0 0x1101d000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SPIS0>; + clock-names =3D "spi"; + assigned-clocks =3D <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + status =3D "disabled"; + }; + + spis1: spi@1101e000 { + compatible =3D "mediatek,mt8195-spi-slave"; + reg =3D <0 0x1101e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SPIS1>; + clock-names =3D "spi"; + assigned-clocks =3D <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + status =3D "disabled"; + }; + + xhci0: usb@11200000 { + compatible =3D "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL_D2>; + status =3D "disabled"; + }; + + mmc2: mmc@11250000 { + compatible =3D "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; + clock-names =3D "source", "hclk", "source_cg"; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL_D2>; + status =3D "disabled"; + }; + + xhci1: usb@11290000 { + compatible =3D "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP_1P>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&topckgen CLK_TOP_SSUSB_P1_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + status =3D "disabled"; + }; + + xhci2: usb@112a0000 { + compatible =3D "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port2 PHY_TYPE_USB2>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP_2P>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&topckgen CLK_TOP_SSUSB_P2_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "xhci_ck"; + status =3D "disabled"; + }; + + xhci3: usb@112b0000 { + compatible =3D "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port3 PHY_TYPE_USB2>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP_3P>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&topckgen CLK_TOP_SSUSB_P3_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "xhci_ck"; + status =3D "disabled"; + }; + + nor_flash: spi@1132c000 { + compatible =3D "mediatek,mt8195-nor", + "mediatek,mt8173-nor"; + reg =3D <0 0x1132c000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SPINOR>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names =3D "spi", "sf", "axi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + u3phy2: t-phy@11c40000 { + compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x11c40000 0x700>; + status =3D "disabled"; + + u2port2: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u3phy3: t-phy@11c50000 { + compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x11c50000 0x700>; + status =3D "disabled"; + + u2port3: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + i2c5: i2c@11d00000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11d00000 0 0x1000>, + <0 0x10220580 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@11d01000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11d01000 0 0x1000>, + <0 0x10220600 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@11d02000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11d02000 0 0x1000>, + <0 0x10220680 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_s: clock-controller@11d03000 { + compatible =3D "mediatek,mt8195-imp_iic_wrap_s"; + reg =3D <0 0x11d03000 0 0x1000>; + #clock-cells =3D <1>; + }; + + i2c0: i2c@11e00000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11e00000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + }; + + i2c1: i2c@11e01000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11e01000 0 0x1000>, + <0 0x10220200 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11e02000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11e02000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@11e03000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11e03000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@11e04000 { + compatible =3D "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg =3D <0 0x11e04000 0 0x1000>, + <0 0x10220500 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e05000 { + compatible =3D "mediatek,mt8195-imp_iic_wrap_w"; + reg =3D <0 0x11e05000 0 0x1000>; + #clock-cells =3D <1>; + }; + + u3phy1: t-phy@11e30000 { + compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x11e30000 0xe00>; + status =3D "disabled"; + + u2port1: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, + <&clk26m>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u3port1: usb-phy@700 { + reg =3D <0x700 0x700>; + clocks =3D <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + + u3phy0: t-phy@11e40000 { + compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x11e40000 0xe00>; + status =3D "disabled"; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&clk26m>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u3port0: usb-phy@700 { + reg =3D <0x700 0x700>; + clocks =3D <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + + ufsphy: ufs-phy@11fa0000 { + compatible =3D "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg =3D <0 0x11fa0000 0 0xc000>; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "unipro", "mp"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible =3D "mediatek,mt8195-mfgcfg"; + reg =3D <0 0x13fbf000 0 0x1000>; + #clock-cells =3D <1>; + }; + + wpesys: clock-controller@14e00000 { + compatible =3D "mediatek,mt8195-wpesys"; + reg =3D <0 0x14e00000 0 0x1000>; + #clock-cells =3D <1>; + }; + + wpesys_vpp0: clock-controller@14e02000 { + compatible =3D "mediatek,mt8195-wpesys_vpp0"; + reg =3D <0 0x14e02000 0 0x1000>; + #clock-cells =3D <1>; + }; + + wpesys_vpp1: clock-controller@14e03000 { + compatible =3D "mediatek,mt8195-wpesys_vpp1"; + reg =3D <0 0x14e03000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys: clock-controller@15000000 { + compatible =3D "mediatek,mt8195-imgsys"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1_dip_top: clock-controller@15110000 { + compatible =3D "mediatek,mt8195-imgsys1_dip_top"; + reg =3D <0 0x15110000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1_dip_nr: clock-controller@15130000 { + compatible =3D "mediatek,mt8195-imgsys1_dip_nr"; + reg =3D <0 0x15130000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1_wpe: clock-controller@15220000 { + compatible =3D "mediatek,mt8195-imgsys1_wpe"; + reg =3D <0 0x15220000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ipesys: clock-controller@15330000 { + compatible =3D "mediatek,mt8195-ipesys"; + reg =3D <0 0x15330000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys: clock-controller@16000000 { + compatible =3D "mediatek,mt8195-camsys"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawa: clock-controller@1604f000 { + compatible =3D "mediatek,mt8195-camsys_rawa"; + reg =3D <0 0x1604f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_yuva: clock-controller@1606f000 { + compatible =3D "mediatek,mt8195-camsys_yuva"; + reg =3D <0 0x1606f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawb: clock-controller@1608f000 { + compatible =3D "mediatek,mt8195-camsys_rawb"; + reg =3D <0 0x1608f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_yuvb: clock-controller@160af000 { + compatible =3D "mediatek,mt8195-camsys_yuvb"; + reg =3D <0 0x160af000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_mraw: clock-controller@16140000 { + compatible =3D "mediatek,mt8195-camsys_mraw"; + reg =3D <0 0x16140000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ccusys: clock-controller@17200000 { + compatible =3D "mediatek,mt8195-ccusys"; + reg =3D <0 0x17200000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys_soc: clock-controller@1800f000 { + compatible =3D "mediatek,mt8195-vdecsys_soc"; + reg =3D <0 0x1800f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys: clock-controller@1802f000 { + compatible =3D "mediatek,mt8195-vdecsys"; + reg =3D <0 0x1802f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys_core1: clock-controller@1803f000 { + compatible =3D "mediatek,mt8195-vdecsys_core1"; + reg =3D <0 0x1803f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + apusys_pll: clock-controller@190f3000 { + compatible =3D "mediatek,mt8195-apusys_pll"; + reg =3D <0 0x190f3000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vencsys: clock-controller@1a000000 { + compatible =3D "mediatek,mt8195-vencsys"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vencsys_core1: clock-controller@1b000000 { + compatible =3D "mediatek,mt8195-vencsys_core1"; + reg =3D <0 0x1b000000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.18.0