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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id t19-20020a056402525300b0041952a1a764sm8510909edd.33.2022.03.29.04.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:29:07 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] ARM: dts: qcom: ipq4019: align dmas in SPI with DT schema Date: Tue, 29 Mar 2022 13:28:59 +0200 Message-Id: <20220329112902.252937-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> References: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski Acked-by: Kuldeep Singh --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index a9d0566a3190..dc8260684aee 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -253,8 +253,8 @@ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ clock-names =3D "core", "iface"; #address-cells =3D <1>; #size-cells =3D <0>; - dmas =3D <&blsp_dma 5>, <&blsp_dma 4>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 4>, <&blsp_dma 5>; + dma-names =3D "tx", "rx"; status =3D "disabled"; }; =20 @@ -267,8 +267,8 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ clock-names =3D "core", "iface"; #address-cells =3D <1>; #size-cells =3D <0>; - dmas =3D <&blsp_dma 7>, <&blsp_dma 6>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 6>, <&blsp_dma 7>; + dma-names =3D "tx", "rx"; status =3D "disabled"; }; =20 --=20 2.32.0 From nobody Sun Jun 21 10:22:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A47C433F5 for ; Tue, 29 Mar 2022 11:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235828AbiC2La6 (ORCPT ); Tue, 29 Mar 2022 07:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232359AbiC2Lax (ORCPT ); Tue, 29 Mar 2022 07:30:53 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD863215919 for ; Tue, 29 Mar 2022 04:29:10 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id b24so20305702edu.10 for ; Tue, 29 Mar 2022 04:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oeY2VwpzFpq+ahpdKff0SvoKtIxVNW39tqhBA+XG7Pw=; b=E3iUpWr4K4oxsFdairIy8IPoKPb8A5Z9Rslrnt5uD7TA7OjHlP6XEs0leXi7BYmlBB fX/Gywja0ECNstL71d5ys63cDrvYqHdvg+7kHSQiJo4AqCViS54TzaSWPvdBlkqhwTDt VzO0T/Kn2Kn7IK3KDtSczaWwM3FNeXyRb5h8ABt+mZnlSEnueTR3vgruqeBSfo62E8Fi /aqtKuwk6/wBo+dTHNsEfFzth4cIOiBH8drVIleVLMNjGnnSBCXrf7nvK4gWyV8rwb6v pOrs9FchbOYtiKniYqdpSM0gEeWeqR1sPo2wBPy21TAYL34bM9oaDqM1lI5uSnDPSJNR 3XJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oeY2VwpzFpq+ahpdKff0SvoKtIxVNW39tqhBA+XG7Pw=; b=Q9ugvRXsmbDeLVckJKB1sPkcUI4t41RwULcTK5mY+QpFoONKdL2Of8dOtZTV1hknb3 ts7oQtRnmJsCKUaUqL2IVYMzC4kxu3ncflUVKrAQrfLkO2IqIO77xIqyhAy5AVBRF0Dv JZSDRYunNqOuyZskVI7qR8+g0q9IwpYjf4c188HTe8gikXwakgNgpNZ3BDmqjfOi90wE 58LgUF9d4FyOAxaax+yitLqEVGMgX9KctCjxbG0k9mst92vHLYXSele/h7NlZlSgCKkh 0Uf4hvLueGUHjgqrgm6hdvXzRrLaA0jNsLnOL7TXVj2SM15Fm0NqG2Q/0K8zd1qLL3V7 S5GA== X-Gm-Message-State: AOAM531L7voQQJBIX3varw3vlGNqHK2oVISkG7nC76c/hAbSj2blIfHo yvKVVNSU8o81Kz2eruP/X83yRXVDDZR49hPZ X-Google-Smtp-Source: ABdhPJyL9/o3X64nZeOHCAVP2P8R0/sQb/sL5/MrwdEeHc4B16wUTFqJuM59hyR60G29ny1CUz4JXg== X-Received: by 2002:a05:6402:34c4:b0:419:e00e:64c1 with SMTP id w4-20020a05640234c400b00419e00e64c1mr3978193edc.88.1648553349028; Tue, 29 Mar 2022 04:29:09 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id t19-20020a056402525300b0041952a1a764sm8510909edd.33.2022.03.29.04.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:29:08 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: qcom: msm8916: align dmas in SPI with DT schema Date: Tue, 29 Mar 2022 13:29:00 +0200 Message-Id: <20220329112902.252937-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> References: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski Acked-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index e34963505e07..6e5e7883c747 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1529,8 +1529,8 @@ blsp_spi1: spi@78b5000 { clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 5>, <&blsp_dma 4>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 4>, <&blsp_dma 5>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi1_default>; pinctrl-1 =3D <&spi1_sleep>; @@ -1561,8 +1561,8 @@ blsp_spi2: spi@78b6000 { clocks =3D <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 7>, <&blsp_dma 6>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 6>, <&blsp_dma 7>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi2_default>; pinctrl-1 =3D <&spi2_sleep>; @@ -1593,8 +1593,8 @@ blsp_spi3: spi@78b7000 { clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 9>, <&blsp_dma 8>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 8>, <&blsp_dma 9>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi3_default>; pinctrl-1 =3D <&spi3_sleep>; @@ -1625,8 +1625,8 @@ blsp_spi4: spi@78b8000 { clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 11>, <&blsp_dma 10>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 10>, <&blsp_dma 11>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi4_default>; pinctrl-1 =3D <&spi4_sleep>; @@ -1657,8 +1657,8 @@ blsp_spi5: spi@78b9000 { clocks =3D <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 13>, <&blsp_dma 12>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 12>, <&blsp_dma 13>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi5_default>; pinctrl-1 =3D <&spi5_sleep>; @@ -1689,8 +1689,8 @@ blsp_spi6: spi@78ba000 { clocks =3D <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names =3D "core", "iface"; - dmas =3D <&blsp_dma 15>, <&blsp_dma 14>; - dma-names =3D "rx", "tx"; + dmas =3D <&blsp_dma 14>, <&blsp_dma 15>; + dma-names =3D "tx", "rx"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi6_default>; pinctrl-1 =3D <&spi6_sleep>; --=20 2.32.0 From nobody Sun Jun 21 10:22:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B075CC433F5 for ; Tue, 29 Mar 2022 11:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235843AbiC2LbC (ORCPT ); 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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id t19-20020a056402525300b0041952a1a764sm8510909edd.33.2022.03.29.04.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:29:09 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: qcom: qcs404: align clocks in SPI with DT schema Date: Tue, 29 Mar 2022 13:29:01 +0200 Message-Id: <20220329112902.252937-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> References: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DT schema expects clocks core-iface order. No functional change. Signed-off-by: Krzysztof Kozlowski Acked-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index 3f06f7cd3cf2..4af5065e830b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x078b5000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp1_spi0_default>; #address-cells =3D <1>; @@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x078b6000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp1_spi1_default>; #address-cells =3D <1>; @@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x078b7000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp1_spi2_default>; #address-cells =3D <1>; @@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x078b8000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp1_spi3_default>; #address-cells =3D <1>; @@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x078b9000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp1_spi4_default>; #address-cells =3D <1>; @@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 { compatible =3D "qcom,spi-qup-v2.2.1"; reg =3D <0x07af5000 0x600>; interrupts =3D ; - clocks =3D <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names =3D "iface", "core"; + clocks =3D <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; pinctrl-names =3D "default"; pinctrl-0 =3D <&blsp2_spi0_default>; #address-cells =3D <1>; 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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id t19-20020a056402525300b0041952a1a764sm8510909edd.33.2022.03.29.04.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 04:29:10 -0700 (PDT) From: Krzysztof Kozlowski To: linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Mark Brown , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] spi: dt-bindings: qcom,spi-qup: convert to dtschema Date: Tue, 29 Mar 2022 13:29:02 +0200 Message-Id: <20220329112902.252937-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> References: <20220329112902.252937-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. Signed-off-by: Krzysztof Kozlowski Acked-by: Kuldeep Singh --- .../devicetree/bindings/spi/qcom,spi-qup.txt | 103 ------------------ .../devicetree/bindings/spi/qcom,spi-qup.yaml | 82 ++++++++++++++ 2 files changed, 82 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Docum= entation/devicetree/bindings/spi/qcom,spi-qup.txt deleted file mode 100644 index 5c090771c016..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ /dev/null @@ -1,103 +0,0 @@ -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP core is an AHB slave that provides a common data path (an output F= IFO -and an input FIFO) for serial peripheral interface (SPI) mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programm= able -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Should contain: - "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. - "qcom,spi-qup-v2.1.1" for 8974 and later - "qcom,spi-qup-v2.2.1" for 8974 v2 and later. - -- reg: Should contain base register location and length -- interrupts: Interrupt number used by this controller - -- clocks: Should contain the core clock and the AHB clock. -- clock-names: Should be "core" for the core clock and "iface" for the - AHB clock. - -- #address-cells: Number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: Should be zero. - -Optional properties: -- spi-max-frequency: Specifies maximum SPI clock frequency, - Units - Hz. Definition as per - Documentation/devicetree/bindings/spi/spi-bus.txt -- num-cs: total number of chipselects -- cs-gpios: should specify GPIOs used for chipselects. - The gpios will be referred to as reg =3D in the SPI child - nodes. If unspecified, a single SPI device without a chip - select can be used. - -- dmas: Two DMA channel specifiers following the convention outlin= ed - in bindings/dma/dma.txt -- dma-names: Names for the dma channels, if present. There must be at - least one channel named "tx" for transmit and named "rx" f= or - receive. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - spi_8: spi@f9964000 { /* BLSP2 QUP2 */ - - compatible =3D "qcom,spi-qup-v2"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0xf9964000 0x1000>; - interrupts =3D <0 102 0>; - spi-max-frequency =3D <19200000>; - - clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names =3D "core", "iface"; - - dmas =3D <&blsp1_bam 13>, <&blsp1_bam 12>; - dma-names =3D "rx", "tx"; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&spi8_default>; - - device@0 { - compatible =3D "arm,pl022-dummy"; - #address-cells =3D <1>; - #size-cells =3D <1>; - reg =3D <0>; /* Chip select 0 */ - spi-max-frequency =3D <19200000>; - spi-cpol; - }; - - device@1 { - compatible =3D "arm,pl022-dummy"; - #address-cells =3D <1>; - #size-cells =3D <1>; - reg =3D <1>; /* Chip select 1 */ - spi-max-frequency =3D <9600000>; - spi-cpha; - }; - - device@2 { - compatible =3D "arm,pl022-dummy"; - #address-cells =3D <1>; - #size-cells =3D <1>; - reg =3D <2>; /* Chip select 2 */ - spi-max-frequency =3D <19200000>; - spi-cpol; - spi-cpha; - }; - - device@3 { - compatible =3D "arm,pl022-dummy"; - #address-cells =3D <1>; - #size-cells =3D <1>; - reg =3D <3>; /* Chip select 3 */ - spi-max-frequency =3D <19200000>; - spi-cpol; - spi-cpha; - spi-cs-high; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Docu= mentation/devicetree/bindings/spi/qcom,spi-qup.yaml new file mode 100644 index 000000000000..aa5756f7ba85 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SP= I) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP core is an AHB slave that provides a common data path (an output= FIFO + and an input FIFO) for serial peripheral interface (SPI) mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol vari= ants. + +allOf: + - $ref: /spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064 + - qcom,spi-qup-v2.1.1 # for 8974 and later + - qcom,spi-qup-v2.2.1 # for 8974 v2 and later + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi@7575000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07575000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_spi1_default>; + pinctrl-1 =3D <&blsp1_spi1_sleep>; + dmas =3D <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; --=20 2.32.0