From nobody Fri Jun 19 20:12:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBD4C433EF for ; Tue, 29 Mar 2022 07:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233423AbiC2HbU (ORCPT ); Tue, 29 Mar 2022 03:31:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233399AbiC2HbP (ORCPT ); Tue, 29 Mar 2022 03:31:15 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 523BF2AE6 for ; Tue, 29 Mar 2022 00:29:32 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id i11so5580476plg.12 for ; Tue, 29 Mar 2022 00:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ppNdA/FhRD9g5++0K+Ya9WXyfU57mPy49sftAdzbp8w=; b=gcxsu0qkGm5afdR5CecI5Kj8Oz6i3fcQWabAOBtFVeKspQqMZnaPQbPXsIka/7QqWP 9OQkwOZjEs6rHriQ+9z/OPi20q/Ls2Pux0FjbNwIgCvCXXYtnsgC8xiERCIKs3aauJZq 2SkeykXVA4WYN1kV0ltpa77beaHtqiG9ZyqBK7s8kixX9iZxBVWaN9lKrwl2GqZmtUiU PjadOpN8iLSAn/qFU3U+L3zUGR+Q1cix9aqfgtreFrCpzQbxt772CqygJoxK1ysRSwVr h1bYIcV2FfMvpzAAkgIhlfwE/JWw3yyDlBi1bjfO7AdG8Ajtx8PEIbh/4N7Bjshf2yVa pheg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ppNdA/FhRD9g5++0K+Ya9WXyfU57mPy49sftAdzbp8w=; b=bj21XY3DXCnLOl3OEf0SY8lFbvwMNALvaVuqn3PbATyRE8bnGGbLMS9ik/g0YWVQ5g NqSwgD0RwYGTpltuYIT8/UIgETMU14NAXoZGIS4fHZ7TMBkiSbw+8CSyujH/tnEyRf6t +hNwuoQv8FMVIppHAZpxisFY4WzJoJTA+ttt7L7tM7QH8dueFyU4MdAeOv4Cb1Cz/ye2 J0Mz/93twFHzcwyuuu36j5CfFzb4bAg8Qk1qdF3gQFoRxC/VXeJ+NcEFeJWIy5JL5fCL +pOSgOQGYDn+svT7uIpwRWwpttR0NJKOb+xpstrxndLv93odm/bq0Er+2K6G4/nicVxL S4Tg== X-Gm-Message-State: AOAM533kcedrU48Kunzv0wnp0xFjvasBR+ZnaMV3EjzBKwQOSt5zTiEa Gor3auiB6AQZUmpBbUA4qjiy5A== X-Google-Smtp-Source: ABdhPJy2ncza1YsBMMpe2gT2oc1Mdzb1vOn0BTJCkEqLNqVWhS3Cu0hZ6v8Sf5pye4QquhPixMb92w== X-Received: by 2002:a17:90b:4b83:b0:1c9:6d37:38b7 with SMTP id lr3-20020a17090b4b8300b001c96d3738b7mr3124696pjb.21.1648538972341; Tue, 29 Mar 2022 00:29:32 -0700 (PDT) Received: from localhost.localdomain ([122.171.166.231]) by smtp.gmail.com with ESMTPSA id z6-20020a056a00240600b004e17ab23340sm19440564pfh.177.2022.03.29.00.29.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 00:29:31 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Albert Ou , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Date: Tue, 29 Mar 2022 12:59:09 +0530 Message-Id: <20220329072911.1692766-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220329072911.1692766-1-apatel@ventanamicro.com> References: <20220329072911.1692766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Supporting hardware updates of PTE A and D bits is optional for any RISC-V implementation so current software strategy is to always set these bits in both G-stage (hypervisor) and VS-stage (guest kernel). If PTE A and D bits are not set by software (hypervisor or guest) then RISC-V implementations not supporting hardware updates of these bits will cause traps even for perfectly valid PTEs. Based on above explanation, the VS-stage page table created by various KVM selftest applications is not correct because PTE A and D bits are not set. This patch fixes VS-stage page table programming of PTE A and D bits for KVM selftests. Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V 64-bit") Signed-off-by: Anup Patel Tested-by: Mayuresh Chitale --- tools/testing/selftests/kvm/include/riscv/processor.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index dc284c6bdbc3..eca5c622efd2 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -101,7 +101,9 @@ static inline void set_reg(struct kvm_vm *vm, uint32_t = vcpuid, uint64_t id, #define PGTBL_PTE_WRITE_SHIFT 2 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL #define PGTBL_PTE_READ_SHIFT 1 -#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \ +#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \ + PGTBL_PTE_DIRTY_MASK | \ + PGTBL_PTE_EXECUTE_MASK | \ PGTBL_PTE_WRITE_MASK | \ PGTBL_PTE_READ_MASK) #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL --=20 2.25.1 From nobody Fri Jun 19 20:12:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 499C9C433F5 for ; Tue, 29 Mar 2022 07:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233463AbiC2Hb2 (ORCPT ); Tue, 29 Mar 2022 03:31:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233399AbiC2HbY (ORCPT ); Tue, 29 Mar 2022 03:31:24 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0C021D315 for ; Tue, 29 Mar 2022 00:29:37 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id mp6-20020a17090b190600b001c6841b8a52so1317121pjb.5 for ; Tue, 29 Mar 2022 00:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0HpwULoTFveWXl4V/JL0uWMQpAlO9P0Ps2jhRe3PZdI=; b=kF8viRN8VFCL1uNo9D6ZUyCgw9eFpyecK3uRGR8wpUQFmHxTfHZFyptqrp5t0lZu06 JFlvhmxASkTOycvxyaHDul06KAd/YihiOZC8edSC3ff6j/40/8pp6+YK383GA9SvQ0U1 td+9tyfhMqXLjIQ7gkcPM+R4LC+xWeOD4B+AJshFKXebhMR+zOOUivCtkd6oH6k3LJU8 YyK1oOWO/cu04eR6ymTj0ZJ41ojlIeG0wP+GOzrN20Na3uEDphlN56znbvx8I2SGzc3g cOfTHjGK3GYZDNodXAjBwVvrSVBr4tqTndpghoEp7OdOnqAy0rZ3ns689yM76MRYlLfR 80mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0HpwULoTFveWXl4V/JL0uWMQpAlO9P0Ps2jhRe3PZdI=; b=ZjA5KzJhMNmzJn/j8g+z03+DfCtXrCNbCsRbYag7UjfcghECU67aBI+3dp9l594d0Q 6lhBwlYDBp3oyXDySO2YKu/wlPX1Zn/uWhiFx49WwXuIqKcZd6jEER38okbZo3ohcWRp jwCZyMVW/ePwEopbB7pzU8KVL23lUmBGYx+8OktjryDBgmGcx/HVSOyGWO+hxD+XClqB NXQfn1jKKr+4lndz4q8o05yRLJnzTofNTFYMGVhv+KrJ/6gFTClpCMdWOGbKBHY9M5Sl ge7XnVc/eHBQ2RrCS3AsaWyfY8Sfl56adhJGjXRBT5qW2EfQP1wBEEgMNEjO6gHqU+VM HTFw== X-Gm-Message-State: AOAM531vraKQm+iZiUfF9LeygaC0qz6iXNU0O2L+N9vAmRrwfQ76PPYe 1lSrOpImZHZF1Xy5lgQCK70d3w== X-Google-Smtp-Source: ABdhPJwv9HEf1+Tg5g89cxyYW4osYZtB2rzBNpuRrv2oD5B9ruSdYimiL5jrIew81samurr7NTJlFQ== X-Received: by 2002:a17:902:e545:b0:154:4d5b:2006 with SMTP id n5-20020a170902e54500b001544d5b2006mr29028859plf.94.1648538977366; Tue, 29 Mar 2022 00:29:37 -0700 (PDT) Received: from localhost.localdomain ([122.171.166.231]) by smtp.gmail.com with ESMTPSA id z6-20020a056a00240600b004e17ab23340sm19440564pfh.177.2022.03.29.00.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 00:29:36 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Albert Ou , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Date: Tue, 29 Mar 2022 12:59:10 +0530 Message-Id: <20220329072911.1692766-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220329072911.1692766-1-apatel@ventanamicro.com> References: <20220329072911.1692766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The guest_hang() function is used as the default exception handler for various KVM selftests applications by setting it's address in the vstvec CSR. The vstvec CSR requires exception handler base address to be at least 4-byte aligned so this patch fixes alignment of the guest_hang() function. Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V 64-bit") Signed-off-by: Anup Patel Tested-by: Mayuresh Chitale --- tools/testing/selftests/kvm/lib/riscv/processor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index d377f2603d98..3961487a4870 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -268,7 +268,7 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_= t vcpuid, uint8_t indent) core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); } =20 -static void guest_hang(void) +static void __aligned(16) guest_hang(void) { while (1) ; --=20 2.25.1 From nobody Fri Jun 19 20:12:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2FB3C433EF for ; Tue, 29 Mar 2022 07:29:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233453AbiC2Hbe (ORCPT ); Tue, 29 Mar 2022 03:31:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233455AbiC2HbY (ORCPT ); Tue, 29 Mar 2022 03:31:24 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAD4321E29 for ; Tue, 29 Mar 2022 00:29:42 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id bx24-20020a17090af49800b001c6872a9e4eso1917699pjb.5 for ; Tue, 29 Mar 2022 00:29:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6rXr5EFnwcPfvG4wwHcp5gBTd13vVk723LJlXrxEIl0=; b=JUEfuj4EGIOyLkV/IXA9H+MaweDOMgrZPy7qZw8Pyng5lrFo1g12sEgAvyyDoeI+/Z YPk2gGUnDX7efP5RkgRPk4mRgN8A2gGZmlzNHpPC9HvA2qQU9wBS+bdi8sfIjs/DsP/w xSUYVR13TsKBRnGeCYKcLnwTjvV48fHV5QJ2MB0uRDjihOxUpVGbWsPNpSJkZPwie9pO j41Itpr2BFG30RoEPPqklTH4OzYeRSKIMIrDTeaSALBCOyv8omF7HVz6pZOdi8H157h0 qA2PW3g5DT19eO2KsOy7Dh0jldHhgbiK/7Oq0zHx0pAh1DUrUhFFRjOB4Y4XYBt2n5Ms /f0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6rXr5EFnwcPfvG4wwHcp5gBTd13vVk723LJlXrxEIl0=; b=BN3OhtDsm3gzQtBnkbTgGqw5i/hr8Uz7GIsXPuarELrLwBWUX3qDamDkYw3AzFmazB 61KpxEixJaW4DYu3NsMd5LjgwwQL+LVHxxJKVDOxPQPyYlFUGUMLc80l+ITzFX/k5TIY Dva6m7NlSYlTx/6itsvlw7WjJFjdHeTIv3bbcg/r+U8YsD51/oDIUPqPjo+B6ioeVa9b opYxawWEPm9qaR9AkT/B9aRIsSS/Tntlceh0SKdO/6FbFXpWohWQ2IyeSDUPWlD+RgSX DbcVzvXFBfKirl6CgIkGXqi9lBqXUuEaj16EuxVx1iellnMkwswR74Qa6xahtY4HESOD orYA== X-Gm-Message-State: AOAM532DALdPmPhXNSycrDvcH1aXm71WMO2sYJI3nl8+LM8rlwTjVS5p WpwChGSrqqU5WXoKtqcAJedR2A== X-Google-Smtp-Source: ABdhPJyQsJ0ZlUOLuEkiaRQqfOzbwaJd1hT2x05o7Ql9dQ+kWwo1Qx58V2AZp5og6pJtenzmq+sD/A== X-Received: by 2002:a17:902:9a98:b0:155:f634:5f37 with SMTP id w24-20020a1709029a9800b00155f6345f37mr14193551plp.86.1648538982243; Tue, 29 Mar 2022 00:29:42 -0700 (PDT) Received: from localhost.localdomain ([122.171.166.231]) by smtp.gmail.com with ESMTPSA id z6-20020a056a00240600b004e17ab23340sm19440564pfh.177.2022.03.29.00.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 00:29:41 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Albert Ou , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling Date: Tue, 29 Mar 2022 12:59:11 +0530 Message-Id: <20220329072911.1692766-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220329072911.1692766-1-apatel@ventanamicro.com> References: <20220329072911.1692766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, we simply hang using "while (1) ;" upon any unexpected guest traps because the default guest trap handler is guest_hang(). The above approach is not useful to anyone because KVM selftests users will only see a hung application upon any unexpected guest trap. This patch improves unexpected guest trap handling for KVM RISC-V selftests by doing the following: 1) Return to host user-space 2) Dump VCPU registers 3) Die using TEST_ASSERT(0, ...) Signed-off-by: Anup Patel Tested-by: Mayuresh Chitale --- .../selftests/kvm/include/riscv/processor.h | 8 +++-- .../selftests/kvm/lib/riscv/processor.c | 9 +++--- tools/testing/selftests/kvm/lib/riscv/ucall.c | 31 +++++++++++++------ 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index eca5c622efd2..4fcfd1c0389d 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -119,10 +119,12 @@ static inline void set_reg(struct kvm_vm *vm, uint32_= t vcpuid, uint64_t id, #define SATP_ASID_SHIFT 44 #define SATP_ASID_MASK _AC(0xFFFF, UL) =20 -#define SBI_EXT_EXPERIMENTAL_START 0x08000000 -#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF +#define SBI_EXT_EXPERIMENTAL_START 0x08000000 +#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF =20 -#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END +#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END +#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 +#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 =20 struct sbiret { long error; diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index 3961487a4870..56e4705f7744 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -268,10 +268,11 @@ void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint3= 2_t vcpuid, uint8_t indent) core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); } =20 -static void __aligned(16) guest_hang(void) +static void __aligned(16) guest_unexp_trap(void) { - while (1) - ; + sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, + KVM_RISCV_SELFTESTS_SBI_UNEXP, + 0, 0, 0, 0, 0, 0); } =20 void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_c= ode) @@ -310,7 +311,7 @@ void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vc= puid, void *guest_code) =20 /* Setup default exception vector of guest */ set_reg(vm, vcpuid, RISCV_CSR_REG(stvec), - (unsigned long)guest_hang); + (unsigned long)guest_unexp_trap); } =20 void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, .= ..) diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/= selftests/kvm/lib/riscv/ucall.c index 9e42d8248fa6..8550f424d093 100644 --- a/tools/testing/selftests/kvm/lib/riscv/ucall.c +++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c @@ -60,8 +60,9 @@ void ucall(uint64_t cmd, int nargs, ...) uc.args[i] =3D va_arg(va, uint64_t); va_end(va); =20 - sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc, - 0, 0, 0, 0, 0); + sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, + KVM_RISCV_SELFTESTS_SBI_UCALL, + (vm_vaddr_t)&uc, 0, 0, 0, 0, 0); } =20 uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc) @@ -73,14 +74,24 @@ uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id,= struct ucall *uc) memset(uc, 0, sizeof(*uc)); =20 if (run->exit_reason =3D=3D KVM_EXIT_RISCV_SBI && - run->riscv_sbi.extension_id =3D=3D KVM_RISCV_SELFTESTS_SBI_EXT && - run->riscv_sbi.function_id =3D=3D 0) { - memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]), - sizeof(ucall)); - - vcpu_run_complete_io(vm, vcpu_id); - if (uc) - memcpy(uc, &ucall, sizeof(ucall)); + run->riscv_sbi.extension_id =3D=3D KVM_RISCV_SELFTESTS_SBI_EXT) { + switch (run->riscv_sbi.function_id) { + case KVM_RISCV_SELFTESTS_SBI_UCALL: + memcpy(&ucall, addr_gva2hva(vm, + run->riscv_sbi.args[0]), sizeof(ucall)); + + vcpu_run_complete_io(vm, vcpu_id); + if (uc) + memcpy(uc, &ucall, sizeof(ucall)); + + break; + case KVM_RISCV_SELFTESTS_SBI_UNEXP: + vcpu_dump(stderr, vm, vcpu_id, 2); + TEST_ASSERT(0, "Unexpected trap taken by guest"); + break; + default: + break; + } } =20 return ucall.cmd; --=20 2.25.1