From nobody Sun Sep 22 09:29:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88854C433EF for ; Sun, 27 Mar 2022 22:41:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237048AbiC0WnO (ORCPT ); Sun, 27 Mar 2022 18:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237034AbiC0Wm5 (ORCPT ); Sun, 27 Mar 2022 18:42:57 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2A994EF73 for ; Sun, 27 Mar 2022 15:41:14 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id r190-20020a1c2bc7000000b0038a1013241dso7549435wmr.1 for ; Sun, 27 Mar 2022 15:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6eEHSj6Z+4nINe2TDPCkNf9jm6eypipKQx8L5na/Yyk=; b=DtFMnxGtYKmHRMUzTzh7I6DLdETH4okBmY0yZ9MvHLaMjh7fxn1GjzlARnO3nrFeWF fAPT53BgUugvQLqbPDGrhB8vEtKqIwVN94hSFvkmA+1bqD4Uvxix0VTlrpWP+D8m8qF7 bA0xO4T7ZA81J57O0lYpS9zt3+ibyiWZJaCZO5Abrn5mdXVOteXj2y1+H6YjtusmUJ08 u/HDaDEKnxRVhmoH8NbMPtcEq+5nqkd3h9yfBlUw4wsUouWfc8lt4x6PuqSNljcI4QXi QV28++7r5tExDrqDZ0A+kVrw7hf/wJX3e66BiKMUKqmqvQ31tSdpibf2ahQvnwpwenD8 JVcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6eEHSj6Z+4nINe2TDPCkNf9jm6eypipKQx8L5na/Yyk=; b=f90DGIucgE+uf1sXUjihoaGZ7cKJq2a4H9mJ/p1Be2zWPkx5PRbPdwnyIqPUdMQLJN rKgjsUZPPiD8YNLPkabOGw4d7rfWSyqtv+oy0LfTUhzDAf01qrv8xJm0f3WLBen2yBek /p5/Yt7KuCxouTO/ICrux9pQM4XzQqBIckkN/1U2Af1ZB4Fj6NRLAXBd7e1DLZGwRDZT oScuFBOx0uvv5KEm0vQdCUH/PSbYnlLc4OooWpHOX2DyEaFR3fYKD1YfmmPHpcyvZmLl lDW+S420iKaPTCdXigfI5npAwUkFR119WU/kmbXuEtbwyW1QKn40fvdj89z7tg5BycqZ Ohkg== X-Gm-Message-State: AOAM531ZktAbv/hjLSrWzdETIFrIk+eHTXebbB3MVR8utisagKAe2WKd pI5GvQgf++3K/vV4kJMD1Oyr+w== X-Google-Smtp-Source: ABdhPJwwxg1FtE27D6XIHM4ZTzbNM8vseNiuJQfxCtcwkqMIdfzlsCy1lOxRrCu9aFCLBsjbKsrLYQ== X-Received: by 2002:a7b:ce92:0:b0:38b:ed80:9e66 with SMTP id q18-20020a7bce92000000b0038bed809e66mr31716224wmj.82.1648420873144; Sun, 27 Mar 2022 15:41:13 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6341-357e-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6341:357e:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id v5-20020adfe4c5000000b001edc1e5053esm10400867wrm.82.2022.03.27.15.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Mar 2022 15:41:12 -0700 (PDT) From: Guillaume Ranquet To: airlied@linux.ie, angelogioacchino.delregno@collabora.com, chunfeng.yun@mediatek.com, chunkuang.hu@kernel.org, ck.hu@mediatek.com, daniel@ffwll.ch, deller@gmx.de, jitao.shi@mediatek.com, kishon@ti.com, krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mripard@kernel.org, p.zabel@pengutronix.de, robh+dt@kernel.org, tzimmermann@suse.de, vkoul@kernel.org Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, markyacoub@google.com Subject: [PATCH v9 09/22] drm/mediatek: dpi: implement a swap_input toggle in SoC config Date: Mon, 28 Mar 2022 00:39:14 +0200 Message-Id: <20220327223927.20848-10-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220327223927.20848-1-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support SoCs without swap_input support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 545a1337cc89..454f8563efae 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dp= i *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1