From nobody Sat Jun 20 01:02:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24DD9C433EF for ; Sat, 26 Mar 2022 20:25:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235256AbiCZU1B (ORCPT ); Sat, 26 Mar 2022 16:27:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230431AbiCZU0z (ORCPT ); Sat, 26 Mar 2022 16:26:55 -0400 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5A2E1E3EC for ; Sat, 26 Mar 2022 13:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=rAl9xafuDgeMtqKjng+jIOA2xEyxA42IxfNsimCsIDI=; b=Vo8tAL4pJcCNKs1Apoo48Qq7TW Lz/9bVDEpiBFRcGttZ3lanIvkl5cgvmQufrXvPSV6l/L2TqFB9haMJEfhxYER34H/CdHbedtz7Gp8 mOPPURwwSE8tEH9g2TKxtXj55c84KjVCx44h9yRPYiPVFfmNGgu1hJ+orKJYAKM8M2YtsB4WT/JsJ wtnsFWJ5tzhey+q/delDFtIiacoGnTpOU4yLWBNULSltmoOHTWS4imdsfkLxQqflG4zFjZWDzTirn h4Mvs+0Sw/VtA4Ue6rMO3JCStnIzWJ8iQ8Wcbxgd/bEBXDZhucS4tFWqjuGdc8RDmCmL96AHAqEZn LVTv+U2A==; Received: from [165.90.126.25] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1nYCyG-0007e9-Sy; Sat, 26 Mar 2022 21:25:13 +0100 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie, daniel@ffwll.ch Cc: Qingqing Zhuo , Dmytro Laktyushkin , Jasdeep Dhillon , Melissa Wen , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] drm/amd/display: detach fpu operations from dcn10_validate_bandwidth in calcs Date: Sat, 26 Mar 2022 19:24:47 -0100 Message-Id: <20220326202448.2046077-2-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220326202448.2046077-1-mwen@igalia.com> References: <20220326202448.2046077-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dcn10_validate_bandwidth is only used on dcn10 files, but is declared in dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper inside DML folder and create an specific dcn10_validate_bandwidth in dcn10_resources that calls dcn_validate_bandwidth and properly wraps that FPU function with DC_FP_* macro. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 14 ++++++++++++++ .../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 5 +---- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/driver= s/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 4048908dd265..1587a060b55a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1141,6 +1141,20 @@ static void dcn10_destroy_resource_pool(struct resou= rce_pool **pool) *pool =3D NULL; } =20 +static bool dcn10_validate_bandwidth( + struct dc *dc, + struct dc_state *context, + bool fast_validate) +{ + bool voltage_supported; + + DC_FP_START(); + voltage_supported =3D dcn_validate_bandwidth(dc, context, fast_validate); + DC_FP_END(); + + return voltage_supported; +} + static enum dc_status dcn10_validate_plane(const struct dc_plane_state *pl= ane_state, struct dc_caps *caps) { if (plane_state->format >=3D SURFACE_PIXEL_FORMAT_VIDEO_BEGIN diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers= /gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index e447c74be713..c25023f7d604 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -764,7 +764,7 @@ static unsigned int get_highest_allowed_voltage_level(u= int32_t chip_family, return 4; } =20 -bool dcn10_validate_bandwidth( +bool dcn_validate_bandwidth( struct dc *dc, struct dc_state *context, bool fast_validate) @@ -790,7 +790,6 @@ bool dcn10_validate_bandwidth( dcn_bw_sync_calcs_and_dml(dc); =20 memset(v, 0, sizeof(*v)); - DC_FP_START(); =20 v->sr_exit_time =3D dc->dcn_soc->sr_exit_time; v->sr_enter_plus_exit_time =3D dc->dcn_soc->sr_enter_plus_exit_time; @@ -1323,8 +1322,6 @@ bool dcn10_validate_bandwidth( bw_limit =3D dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_band= width_vmax0p9; bw_limit_pass =3D (v->total_data_read_bandwidth / 1000.0) < bw_limit; =20 - DC_FP_END(); - PERFORMANCE_TRACE_END(); BW_VAL_TRACE_FINISH(); =20 diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/d= rm/amd/display/dc/inc/dcn_calcs.h index 337c0161e72d..806f3041db14 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -619,7 +619,7 @@ struct dcn_ip_params { }; extern const struct dcn_ip_params dcn10_ip_defaults; =20 -bool dcn10_validate_bandwidth( +bool dcn_validate_bandwidth( struct dc *dc, struct dc_state *context, bool fast_validate); --=20 2.35.1 From nobody Sat Jun 20 01:02:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7AF2C433F5 for ; Sat, 26 Mar 2022 20:25:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235264AbiCZU1V (ORCPT ); Sat, 26 Mar 2022 16:27:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230431AbiCZU1T (ORCPT ); Sat, 26 Mar 2022 16:27:19 -0400 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ED052127B for ; Sat, 26 Mar 2022 13:25:42 -0700 (PDT) DKIM-Signature: v=1; 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charset="utf-8" FPU documentation states that developers must not use DC_FP_START/END inside dml files, but use this macro to wrap calls to FPU functions in dc folder (outside dml folder). Therefore, this patch removes DC_FP_* wrappers from dml folder and wraps calls for these FPU operations outside dml, as required. Signed-off-by: Melissa Wen --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++++++-- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 ++ .../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 14 -------------- .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 -- 4 files changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/dr= ivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c3e141c19a77..6b4d9917933b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2979,8 +2979,11 @@ void dcn10_prepare_bandwidth( true); dcn10_stereo_hw_frame_pack_wa(dc, context); =20 - if (dc->debug.pplib_wm_report_mode =3D=3D WM_REPORT_OVERRIDE) + if (dc->debug.pplib_wm_report_mode =3D=3D WM_REPORT_OVERRIDE) { + DC_FP_START(); dcn_bw_notify_pplib_of_wm_ranges(dc); + DC_FP_END(); + } =20 if (dc->debug.sanity_checks) hws->funcs.verify_allow_pstate_change_high(dc); @@ -3013,8 +3016,11 @@ void dcn10_optimize_bandwidth( =20 dcn10_stereo_hw_frame_pack_wa(dc, context); =20 - if (dc->debug.pplib_wm_report_mode =3D=3D WM_REPORT_OVERRIDE) + if (dc->debug.pplib_wm_report_mode =3D=3D WM_REPORT_OVERRIDE) { + DC_FP_START(); dcn_bw_notify_pplib_of_wm_ranges(dc); + DC_FP_END(); + } =20 if (dc->debug.sanity_checks) hws->funcs.verify_allow_pstate_change_high(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/driver= s/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 1587a060b55a..bca049b2f867 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1506,6 +1506,7 @@ static bool dcn10_resource_construct( && pool->base.pp_smu->rv_funcs.set_pme_wa_enable !=3D NULL) dc->debug.az_endpoint_mute_only =3D false; =20 + DC_FP_START(); if (!dc->debug.disable_pplib_clock_request) dcn_bw_update_from_pplib(dc); dcn_bw_sync_calcs_and_dml(dc); @@ -1513,6 +1514,7 @@ static bool dcn10_resource_construct( dc->res_pool =3D &pool->base; dcn_bw_notify_pplib_of_wm_ranges(dc); } + DC_FP_END(); =20 { struct irq_service_init_data init_data; diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers= /gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c index c25023f7d604..db3b16b77034 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c @@ -639,7 +639,6 @@ static bool dcn_bw_apply_registry_override(struct dc *d= c) { bool updated =3D false; =20 - DC_FP_START(); if ((int)(dc->dcn_soc->sr_exit_time * 1000) !=3D dc->debug.sr_exit_time_ns && dc->debug.sr_exit_time_ns) { updated =3D true; @@ -675,7 +674,6 @@ static bool dcn_bw_apply_registry_override(struct dc *d= c) dc->dcn_soc->dram_clock_change_latency =3D dc->debug.dram_clock_change_latency_ns / 1000.0; } - DC_FP_END(); =20 return updated; } @@ -1492,8 +1490,6 @@ void dcn_bw_update_from_pplib(struct dc *dc) res =3D dm_pp_get_clock_levels_by_type_with_voltage( ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); =20 - DC_FP_START(); - if (res) res =3D verify_clock_values(&fclks); =20 @@ -1523,13 +1519,9 @@ void dcn_bw_update_from_pplib(struct dc *dc) } else BREAK_TO_DEBUGGER(); =20 - DC_FP_END(); - res =3D dm_pp_get_clock_levels_by_type_with_voltage( ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); =20 - DC_FP_START(); - if (res) res =3D verify_clock_values(&dcfclks); =20 @@ -1540,8 +1532,6 @@ void dcn_bw_update_from_pplib(struct dc *dc) dc->dcn_soc->dcfclkv_max0p9 =3D dcfclks.data[dcfclks.num_levels - 1].clo= cks_in_khz / 1000.0; } else BREAK_TO_DEBUGGER(); - - DC_FP_END(); } =20 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) @@ -1556,11 +1546,9 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) if (!pp || !pp->set_wm_ranges) return; =20 - DC_FP_START(); min_fclk_khz =3D dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 100000= 0 / 32; min_dcfclk_khz =3D dc->dcn_soc->dcfclkv_min0p65 * 1000; socclk_khz =3D dc->dcn_soc->socclk * 1000; - DC_FP_END(); =20 /* Now notify PPLib/SMU about which Watermarks sets they should select * depending on DPM state they are in. And update BW MGR GFX Engine and @@ -1611,7 +1599,6 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) =20 void dcn_bw_sync_calcs_and_dml(struct dc *dc) { - DC_FP_START(); DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n" "sr_enter_plus_exit_time: %f ns\n" "urgent_latency: %f ns\n" @@ -1800,5 +1787,4 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) dc->dml.ip.bug_forcing_LC_req_same_size_fixed =3D dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed =3D= =3D dcn_bw_yes; dc->dml.ip.dcfclk_cstate_latency =3D dc->dcn_ip->dcfclk_cstate_latency; - DC_FP_END(); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers= /gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 2f6122153bdb..36b12a350bbd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1290,9 +1290,7 @@ int dcn20_populate_dml_pipes_from_context( } =20 /* populate writeback information */ - DC_FP_START(); dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pip= es); - DC_FP_END(); =20 return pipe_cnt; } --=20 2.35.1