From nobody Fri Jun 19 23:48:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 880E3C433F5 for ; Sat, 26 Mar 2022 05:58:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231350AbiCZF7u (ORCPT ); Sat, 26 Mar 2022 01:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231326AbiCZF7n (ORCPT ); Sat, 26 Mar 2022 01:59:43 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62504614E for ; Fri, 25 Mar 2022 22:58:07 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id t14so8105920pgr.3 for ; Fri, 25 Mar 2022 22:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jUGw0NkuB9iBqYF8FzgnNYOetLAQGByMMthQDolliB8=; b=wlCcMTt3dwqmuoumWfTufSjw4c6VT2ZQeUsWI+tMhOvBu1R3aIYaDhCq4VvGfTzXKz ONZ4z8zsbn6g1b858Oi96Hn4mbYBuI2gdQgsORI3vNf9Fz/AItmFpJg+dk3r54to0UdH WEW8bdADV2ishmzExJZVpe0xvgAV5G7BPaTq+Px4Jgbasvf+TO2sXPJ84GfeEdsqhJn9 pKwahNH3tL9y5yR8jiA/tOZFq8KlkvHBLmjDpjt8s3fZcr7zkCJtyIUzjwmnZ7uYHsd1 9Q6uP5ve6xslOg5P+tKNooGsLV0QBfowp7S4/rqXk7ALT3i5C7uRQv7HcAHonehEPn4A Nzhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jUGw0NkuB9iBqYF8FzgnNYOetLAQGByMMthQDolliB8=; b=eNuQcPwQyn5UFXwdEirRPq2m8ZXOEUqY+EXRIc3HVhInqeY6vNxJPFHz/SBrZY1Y2L nkSmHCjcN2iqjc+fccV3/738FzBN3xKyJiqtJ3en/Ugv2wOpgfi6xzZByIE0y7UcA+Ol ojiHTgqip+/qwRThYc87DvRtRvcvCIk5fSKPFDkbyv4F+hL/cvcJWc2uDABYEo+OmOk+ 2oIWLKVshfZxWRR1cPkIrQAXCJTbA2tfkRUo3fyL4t3cmKLykSx9rJjfAN+DP0a/58I+ Bru28BosXXrPNWT7MLLShpsIsIFkR2sCQ7QXmIxuVVESS8Akxcc2PG2m94sjMjS1CvLz FcTw== X-Gm-Message-State: AOAM530ChmFePWr3CPNN+6+Ko7xND49muEAkRbuUuFDYgfk2p3/K00jL DrEinoguAn9CrrzjfaAhx4EwNA== X-Google-Smtp-Source: ABdhPJyAMn/DeFOZZx6cut1nCZkXaySZIajbvqSwfXBIXHjlXQlsZgIIe+Yg5Tb1pWaKxCRboloWpw== X-Received: by 2002:a63:1a0c:0:b0:382:1ced:62c0 with SMTP id a12-20020a631a0c000000b003821ced62c0mr2407755pga.36.1648274286855; Fri, 25 Mar 2022 22:58:06 -0700 (PDT) Received: from localhost.localdomain ([223.233.78.42]) by smtp.gmail.com with ESMTPSA id b2-20020a056a000a8200b004e1414f0bb1sm9505067pfl.135.2022.03.25.22.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 22:58:06 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org Subject: [PATCH v4 1/2] arm64: dts: qcom: sm8150: Add PCIe nodes Date: Sat, 26 Mar 2022 11:27:53 +0530 Message-Id: <20220326055754.1796146-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220326055754.1796146-1-bhupesh.sharma@linaro.org> References: <20220326055754.1796146-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for the two PCIe controllers found on the SM8150 SoC. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 15f3bf2e7ea0..92b3705b0941 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1746,6 +1746,203 @@ system-cache-controller@9200000 { interrupts =3D ; }; =20 + pcie0: pci@1c00000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommus =3D <&apps_smmu 0x1d80 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie0_lane: phy@1c06200 { + reg =3D <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1e00 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c0e000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie1_lane: phy@1c0e200 { + reg =3D <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -2448,6 +2645,52 @@ qup_spi19_default: qup-spi19-default { drive-strength =3D <6>; bias-disable; }; + + pcie0_default_state: pcie0-default { + perst { + pins =3D "gpio35"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio36"; + function =3D "pci_e0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio37"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio103"; + function =3D "pci_e1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio104"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; }; =20 remoteproc_mpss: remoteproc@4080000 { --=20 2.35.1 From nobody Fri Jun 19 23:48:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2697DC433F5 for ; Sat, 26 Mar 2022 05:58:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbiCZF7z (ORCPT ); Sat, 26 Mar 2022 01:59:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231349AbiCZF7r (ORCPT ); Sat, 26 Mar 2022 01:59:47 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6BF22528 for ; Fri, 25 Mar 2022 22:58:10 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id h19so7259411pfv.1 for ; Fri, 25 Mar 2022 22:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vsQ1ZJDbzm8xjG34TYgWolguHSp0d0tTX8/9HERcrNs=; b=kgzEx5U+usqwGcjy+zG6MpsKazUBCOMJOf2PLiHhrDWVNJM+iNJC8CcWFSzYizXcsi QUZoBL3re5R5zeI/lxOMb26SMNBs+nV+SDBGoYSzY6sA/LBeewodQuwfC2PM7O0FsA70 V5pStK942xQ/MvlV0rE92NiCEzgdH/P82kGKqSiXK/Rvfrg+7Wfjg9m7bQ39UChtsGwa LEw0z+BoBPOBfzEuyIB2fC3CxHZLEx8u5W3sr3lTn3o2RLOO/4gnM5nU9C87BWZ3yRaX gchVUyHz1J3++5amMcHeRgMUPMIffhdkl1QiNWs2U7UTYMNKCr9sdKHHnnsv27d+jLjY 46Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vsQ1ZJDbzm8xjG34TYgWolguHSp0d0tTX8/9HERcrNs=; b=s6qNpEYnh0LCiaaITt5QtcBeQkr7eXNbcVrE9XAgPjtXisszO3mbldZVjqHcFG8Q/G P/VyNscBXE/B8SlxPSEDXbpze1LoY4C0NlsgStAveD5S9rPz+svlbuY90ZoC+TJLXpWB XEJYPWDxAxK2OVfN8fChsctBHLTZ8e103zKiXwgVYSebdleouWvpecij0+QgRs+lcR1F eFMkNFX5mciVRgkYO1+nL7NKKUdl+eqFTy//9LLAEWbUaDlcY4AhXcQ2ZP3NlJFIyRur usdRqLKLL90yfwIFXEVO+WU3vjx7wVEozFVWj6Md+RGduSBeJ7zl9jbHUOp/dnfrTJY4 EZdA== X-Gm-Message-State: AOAM530SubWiZGYNRcWb3LoJ5vAsnva4AXI+eDiKFQOCs+xX9zhXCKRM KjAHSXexxvFi7F+SuLrIR6/i8Q== X-Google-Smtp-Source: ABdhPJxq7vt7oi+D/i4f+hhO8Q9TjjM+NhAy6KY+3G6J6E9XjTOtp/mFZY9Tb46J0USK4Aj4I59jJA== X-Received: by 2002:a63:481d:0:b0:380:ea8d:4301 with SMTP id v29-20020a63481d000000b00380ea8d4301mr2312697pga.285.1648274290336; Fri, 25 Mar 2022 22:58:10 -0700 (PDT) Received: from localhost.localdomain ([223.233.78.42]) by smtp.gmail.com with ESMTPSA id b2-20020a056a000a8200b004e1414f0bb1sm9505067pfl.135.2022.03.25.22.58.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 22:58:10 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org, Vinod Koul Subject: [PATCH v4 2/2] arm64: dts: qcom: sa8155: Enable PCIe nodes Date: Sat, 26 Mar 2022 11:27:54 +0530 Message-Id: <20220326055754.1796146-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220326055754.1796146-1-bhupesh.sharma@linaro.org> References: <20220326055754.1796146-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8155p-adp.dts index 8756c2b25c7e..676e4fe3f848 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -387,6 +387,21 @@ &usb_2_qmpphy { vdda-pll-supply =3D <&vdda_usb_ss_dp_core_1>; }; =20 +&pcie0 { + status =3D "okay"; +}; + +&pcie0_phy { + status =3D "okay"; + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + &tlmm { gpio-reserved-ranges =3D <0 4>; =20 --=20 2.35.1