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charset="utf-8" Add the following two PCIe PHYs found on SM8150, to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Acked-by: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e20d9b087bb8..1e08acb8a59a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -39,6 +39,8 @@ properties: - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm6115-qmp-ufs-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy @@ -336,6 +338,8 @@ allOf: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy --=20 2.35.1 From nobody Fri Jun 19 23:49:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E12C433EF for ; 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Fri, 25 Mar 2022 15:21:44 -0700 (PDT) From: Bhupesh Sharma To: linux-phy@lists.infradead.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, bjorn.andersson@linaro.org Subject: [PATCH v4 2/2] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Date: Sat, 26 Mar 2022 03:51:30 +0530 Message-Id: <20220325222130.1783242-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220325222130.1783242-1-bhupesh.sharma@linaro.org> References: <20220325222130.1783242-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8150 has multiple (different) PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Add support for these with relevant init sequence. Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma --- drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy= -qcom-qmp.c index b144ae1f729a..8e928b9619b6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] =3D= { "aux", "cfg_ahb", "ref", "refgen", }; =20 +/* the pcie phy on sm8150 doesn't have a ref clock */ +static const char * const sm8150_pciephy_clk_l[] =3D { + "aux", "cfg_ahb", "refgen", +}; + static const char * const qmp_v4_phy_clk_l[] =3D { "aux", "ref_clk_src", "ref", "com_aux", }; @@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_c= fg =3D { .pwrdn_delay_max =3D 1005, /* us */ }; =20 +static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 1, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec =3D sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 2, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .is_dual_lane_phy =3D true, + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg =3D { .type =3D PHY_TYPE_PCIE, .nlanes =3D 1, @@ -6007,6 +6091,12 @@ static const struct of_device_id qcom_qmp_phy_of_mat= ch_table[] =3D { }, { .compatible =3D "qcom,sm6115-qmp-ufs-phy", .data =3D &sm6115_ufsphy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy", + .data =3D &sm8150_qmp_gen3x1_pciephy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy", + .data =3D &sm8150_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,sm8150-qmp-ufs-phy", .data =3D &sm8150_ufsphy_cfg, --=20 2.35.1