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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:44 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com, Krzysztof Kozlowski Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann , Rob Herring Subject: [PATCH 01/22] dt-bindings: mediatek,dpi: Add DP_INTF compatible Date: Fri, 25 Mar 2022 18:14:50 +0100 Message-Id: <20220325171511.23493-2-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann DP_INTF is similar to DPI but does not have the exact same feature set or register layouts. DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: Rob Herring --- .../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index dd2896a40ff0..53acf9a84f7f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: mediatek DPI Controller Device Tree Bindings +title: mediatek DPI/DP_INTF Controller Device Tree Bindings =20 maintainers: - CK Hu - Jitao shi =20 description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The Mediatek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data= on a + parallel output bus. =20 properties: compatible: @@ -23,6 +23,7 @@ properties: - mediatek,mt8173-dpi - mediatek,mt8183-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dpintf =20 reg: maxItems: 1 @@ -54,7 +55,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of= an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. =20 required: - compatible --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF94FC433EF for ; Fri, 25 Mar 2022 17:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229808AbiCYRSk (ORCPT ); Fri, 25 Mar 2022 13:18:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377374AbiCYRS0 (ORCPT ); Fri, 25 Mar 2022 13:18:26 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09901E9945 for ; Fri, 25 Mar 2022 10:16:48 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id v2-20020a7bcb42000000b0037b9d960079so9424711wmj.0 for ; Fri, 25 Mar 2022 10:16:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kxLbJh/5GTpyK0sJHkMhIg51PKQ0gujNd33p5sfYd68=; b=25A0IRKOTfVWYt6ly9GPt/OjAFv2TMiYasnPsVRIu30KUgeWiS9JPJZ2ysQi5q/owZ gHB+w9zhhNcjcDodCfJoh9NgOwHYs2LBFVzaFDaxb4NRJ6BcNMCUqztopNNNVFvXDFYN pitmnvmAGxeDAtklO9ssjG3TCvC8r+Dcj7t7qem1dVJlyaKYPxml8dsT7RWQfrWmruvn CXPz8Dmj5xVRzL4FuuYLo678DuloDipYM7fmDpdFCmjClMQGhOJDAnnsZlXq+AdSq7I/ A/1yXarnjisOiWXCApoiac4bOn6ZbtpHIAMqAfXiGn1pqxIw8Qo0pErnPlKaicjzbjGs d4+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kxLbJh/5GTpyK0sJHkMhIg51PKQ0gujNd33p5sfYd68=; b=tY3+doc/Kaa/2LZ4ymg19wNRBYpH3dbrDH4x9uKxnzGywxv/KANQPLI4sACGqAe08A rbLtsWbkkY1quROgdjCFgHyDFYewNWWKWrB3k0XtR6PSFxYaCkEUZ34ShpQmw+SkavTA iOm0e2BmM708fvnibOx+J1bcaJPPpoPHVvAPYRIjjhnRukA90OHq8Rdff3KKoBBuxmFP LBdZ9AT3hLD3fTUyIYM+VG0CoTRs6bO83HIiIjt8MWR8/q7w5ruOZ27o0FyruwCMZpTI 0ssap4seNyBAKGvHdLq4Z5ZsZjI7Grc8ajuVTLp4Prf5SzlWoyOn1KOu0rNh8KhIPV1J 8NMw== X-Gm-Message-State: AOAM531NJz34vYeNk00imhdBH4Vwf+K80SLp1gO1cSwPJnXOdTp32iQD MROEZc0ZIf5e5IMCMt5vMBuDUw== X-Google-Smtp-Source: ABdhPJwNQpIImDscEbLueHTSw+vh13EH8/JtYWdT4NMiTrPeQs+QvSgzCntOpuP2NQR+McLC+CEjAA== X-Received: by 2002:a05:600c:3ac7:b0:38b:f9c6:27b8 with SMTP id d7-20020a05600c3ac700b0038bf9c627b8mr10820156wms.75.1648228607273; Fri, 25 Mar 2022 10:16:47 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:46 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com, Krzysztof Kozlowski Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann , Rob Herring Subject: [PATCH 02/22] dt-bindings: mediatek,dp: Add Display Port binding Date: Fri, 25 Mar 2022 18:14:51 +0100 Message-Id: <20220325171511.23493-3-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This controller is present on several mediatek hardware. Currently mt8195 and mt8395 have this controller without a functional difference, so only one compatible field is added. The controller can have two forms, as a normal display port and as an embedded display port. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: Rob Herring --- .../display/mediatek/mediatek,dp.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 000000000000..74db5c4e0f73 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Display Port Controller + +maintainers: + - CK Hu + - Jitao shi + +description: | + Device tree bindings for the Mediatek (embedded) Display Port controller + present on some Mediatek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + - syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: faxi clock + + clock-names: + items: + - const: faxi + + phys: + maxItems: 1 + + phy-names: + items: + - const: dp + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the controller + +required: + - compatible + - reg + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + #include + edp_tx: edp_tx@1c500000 { + compatible =3D "mediatek,mt8195-dp-tx","syscon"; + reg =3D <0 0x1c500000 0 0x8000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_pin>; + phys =3D <&dp_phy>; + phy-names =3D "dp"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dp_intf0_out>; + }; + }; + port@1 { + reg =3D <1>; + edp_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFB85C43217 for ; Fri, 25 Mar 2022 17:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377319AbiCYRSo (ORCPT ); Fri, 25 Mar 2022 13:18:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377323AbiCYRSg (ORCPT ); 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:49 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com, Krzysztof Kozlowski Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding Date: Fri, 25 Mar 2022 18:14:52 +0100 Message-Id: <20220325171511.23493-4-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This phy controller is embedded in the Display Port Controller on mt8195 So= Cs. Signed-off-by: Guillaume Ranquet --- .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.y= aml diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/D= ocumentation/devicetree/bindings/phy/mediatek,dp-phy.yaml new file mode 100644 index 000000000000..4180d40f4fa7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2022 MediaTek +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port PHY binding + +maintainers: + - CK Hu + - Jitao shi + +description: | + Device tree bindings for the Mediatek (embedded) Display Port PHY + present on some Mediatek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-phy + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the Display Port node. + + "#phy-cells": + const: 0 + +required: + - compatible + - regmap + - "#phy-cells" + +additionalProperties: false + +examples: + - | + dp_phy: dp_phy { + compatible =3D "mediatek,mt8195-dp-phy"; + regmap =3D <&dp_tx>; + #phy-cells =3D <0>; + }; --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABF73C433EF for ; Fri, 25 Mar 2022 17:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344056AbiCYRSt (ORCPT ); Fri, 25 Mar 2022 13:18:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233918AbiCYRSh (ORCPT ); Fri, 25 Mar 2022 13:18:37 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB3C5E9C80 for ; Fri, 25 Mar 2022 10:16:52 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id l9-20020a05600c4f0900b0038ccd1b8642so2918864wmq.0 for ; Fri, 25 Mar 2022 10:16:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NqdfmywTZ6fQ/7jJTAQIW5tJoHGg7kZG5yl6dza7Kzg=; b=6bXchobGzN8pKvh+gXq4jQSUpRYYt6KibxSAsqSutu1/Yix1bAtFWio+4+5L2OT8gO KRwuxVreNneXSQGczLUHqu/9HMPhxIRfgbJW/r3UPWCbrTyCufwjX5onl9UM5gV/JWhK zUAlnmhVP2Md/IVwZvzxDWkkSGER0G02QgvLhUL/X7jArek2m0p9TQei65y4Fqg0z9RB F6/adAuTQCOPL7XbJ907Vf3vNG3Pv+ViBiGQYC4xuV49DFVqBZv5yCQRWsvtbUueYzoS Hl22196SiZd0bGZTvV+MLU+u/PO6RWkOpZhSUmnIt+Vic3k1GEXhwXmSAMdccnZ7lakM fwnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NqdfmywTZ6fQ/7jJTAQIW5tJoHGg7kZG5yl6dza7Kzg=; b=a5Kzgm/JYp4bunXuCD1XAVAz/iUyxe8iAxfHl9CVsilXd3VUjHR0YbvUBp+W91SCmd gNqRWeFUrnqEJdVJxBcl0IVNf4IFDjQTrIhau5C22Ba/yl49CK+r/NMJ9JuiKm8AfNKM nTO+Y85ohmb0SxoadttOta4D/cZ4mPeT+AxvfZQ+3ggkgqR38VZk0B69bBqVWr5tAVQf ZzeL7vL7MNz8hjHEq4aH8EMpVZHgVHCFGzed89Fyuo+RMNlKrJYsK3N2YhqUIsSQxDK6 u8p0XKJYONbRiW/DjtyK3F/MPama+YdpM6sLSewqWTN42VixeF1EhASGZ3Ga/wqJGkaN aUWg== X-Gm-Message-State: AOAM532A86iQ74Gm9xbIh8jQSFaJk3UXo1iph9d3/+mi6apXQ35cadr8 lx0qyg9JsIkekQtL69WnSh8bBA== X-Google-Smtp-Source: ABdhPJztbg41uIEn6kYbSEgV3LT+xnRXVt+kN+pXwZTNOue5R4lV3fouoQj4ndoTzsNVOsRmWuPg8Q== X-Received: by 2002:a7b:c30c:0:b0:38c:8ff1:625b with SMTP id k12-20020a7bc30c000000b0038c8ff1625bmr20345780wmj.30.1648228611391; Fri, 25 Mar 2022 10:16:51 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:51 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 04/22] drm/edid: Convert cea_sad helper struct to kernelDoc Date: Fri, 25 Mar 2022 18:14:53 +0100 Message-Id: <20220325171511.23493-5-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Guillaume Ranquet --- include/drm/drm_edid.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 144c495b99c4..5d4d840b9904 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -359,12 +359,17 @@ struct edid { =20 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) =20 -/* Short Audio Descriptor */ +/* struct cea_sad - Short Audio Descriptor. + @format: See HDMI_AUDIO_CODING_TYPE_*. + @channels: max number of channels - 1. + @freq: See CEA_SAD_FREQ_*. + @byte2: meaning depends on format. +*/ struct cea_sad { u8 format; - u8 channels; /* max number of channels - 1 */ + u8 channels; u8 freq; - u8 byte2; /* meaning depends on format */ + u8 byte2; }; =20 struct drm_encoder; --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F9EAC433F5 for ; Fri, 25 Mar 2022 17:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239082AbiCYRSx (ORCPT ); Fri, 25 Mar 2022 13:18:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377375AbiCYRSh (ORCPT ); Fri, 25 Mar 2022 13:18:37 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1865CE9CB5 for ; Fri, 25 Mar 2022 10:16:55 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id p184-20020a1c29c1000000b0037f76d8b484so4780049wmp.5 for ; Fri, 25 Mar 2022 10:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bYxsps88w8XOTS4NTOr0eUjfIjqeWe2ct6Gz/AMg8SQ=; b=3QeDLL+kno2ASafNq1yAb+eY4UN1c6ynD3eQFooOufQwRPGl+4wMEaT1N5cCrY99Si VNLFY0Y4we3NdSHkYcoBhNLSatiuy3H1J6+K4H7kV2i6VXlK+v6UlgAC8se+jjwoqjhX mTW/CF6a0rKfHBItcMn8Ar9gBmCKsHWpdqXWF2kUrpr6qCLPj5ssBHCupdrOLoJlLXK2 IdW2FqJnPqf8Wtlswtx2B/Ec4RsCJZKUr2Y5tKvf+xYGsnzYz3Wfgl3WpLExdToNMG0D J/ni6ftntvbnq0QHLkXZE0xTJQoTJKifEvEOIVtULBJPX8kk/ujsIBCkEmzaexC2xD69 ja5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bYxsps88w8XOTS4NTOr0eUjfIjqeWe2ct6Gz/AMg8SQ=; b=LwTHVwzNUnjBDYUm+m5uvmgjdzxu/qGp72/SJWr3aECRq8Pa71FUYykswQ+paCPkct 7RXoxDqC3v1X8XEnfv2RMrikP9+rs05zURzNFczVnIuzbhKzFCTdWha5qHHtpij7zahD Jj9YGeZ7+LClS6v1GVLjK2U3+5cKT2AktGAGLQqplGY07O8GhKdOAe88YLsl/QEbVNXp oJjCGCBjwBI27yfJgkk6rPE4ut+JzVUCE+PIhF5a+Tskt0LK/vaoXhqEpr0zW0aTW+74 yoGLSC2mlIAMVqcTBdtGE20MtpyOpoOVoSZ1VugTEw+FNoj2NxYeEh4WArAedSE9MEu+ ytPw== X-Gm-Message-State: AOAM533eI0OVzsSPyTvIx/w6PPSBvgvSIxjHhWtpSOA26FHcM8VL72lA RUD09Ib1nv3DQ6BMEVGx40bZxg== X-Google-Smtp-Source: ABdhPJydSZEDR1RKQvP5hXg5nNvDMg1nkizYbpag71bPLKRQ0E5MKTsq4pT9e5lWJ5szAy/SJlYt9g== X-Received: by 2002:a05:600c:3b1e:b0:38c:da9f:9309 with SMTP id m30-20020a05600c3b1e00b0038cda9f9309mr7349169wms.9.1648228613538; Fri, 25 Mar 2022 10:16:53 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:53 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann Subject: [PATCH 05/22] drm/edid: Add cea_sad helpers for freq/length Date: Fri, 25 Mar 2022 18:14:54 +0100 Message-Id: <20220325171511.23493-6-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds two helper functions that extract the frequency and word length from a struct cea_sad. For these helper functions new defines are added that help translate the 'freq' and 'byte2' fields into real numbers. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/drm_edid.c | 74 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 14 ++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 3b7041fc9cdf..2e98c993aaca 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4758,6 +4758,80 @@ int drm_edid_to_speaker_allocation(struct edid *edid= , u8 **sadb) } EXPORT_SYMBOL(drm_edid_to_speaker_allocation); =20 +/** + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad frequency field and returns the sample rate in Hz. + * + * Return: Sample rate in Hz or a negative errno if parsing failed. + */ +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad) +{ + switch (sad->freq) { + case DRM_CEA_SAD_FREQ_32KHZ: + return 32000; + case DRM_CEA_SAD_FREQ_44KHZ: + return 44100; + case DRM_CEA_SAD_FREQ_48KHZ: + return 48000; + case DRM_CEA_SAD_FREQ_88KHZ: + return 88200; + case DRM_CEA_SAD_FREQ_96KHZ: + return 96000; + case DRM_CEA_SAD_FREQ_176KHZ: + return 176400; + case DRM_CEA_SAD_FREQ_192KHZ: + return 192000; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate); + +static bool drm_cea_sad_is_uncompressed(const struct cea_sad *sad) +{ + switch (sad->format) { + case HDMI_AUDIO_CODING_TYPE_STREAM: + case HDMI_AUDIO_CODING_TYPE_PCM: + return true; + default: + return false; + } +} + +/** + * drm_cea_sad_get_uncompressed_word_length - Extract word length + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad byte2 field and returns the word length for an + * uncompressed stream. + * + * Note: This function may only be called for uncompressed audio. + * + * Return: Word length in bits or a negative errno if parsing failed. + */ +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad) +{ + if (!drm_cea_sad_is_uncompressed(sad)) { + DRM_WARN("Unable to get the uncompressed word length for a compressed fo= rmat: %u\n", + sad->format); + return -EINVAL; + } + + switch (sad->byte2) { + case DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT: + return 16; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT: + return 20; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT: + return 24; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length); + /** * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay * @connector: connector associated with the HDMI/DP sink diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 5d4d840b9904..ebd00ecae205 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -372,6 +372,18 @@ struct cea_sad { u8 byte2; }; =20 +#define DRM_CEA_SAD_FREQ_32KHZ BIT(0) +#define DRM_CEA_SAD_FREQ_44KHZ BIT(1) +#define DRM_CEA_SAD_FREQ_48KHZ BIT(2) +#define DRM_CEA_SAD_FREQ_88KHZ BIT(3) +#define DRM_CEA_SAD_FREQ_96KHZ BIT(4) +#define DRM_CEA_SAD_FREQ_176KHZ BIT(5) +#define DRM_CEA_SAD_FREQ_192KHZ BIT(6) + +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2) + struct drm_encoder; struct drm_connector; struct drm_connector_state; @@ -379,6 +391,8 @@ struct drm_display_mode; =20 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad); +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad); int drm_av_sync_delay(struct drm_connector *connector, const struct drm_display_mode *mode); =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC30C433F5 for ; Fri, 25 Mar 2022 17:17:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230410AbiCYRS4 (ORCPT ); Fri, 25 Mar 2022 13:18:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346121AbiCYRSi (ORCPT ); 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:55 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann Subject: [PATCH 06/22] video/hdmi: Add audio_infoframe packing for DP Date: Fri, 25 Mar 2022 18:14:55 +0100 Message-Id: <20220325171511.23493-7-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann Similar to HDMI, DP uses audio infoframes as well which are structured very similar to the HDMI ones. This patch adds a helper function to pack the HDMI audio infoframe for DP, called hdmi_audio_infoframe_pack_for_dp(). hdmi_audio_infoframe_pack_only() is split into two parts. One of them packs the payload only and can be used for HDMI and DP. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/video/hdmi.c | 82 ++++++++++++++++++++++++++-------- include/drm/dp/drm_dp_helper.h | 2 + include/linux/hdmi.h | 7 ++- 3 files changed, 71 insertions(+), 20 deletions(-) diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index 947be761dfa4..5f50237554ed 100644 --- a/drivers/video/hdmi.c +++ b/drivers/video/hdmi.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ =20 +#include #include #include #include @@ -381,12 +382,34 @@ static int hdmi_audio_infoframe_check_only(const stru= ct hdmi_audio_infoframe *fr * * Returns 0 on success or a negative error code on failure. */ -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame) +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame) { return hdmi_audio_infoframe_check_only(frame); } EXPORT_SYMBOL(hdmi_audio_infoframe_check); =20 +static void +hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame, + u8 *buffer) +{ + u8 channels; + + if (frame->channels >=3D 2) + channels =3D frame->channels - 1; + else + channels =3D 0; + + buffer[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); + buffer[1] =3D ((frame->sample_frequency & 0x7) << 2) | + (frame->sample_size & 0x3); + buffer[2] =3D frame->coding_type_ext & 0x1f; + buffer[3] =3D frame->channel_allocation; + buffer[4] =3D (frame->level_shift_value & 0xf) << 3; + + if (frame->downmix_inhibit) + buffer[4] |=3D BIT(7); +} + /** * hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary= buffer * @frame: HDMI audio infoframe @@ -404,7 +427,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size) { - unsigned char channels; u8 *ptr =3D buffer; size_t length; int ret; @@ -420,28 +442,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct h= dmi_audio_infoframe *frame, =20 memset(buffer, 0, size); =20 - if (frame->channels >=3D 2) - channels =3D frame->channels - 1; - else - channels =3D 0; - ptr[0] =3D frame->type; ptr[1] =3D frame->version; ptr[2] =3D frame->length; ptr[3] =3D 0; /* checksum */ =20 - /* start infoframe payload */ - ptr +=3D HDMI_INFOFRAME_HEADER_SIZE; - - ptr[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); - ptr[1] =3D ((frame->sample_frequency & 0x7) << 2) | - (frame->sample_size & 0x3); - ptr[2] =3D frame->coding_type_ext & 0x1f; - ptr[3] =3D frame->channel_allocation; - ptr[4] =3D (frame->level_shift_value & 0xf) << 3; - - if (frame->downmix_inhibit) - ptr[4] |=3D BIT(7); + hdmi_audio_infoframe_pack_payload(frame, + ptr + HDMI_INFOFRAME_HEADER_SIZE); =20 hdmi_infoframe_set_checksum(buffer, length); =20 @@ -479,6 +486,43 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, } EXPORT_SYMBOL(hdmi_audio_infoframe_pack); =20 +/** + * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for Disp= layPort + * + * @frame: HDMI Audio infoframe + * @sdp: secondary data packet for display port. This is filled wit= h the + * appropriate: data + * @dp_version: Display Port version to be encoded in the header + * + * Packs a HDMI Audio Infoframe to be sent over Display Port. This function + * fills the secondary data packet to be used for Display Port. + * + * Return: Number of total written bytes or a negative errno on failure. + */ +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version) +{ + int ret; + + ret =3D hdmi_audio_infoframe_check(frame); + if (ret) + return ret; + + memset(sdp->db, 0, sizeof(sdp->db)); + + /* Secondary-data packet header */ + sdp->sdp_header.HB0 =3D 0; + sdp->sdp_header.HB1 =3D frame->type; + sdp->sdp_header.HB2 =3D DP_SDP_AUDIO_INFOFRAME_HB2; + sdp->sdp_header.HB3 =3D (dp_version & 0x3f) << 2; + + hdmi_audio_infoframe_pack_payload(frame, sdp->db); + + return frame->length + 4; +} +EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp); + /** * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe * @frame: HDMI vendor infoframe diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..d4adb479263e 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -1576,6 +1576,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw); #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ /* 0x80+ CEA-861 infoframe types */ =20 +#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b + /** * struct dp_sdp_header - DP secondary data packet header * @HB0: Secondary Data Packet ID diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index c8ec982ff498..2f4dcc8d060e 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -336,7 +336,12 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, void *buffer, size_t size); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size); -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame); +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame); + +struct dp_sdp; +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version); =20 enum hdmi_3d_structure { HDMI_3D_STRUCTURE_INVALID =3D -1, --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B083C433FE for ; Fri, 25 Mar 2022 17:17:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235457AbiCYRTG (ORCPT ); Fri, 25 Mar 2022 13:19:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377331AbiCYRSl (ORCPT ); Fri, 25 Mar 2022 13:18:41 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 722C1EA37B for ; Fri, 25 Mar 2022 10:16:59 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id u3so11775794wrg.3 for ; Fri, 25 Mar 2022 10:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jrGtzUb1A9DfB89A9VTRS7pXkzrbTky760VebZOoHK0=; b=iQSrsH9BD/B641T27ogEpQH/ydFOoaJdiqKcbNEnBHC71WQgfBklLXsCO2WIbLIfHH SaGxrPOt/7Ecer7T5920AespR95oBeigGrtrdJdDoG+SGqZ87UyNwdAm16FA+7NVTIiQ W82/Fr7wrq68kVqdQCyQctxG3KuRVv4eaXEK9lycWy4wUztjAdlbKTCnIe6aB+M3LPx2 l7XXlSNBwzh6L6FOthayduEAjl1DSGgWG4DRiKUY0b6gdWCRvrbdv+BxHduUheVqyhto QNxPul63aBFuQMVCURI0sTYm6AGH1ZoEvBV+TlYdljbWGU/zc5m36a6wYy7BOw8DQYRv 575g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jrGtzUb1A9DfB89A9VTRS7pXkzrbTky760VebZOoHK0=; b=WAtQbHrx9m15jCMFnCmgHSBHjhxZJE/2cM5fsjOz2Nm4DnT9Mude0JaGw3VDhS4kwj xgclfYO1YWRdFemrdxu5pmRMOSXFgvWPPGz+IadpdSMk6uiiERUUUrxa6qXIgouA9DHK GecbbUhJnMwEw4+Xfg37tviRpKB278lXIF9U0EoyWPyq7D+ePVhLc4jxfGiZyEEQdr8e vUMSupq2uya4/w3vqg4U6Zn1t16oIABKWcOXq75adp80CJUptaO8UxkN5njivFsf4EsF f8Dt4igqz5vQfo3Xrr08gQyGqQjoA7oVTdELJOLiROT7Kd5ogEcXKK2neTl80hfZkP55 mPyQ== X-Gm-Message-State: AOAM533BPZQLMSGfriggRC0e3aRnLV9E0wF5jVuc8jMyHQdxxeh8HNNi PQeFiQeuycuETTcwtAXiBHmP6aHVJY+GTQ== X-Google-Smtp-Source: ABdhPJyr/MHqNoxrEZxkSxI69GzpBet5NWJv730TUb5gDeppIGg95/PkafvqVtTJGsSmjnsTffPwUA== X-Received: by 2002:a5d:47a6:0:b0:205:97fc:8e98 with SMTP id 6-20020a5d47a6000000b0020597fc8e98mr7810743wrb.103.1648228617894; Fri, 25 Mar 2022 10:16:57 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:57 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 07/22] drm/mediatek: dpi: move dpi limits to SoC config Date: Fri, 25 Mar 2022 18:14:56 +0100 Message-Id: <20220325171511.23493-8-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dpi limits to the SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4554e2de1430..4746eb342567 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi= , u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit =3D dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); =20 - limit.c_bottom =3D 0x0010; - limit.c_top =3D 0x0FE0; - limit.y_bottom =3D 0x0010; - limit.y_top =3D 0x0FE0; - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); =20 - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { + .c_bottom =3D 0x0010, + .c_top =3D 0x0FE0, + .y_bottom =3D 0x0010, + .y_top =3D 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7F7BC433EF for ; Fri, 25 Mar 2022 17:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243488AbiCYRTN (ORCPT ); Fri, 25 Mar 2022 13:19:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377236AbiCYRSp (ORCPT ); Fri, 25 Mar 2022 13:18:45 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86E6EE8869 for ; Fri, 25 Mar 2022 10:17:01 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id i67-20020a1c3b46000000b0038ce25c870dso1296289wma.1 for ; Fri, 25 Mar 2022 10:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z0UyPlWzo4y5KtqMIJtLeHp3pqp/XkkAPry5DhA+scQ=; b=nK1lACwsSe7yZ3o29QQ6+6LAQXlxmu33SzVyzVt0/58cIz6yqIZK4LVHTdn/y/nXa5 /phwBmD8Xwg45AKK2t28fX0I+lQWTfsIC5T370z21ccs1KQN4iKIA7ud0yQAqta2HWyL TeQ37+O1zjxS5J6PF+PZvfkRpKYaOcngE9UCN0pClS16YPQVAm1tSnJS3conrPYsL2+j GTY9h2ht0vbLF5K5xr/k8DalzyZmBr6jf2ZGRdlooXYNI5DG2l6pTXxyes3xxGPw9ypn nnZaeIjkaBPqjPI7gWan+GxMlcwfC1cDuPjjR5rUNKGsMPiB+i0cMnOfRZCT37p1TbwL jb/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z0UyPlWzo4y5KtqMIJtLeHp3pqp/XkkAPry5DhA+scQ=; b=aP2/XmhrstCIO9RF99MnuO6jzfGyvRElHN+h4cGWNqpeP/v5RM12+PGdcIDKiCiE5e Fip0tdL4uGP5BNLOJZxOc1v1xI8gqvbPyy1E+JFJ+oL1AysMF8iTMOWS9j8lVuo1Jd70 iB13/OAj6Mi8bKS4h5+hNtcrmYRRAeIVcWpBMb1LLgrxoA5oCDVBIPzXsBCA3FB9KmQB hNboDJpbskmpV30qDf77wTbCKey40MMbgUNiK2NdjGQR6/s/iLzLcG4h/ye4o60eNPbc DWvnrNATS5ZLW61dT9hBk8SjIUlZcSDLJfTS5HM8AMFjGAEr16s0HGacibRjIj0WLhml c+6A== X-Gm-Message-State: AOAM5303Y7cBJLXPlIpr1c1ujFFqiSGlRaG0YZBrwvhag1afTZ8uitQN COAVAl8vQbZKI7uWrh+qji9FMg== X-Google-Smtp-Source: ABdhPJyXo6ik6r6RQSTysIePMHUG22CLd2y8/JaDeZs3aASy/dXgh8ev1U594xWC7kSgpqvduNejAg== X-Received: by 2002:a05:600c:4e4b:b0:38c:eebc:2ec4 with SMTP id e11-20020a05600c4e4b00b0038ceebc2ec4mr2058412wmq.47.1648228619892; Fri, 25 Mar 2022 10:16:59 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:59 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 08/22] drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config Date: Fri, 25 Mar 2022 18:14:57 +0100 Message-Id: <20220325171511.23493-9-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support SoCs without CK/DE pol support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4746eb342567..545a1337cc89 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -211,13 +212,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; =20 - pol =3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL)= | + mask =3D HSYNC_POL | VSYNC_POL; + pol =3D (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_PO= L) | (dpi_pol->vsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |=3D CK_POL | DE_POL; + pol |=3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } =20 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -799,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -809,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -818,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -827,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58150C433EF for ; Fri, 25 Mar 2022 17:17:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353548AbiCYRTR (ORCPT ); Fri, 25 Mar 2022 13:19:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377323AbiCYRSr (ORCPT ); Fri, 25 Mar 2022 13:18:47 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8DF6E9C8C for ; Fri, 25 Mar 2022 10:17:03 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id u3so11776028wrg.3 for ; Fri, 25 Mar 2022 10:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6eEHSj6Z+4nINe2TDPCkNf9jm6eypipKQx8L5na/Yyk=; b=7UtYysHnvqeWIeZMuZiEC8IPVZDMSKlAbRO5E8BytTts4xLZ4UVAs9U89uPHLnkXDR CZ/+ax1ln/JmF6JZgHsnGO4JO0H5YV8MQ883D1jkSlu4H+heh0+z23oteIQioUnwTH45 nnzH6k8Yc++ina40Z3HUalg2xzJYHImxhlKh4jPdHc50J4VSluchb0fpfZD1mTnXuQ0f JZH+0RErOPJbq0lI9y0KPqW0djaXnkwxt+TI/fn+Ry6HRtN1yp+BMIejkA8pOf4D+it5 0cbds2cn1eOD6gIf9Kirm+ZODdIRx9/zoEJDsMlRX+NPASqJ9Coi4ClpVlt63Y1K4NUF Myfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6eEHSj6Z+4nINe2TDPCkNf9jm6eypipKQx8L5na/Yyk=; b=VZt8zqdiAnqPTG/YYItVj8vpjRcc/JY1tWp+VgKpxIqr9ADd5EHCQPJ2ohqC+/KmCc PpYEoaT27+7BZFAGa6mIhvvKFhvCO5efh3qkHbWHWRtPCa3FW+IBSiKX4RsCibwsrulQ syLWK1I25t2ZOn3h0ukco/m4jmSEEDTwVdK+SydQaX6BkHH6JZsH3mPIllwdneSvc8jd HYpdB3MEkmxUG2bIGWMEMpMwSZwxV1Y3wxwL3r9pN8eSjBbZYglWMmmPzXKJ0xjHV3pb b61jFFFgGNqERU2H/FZSLV6YPHjuT1LIMhlz9N+BgOkVn0XUy2/1gVJkvhDOKSaUQU8X LPrA== X-Gm-Message-State: AOAM531TVLKRTa3vvxryw/HAZ++dKcBtB0+Gxvr+dLGvaZBn4C0Zjbef 1AZ4oN13nRTPzXWW+ZeoqXxMgQ== X-Google-Smtp-Source: ABdhPJyzuPxAQnBUd0DqX9rA/COSrSXDlL45D+hPdYrqXIjWtxya//AY+dPfwxGIaXGeO3bCs3LXiw== X-Received: by 2002:a5d:6c67:0:b0:204:ff0:87a8 with SMTP id r7-20020a5d6c67000000b002040ff087a8mr10162708wrz.627.1648228622001; Fri, 25 Mar 2022 10:17:02 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:01 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 09/22] drm/mediatek: dpi: implement a swap_input toggle in SoC config Date: Fri, 25 Mar 2022 18:14:58 +0100 Message-Id: <20220325171511.23493-10-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support SoCs without swap_input support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 545a1337cc89..454f8563efae 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dp= i *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30421C433F5 for ; Fri, 25 Mar 2022 17:17:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377332AbiCYRT0 (ORCPT ); Fri, 25 Mar 2022 13:19:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243363AbiCYRTL (ORCPT ); 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:03 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 10/22] drm/mediatek: dpi: move dimension mask to SoC config Date: Fri, 25 Mar 2022 18:14:59 +0100 Message-Id: <20220325171511.23493-11-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dimension mask to the SoC config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 454f8563efae..bf098f36a466 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ + u32 dimension_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -156,30 +158,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } =20 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -813,6 +815,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -825,6 +828,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -847,6 +852,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:05 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 11/22] drm/mediatek: dpi: move hvsize_mask to SoC config Date: Fri, 25 Mar 2022 18:15:00 +0100 Message-Id: <20220325171511.23493-12-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the hvsize mask to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index bf098f36a466..6eeda222a973 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; + /* HSIZE and VSIZE mask (no shift) */ + u32 hvsize_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *d= pi, bool inter) =20 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 hei= ght) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } =20 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:07 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 12/22] drm/mediatek: dpi: move swap_shift to SoC config Date: Fri, 25 Mar 2022 18:15:01 +0100 Message-Id: <20220325171511.23493-13-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the swap shift value to SoC specific config Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6eeda222a973..6d4d8c6ec47d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; + u32 channel_swap_shift; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -349,7 +350,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, break; } =20 - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << dpi->conf->channel_swap_shif= t, + CH_SWAP_MASK); } =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -821,6 +823,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -835,6 +838,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -848,6 +852,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -861,6 +866,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CE0CC433F5 for ; Fri, 25 Mar 2022 17:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239423AbiCYRUw (ORCPT ); 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:10 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 13/22] drm/mediatek: dpi: move the yuv422_en_bit to SoC config Date: Fri, 25 Mar 2022 18:15:02 +0100 Message-Id: <20220325171511.23493-14-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the yuv422 en bit to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6d4d8c6ec47d..40254cd9d168 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -356,7 +357,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -824,6 +826,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +842,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +857,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -867,6 +872,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6EEEC433EF for ; Fri, 25 Mar 2022 17:36:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbiCYRiY (ORCPT ); Fri, 25 Mar 2022 13:38:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232027AbiCYRiV (ORCPT ); Fri, 25 Mar 2022 13:38:21 -0400 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2A8810C53C for ; Fri, 25 Mar 2022 10:36:42 -0700 (PDT) Received: by mail-wr1-f52.google.com with SMTP id t11so11791145wrm.5 for ; Fri, 25 Mar 2022 10:36:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KMvfz+B/fO4XaHRDT9xBCSiSBmXbtSzCBQeXFCLeYNU=; b=p/bzvqcoe7xmjeGx0bzZZKr3QkGpvN1OffJqFUZIQSXRwAILqcf+RcRhigcNIVuytf gdMEjPWkXeWQUCajFWsp/Aue26OZT25LAtjITkO/AbC7JId1qwsj5MMxiZobBbJXcGBA XxelquKvDUapJkpBpWzf6hj7DWbR/IkirEcEat0Tcvi6e7sL8jfWN/dm9iVMQlYhEj1t dJTdtiFJv/lWnkTJ9S++ymuxEz5s8t4NoGCrjK3oSoDoFNwFQSnpE+l6ExBubJ1I/2OA jbh+S2ZhgOPMjLJ9Bbx4HrkzcNbX3QXmv795tI/LYBkxXIzIvObYQGo/LdNRhdXcgzE9 xEdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KMvfz+B/fO4XaHRDT9xBCSiSBmXbtSzCBQeXFCLeYNU=; b=uIUWd1i+OiGckq/26OiP1tMN5VnCRXn0EjO5wfrqjF606GSsV2oEgIBUe7R2gFPD+U 7pgcyKL+99z6Pg3HYG4ABrEo9LKF7wkZlIvgvAuGT36Con1R98uCCIrLvS1BRCqUGZuO kfG+RBsDxu6aUQCx8WxsNGZo5xbq8z2/Kwzsv1m7w1cI9Xne32TpV+OBUO6pYLxWUDaR Q0Qi5BAcMNhOa8NjxucY5WDRnuIHEOg6VVPKW3TA4Rrcv9HRUEAafCr6EwkGWObcpFXg 0Xok6FRkelgsnmGyHEsNoXwy0Fjui6JjlWxn+xvOPiCnmQcAA8IsxIdntzolsfP85re0 gtrQ== X-Gm-Message-State: AOAM530bgHEbeuswru8xTxXfVyxYu2TwYJYpr5deZqljfusjNdXjgj9A +II37UvF/Z6muXTlN3INI5r9djoM6zod1g== X-Google-Smtp-Source: ABdhPJx6jyzSTLucPsEMVBbYsGniaNIpeoyfEh/lkHKnA/tWkx4gSFEuQudHfuWGo39hyWySDlHC0A== X-Received: by 2002:a5d:4d43:0:b0:205:9376:5d8 with SMTP id a3-20020a5d4d43000000b00205937605d8mr8887728wru.193.1648228632808; Fri, 25 Mar 2022 10:17:12 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:12 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 14/22] drm/mediatek: dpi: move the csc_enable bit to SoC config Date: Fri, 25 Mar 2022 18:15:03 +0100 Message-Id: <20220325171511.23493-15-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the csc_enable bit to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 40254cd9d168..eb969c5c5c2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -363,7 +364,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi= *dpi, bool enable) =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); } =20 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -827,6 +829,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -843,6 +846,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -858,6 +862,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02A22C433F5 for ; Fri, 25 Mar 2022 17:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232676AbiCYRdz (ORCPT ); Fri, 25 Mar 2022 13:33:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232523AbiCYRdp (ORCPT ); Fri, 25 Mar 2022 13:33:45 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9387D11C7E8 for ; Fri, 25 Mar 2022 10:32:02 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id d7so11791557wrb.7 for ; Fri, 25 Mar 2022 10:32:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gekf4ShA07jnHMwX8opXGKHS7o5P4PEEDeyP8c+Tl4k=; b=v89o/VthIOpkZePFFUZ904rr222JNfb4Eqor6XMfeyiOH1gUyYvXLwigK6phCMnvrJ UiOtgR60ps09C/wN81IjrESPmEzjzjBPDaOxpc9S3IEvlexxuS6N7xGlR4u9Op5V+Dpy 6Z7huG8LY9STVycrbMwk5XOu9rdiSbA3xJ0I0reVVTxb+/k4wmOucVpBpgr5JQfQmf8E zqmIZMmm0KmlZoLR2YGXJ58/NWWSQz3YUX1NCgcYeBNE8epipT8aTnDvetXUfWhpHSs7 QEyOby5RfU2xgeWP+mIrt5hlEP1UyP33QKb2+ixqVHcUrMTcg3EM4rjepMaDYdUQX5aj A8MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gekf4ShA07jnHMwX8opXGKHS7o5P4PEEDeyP8c+Tl4k=; b=bl5GtNiJ670spOUoLD6UkYKcaeJSv32oSoJQYFOESEJZc1efYvZ/Ep/ChkscVYbi3J +DmsUVbV1wNniiQyw8sVjf/jfB9wfKNSwsNwXBWwErPuGcSq2lguCQpimb+oHhy3O4mn XEnhM4q0D7FIi/dn26eyTk4bt9YlmhvsArm0A6hH+gbdmEyZtPvpB0tl+efmpnGSmMvd jBojo534a/8zq7koeHrmu1sHckAwp7poKhnuzgm2+dojlytRPU3cgQkQ5tnVH1Lh/4as R0bLBNPiGlfZLVl5rw6SYIyeqgwXLsmvj38uAUB4NeevQ5dcDeY32Jyp+aejoNKwDyxf 8gXQ== X-Gm-Message-State: AOAM5337nChD/a77eDyPmjmmdksdXyS8OFeB3txso9v0xiP5cGFOiFY5 yLOIBHByo7gXJ+hxWILdAEBXtUBLTFN8yQ== X-Google-Smtp-Source: ABdhPJzRsvWraZSp+h9Go9W+WTfcVPlaBmBsiQWwsSeG9pukCx87LlCbm0Csn0fmRJVD7VAGXXQG6g== X-Received: by 2002:adf:db92:0:b0:205:9c92:f1e3 with SMTP id u18-20020adfdb92000000b002059c92f1e3mr5993364wri.515.1648228635347; Fri, 25 Mar 2022 10:17:15 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:14 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann Subject: [PATCH 15/22] drm/mediatek: dpi: Add dpintf support Date: Fri, 25 Mar 2022 18:15:04 +0100 Message-Id: <20220325171511.23493-16-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 78 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 ++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 3 +- 6 files changed, 120 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index eb969c5c5c2e..8198d3cf23ac 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -498,11 +499,11 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, =20 vm.pixelclock =3D pll_rate / factor; if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -515,9 +516,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width =3D vm.hsync_len; - hsync.back_porch =3D vm.hback_porch; - hsync.front_porch =3D vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } else { + hsync.sync_width =3D vm.hsync_len; + hsync.back_porch =3D vm.hback_porch; + hsync.front_porch =3D vm.hfront_porch; + } hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -559,13 +566,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -642,7 +656,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_brid= ge *bridge, dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -801,6 +818,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -810,6 +837,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -817,6 +850,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -882,6 +922,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1004,6 +1057,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe1662..91b32dfffced 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,29 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL BIT(0) +#define INT_MATRIX_SEL_MASK (0x1F << 0) +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index f683e768d61b..3260f773fd3f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -405,6 +405,11 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_CO= MP_TYPE_MAX] =3D { [MTK_DISP_WDMA] =3D "wdma", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", + [MTK_DP_INTF] =3D "dp-intf", + [MTK_DISP_PWM] =3D "pwm", + [MTK_DISP_MUTEX] =3D "mutex", + [MTK_DISP_OD] =3D "od", + [MTK_DISP_BLS] =3D "bls", }; =20 struct mtk_ddp_comp_match { @@ -425,6 +430,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_ID_MAX] =3D { [DDP_COMPONENT_DPI1] =3D { MTK_DPI, 1, &ddp_dpi }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -544,6 +551,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 09ac9496547d..7c908c6c23b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 055dafd7d3fd..4cbfa7cd5c57 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -532,6 +532,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -635,7 +637,8 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_RDMA || comp_type =3D=3D MTK_DPI || - comp_type =3D=3D MTK_DSI) { + comp_type =3D=3D MTK_DPI || + comp_type =3D=3D MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, component_compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 64c77c4a6c56..abb470e201b0 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -17,11 +17,12 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, - DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, DDP_COMPONENT_DSC0, DDP_COMPONENT_DSC1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C45BC433EF for ; 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[2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:17 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com Subject: [PATCH 16/22] drm/meditek: dpi: Add matrix_sel helper Date: Fri, 25 Mar 2022 18:15:05 +0100 Message-Id: <20220325171511.23493-17-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 8198d3cf23ac..82f97c687652 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -385,6 +385,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi= *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } =20 +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color= _format format) +{ + u32 matrix_sel =3D 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <=3D 720) + matrix_sel =3D 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -392,6 +411,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -399,6 +419,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B72A0C433F5 for ; Fri, 25 Mar 2022 19:49:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231524AbiCYTum (ORCPT ); Fri, 25 Mar 2022 15:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231653AbiCYTud (ORCPT ); Fri, 25 Mar 2022 15:50:33 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C16A240660F for ; Fri, 25 Mar 2022 12:33:45 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id m30so12185372wrb.1 for ; Fri, 25 Mar 2022 12:33:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JFsX0/WPKs9zzqrnPVWjuO4JsDdA9a8A6nvPaPiJns8=; b=ttw/ZscnikrmchtQUVLbfdfnd5BAGhFQ80QAAndhJ0bfvNNFhA+6xzv/wo2jdpAgkG tL6TrK2sji2h2nWmjRJGgUN127N8OyexMtfygBoWN5jO4PcrXOEPn9BqjnbxJ6t+6kKr ykRbLlpXW7WOXnpeANjARiJKdy06a8hqCp37MAntImMVBzfyvxPAm0sd3s32OnnWLu39 J6SmC9YP8oaJ50wQOzk8YmdBwdlBhzcVQfgCoDsnLKHSeA7dW9PYluP/3DSaXNLekDz6 Ab5DzZ1vwch1k12GTNajjEf53SK0iHHsasxB71VU6XxYCHk1S+YCzn3Lw5oI3/icbv4B nrcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JFsX0/WPKs9zzqrnPVWjuO4JsDdA9a8A6nvPaPiJns8=; b=dH3ASS0iGHmHcbpuySOgfjv1hvD/OLQr+3lc9epiUr2GBowa4/OEUwBNo4RqhMh+yB wai0j4VEvmmJvqFolxd43qH6/ktOR1tr7VrjILPutDnjFpK/znT4N8sk21VOyKMX+owV ZYwNELLP5rsPFo8glyBouCXJfWXalcOeG/stCLrFxN9fBUpYToTjKTjeScvHg7/oHOKp RF6cn5fJmcmAMHYmRFd0L9oE1gidyURM1sXDxgixF8LM6JC7k0mGy+rK7HlevtDtcY0x a8+SGol1Wp5tNKR2XLDjg3j9SN/sMcW0sphNy37Ug8AsoPRsA7wVjzm02fbAAjB/05iF STLA== X-Gm-Message-State: AOAM531pi82npdDFWm2hdSmYN3wFGYcP0EiaJBJ3sHIktouVO25LyP/m mopMXwRNolTBEztbCdd3zQyu/24KZ5+sbA== X-Google-Smtp-Source: ABdhPJyIWghkQcXRLBEBJVnjGL8Mvb1ANT6alMBDrmNnuNK8givD3IDNYo9MfJGFS5A2lGTUchOSZA== X-Received: by 2002:a5d:5046:0:b0:1ed:9eac:bade with SMTP id h6-20020a5d5046000000b001ed9eacbademr9954861wrt.697.1648228639903; Fri, 25 Mar 2022 10:17:19 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:19 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann Subject: [PATCH 17/22] phy: phy-mtk-dp: Add driver for DP phy Date: Fri, 25 Mar 2022 18:15:06 +0100 Message-Id: <20220325171511.23493-18-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This is a new driver that supports the integrated DisplayPort phy for mediatek SoCs, especially the mt8195. The phy is integrated into the DisplayPort controller and will be created by the mtk-dp driver. This driver expects a struct regmap to be able to work on the same registers as the DisplayPort controller. It sets the device data to be the struct phy so that the DisplayPort controller can easily work with it. The driver does not have any devicetree bindings because the datasheet does not list the controller and the phy as distinct units. The interaction with the controller can be covered by the configure callback of the phy framework and its displayport parameters. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 8 ++ drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-dp.c | 202 ++++++++++++++++++++++++++++++ 4 files changed, 212 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-dp.c diff --git a/MAINTAINERS b/MAINTAINERS index 960add1b4079..f3d4600e0b1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6570,6 +6570,7 @@ L: linux-mediatek@lists.infradead.org (moderated for = non-subscribers) S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ +F: drivers/phy/mediatek/phy-mtk-dp.c F: drivers/phy/mediatek/phy-mtk-hdmi* F: drivers/phy/mediatek/phy-mtk-mipi* =20 diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 55f8e6c048ab..f7ec86059049 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -55,3 +55,11 @@ config PHY_MTK_MIPI_DSI select GENERIC_PHY help Support MIPI DSI for Mediatek SoCs. + +config PHY_MTK_DP + tristate "MediaTek DP-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Support DisplayPort PHY for Mediatek SoCs. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index ace660fbed3a..4ba1e0650434 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -3,6 +3,7 @@ # Makefile for the phy drivers. # =20 +obj-$(CONFIG_PHY_MTK_DP) +=3D phy-mtk-dp.o obj-$(CONFIG_PHY_MTK_TPHY) +=3D phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) +=3D phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) +=3D phy-mtk-xsphy.o diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c new file mode 100644 index 000000000000..e9c95879dbf4 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DisplayPort PHY driver + * + * Copyright (c) 2021 BayLibre + * Author: Markus Schneider-Pargmann + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PHY_OFFSET 0x1000 + +#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14) +#define TPLL_SSC_EN BIT(3) + +#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C) +#define BIT_RATE_RBR 0 +#define BIT_RATE_HBR 1 +#define BIT_RATE_HBR2 2 +#define BIT_RATE_HBR3 3 + +#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) +#define DP_GLB_SW_RST_PHYD BIT(0) + +#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) +#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) +#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) +#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438) +#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) +#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT ((BIT(2) | BIT(4)) << 8) +#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) +#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3) +#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) +#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT ((BIT(2) | BIT(5)) << 16) +#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) +#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) +#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) +#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) +#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) +#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) +#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) +#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 +#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) +#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 +#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) + +struct mtk_dp_phy { + struct regmap *regs; +}; + +static int mtk_dp_phy_init(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 driving_params[] =3D { + DRIVING_PARAM_3_DEFAULT, + DRIVING_PARAM_4_DEFAULT, + DRIVING_PARAM_5_DEFAULT, + DRIVING_PARAM_6_DEFAULT, + DRIVING_PARAM_7_DEFAULT, + DRIVING_PARAM_8_DEFAULT + }; + + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + + return 0; +} + +static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts = *opts) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 val; + + if (opts->dp.set_rate) { + switch (opts->dp.link_rate) { + default: + dev_err(&phy->dev, + "Implementation error, unknown linkrate %x\n", + opts->dp.link_rate); + return -EINVAL; + case 1620: + val =3D BIT_RATE_RBR; + break; + case 2700: + val =3D BIT_RATE_HBR; + break; + case 5400: + val =3D BIT_RATE_HBR2; + break; + case 8100: + val =3D BIT_RATE_HBR3; + break; + } + regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); + } + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, + TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); + + return 0; +} + +static int mtk_dp_phy_reset(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 0); + usleep_range(50, 200); + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 1); + + return 0; +} + +static const struct phy_ops mtk_dp_phy_dev_ops =3D { + .init =3D mtk_dp_phy_init, + .configure =3D mtk_dp_phy_configure, + .reset =3D mtk_dp_phy_reset, + .owner =3D THIS_MODULE, +}; + +static int mtk_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_dp_phy *dp_phy; + struct phy *phy; + struct regmap *regs; + + regs =3D syscon_regmap_lookup_by_phandle(dev->of_node, "regmap"); + + if (IS_ERR(regs)) + return PTR_ERR(regs); + + dp_phy =3D devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); + if (!dp_phy) + return -ENOMEM; + + dp_phy->regs =3D regs; + + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); + + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create DP PHY: %ld\n"= , PTR_ERR(phy)); + + phy_set_drvdata(phy, dp_phy); + + return 0; +} + +struct platform_driver mtk_dp_phy_driver =3D { + .probe =3D mtk_dp_phy_probe, + .driver =3D { + .name =3D "mediatek-dp-phy", + }, +}; +module_platform_driver(mtk_dp_phy_driver); + +MODULE_AUTHOR("Markus Schneider-Pargmann "); +MODULE_DESCRIPTION("MediaTek DP PHY Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Sep 22 07:33:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63E5BC433F5 for ; Fri, 25 Mar 2022 19:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231548AbiCYTqM (ORCPT ); Fri, 25 Mar 2022 15:46:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231628AbiCYTqA (ORCPT ); Fri, 25 Mar 2022 15:46:00 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74D8C1EC63A for ; Fri, 25 Mar 2022 12:27:25 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id w4so12108973wrg.12 for ; Fri, 25 Mar 2022 12:27:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pKYjYwRpB4h7RRL3cstt6OLqAd2/FqdfjKzUbHCjoWU=; b=kGUS4eR2U4VMo/fAksl+VgFsFJXLnC8DFz62sPM+snsVw6S3bJMFXXdZ4tMiBtHYOh pJ7LMW0SSwk/IE4JD8A0bBEeCTAz0zC6q8gUwr/OSNPxZCS3ZKVRyK0mxo1qDjTk5frM oT5bKGprwEU3UUdX8XXOtjrgIIne81n5yGfJU6PCTToQuXsQOjyhbLGuvOevo7cKKkzX C5f6TxoaAzXWI3iO9mg7HcDPnrrvwZdPRVkHEmE0zcuLuNQ8jord4oxxt6kyhcGR2taN KSlCqa5GOtSPTuV95Cvx9vKM99Mm7m5x0OXD5MKCWRF+3Qhi+feJYAMzRaKS4XQwWTdS aWdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pKYjYwRpB4h7RRL3cstt6OLqAd2/FqdfjKzUbHCjoWU=; b=RoSKmd6kwKmfvZebLhEQQ7w3MPjVMBJNzinm6MkuICT1+fEb6KrJEnosuuVjBoclvB /4QB6xcBrxzlKELjQFPLDMqWmnWfiU2onlOagK2AvacxdMCmLE+OmIzrd7bTssNw4M+B fjrmgo3yEhHlw+5L1vZ/LslLf3/2Rw98k6Au6ML4PSV6TR4PiA/AsklomzenmYmzVPwT vc2XXL7hmhHwTy+gokhbwuCHBVWfGUAwa2QYqGA2CyTPQrW9z8h5oU+uysPfMiZoIto1 b29BulwbQMBkT0fqyYsYcqN9kC19SrVQ0CQSNX3b7qwENkUt++5nW2tu3YWgIbxkZHod Ef3Q== X-Gm-Message-State: AOAM533oyBuRr/jkIDPnTh6jpck4aa6hU++Hvhnw1zYOjMLIHtDB5Tc3 U1PaOvSUITlmZMo9bW2gKepm3yzr/+Jn3A== X-Google-Smtp-Source: ABdhPJyMgPYDEJw3WY3vuojt+lBzWrG9a9nbVMY0lmdkWBZBBzgPnOQv9X1x4MQRXTws1Zvo33nY7A== X-Received: by 2002:a5d:6b4c:0:b0:1e6:8ece:62e8 with SMTP id x12-20020a5d6b4c000000b001e68ece62e8mr10023997wrw.201.1648228643632; Fri, 25 Mar 2022 10:17:23 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:17:23 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org, markyacoub@google.com, Markus Schneider-Pargmann , kernel test robot Subject: [PATCH 18/22] drm/mediatek: Add mt8195 Embedded DisplayPort driver Date: Fri, 25 Mar 2022 18:15:07 +0100 Message-Id: <20220325171511.23493-19-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. It supports the mt8195, the embedded DisplayPort units. It offers DisplayPort 1.4 with up to 4 lanes. The driver shares its iomap range with the mtk-dp-phy driver using the regmap/syscon facility. This driver is based on an initial version by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reported-by: kernel test robot --- drivers/gpu/drm/mediatek/Kconfig | 8 + drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_dp.c | 2223 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dp_reg.h | 568 ++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 2803 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kc= onfig index 2976d21e9a34..03ffa9b896c3 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -28,3 +28,11 @@ config DRM_MEDIATEK_HDMI select PHY_MTK_HDMI help DRM/KMS HDMI driver for Mediatek SoCs + +config MTK_DPTX_SUPPORT + tristate "DRM DPTX Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select PHY_MTK_DP + select DRM_DP_HELPER + help + DRM/KMS Display Port driver for Mediatek SoCs. diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index a38e88e82d12..8bfd9fb64db9 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -22,3 +22,5 @@ mediatek-drm-hdmi-objs :=3D mtk_cec.o \ mtk_hdmi_ddc.o =20 obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mediatek-drm-hdmi.o + +obj-$(CONFIG_MTK_DPTX_SUPPORT) +=3D mtk_dp.o diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c new file mode 100644 index 000000000000..e8d918e92e31 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -0,0 +1,2221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2021 BayLibre + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include