From nobody Sun Sep 22 05:35:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64384C433EF for ; Wed, 23 Mar 2022 09:19:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243125AbiCWJVR (ORCPT ); Wed, 23 Mar 2022 05:21:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234729AbiCWJVQ (ORCPT ); Wed, 23 Mar 2022 05:21:16 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDC4F5D654 for ; Wed, 23 Mar 2022 02:19:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 944671F43FE1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1648027185; bh=Knb3Qbz4FitufncDzqCAXY9iWmZ7oO2JSE4/JnyALn8=; h=From:To:Cc:Subject:Date:From; b=XGwOPIe2HYdU9TA+y06TluGf1bR0lZefNH5+gEcIAZBM/eQLWcnKIgS44l8x1HE39 oFb8+spytzkN1/C8bUEPowRsB0Vj9XIrInGe5xiYLAFbnzmxf+XR/lRJuX18t/zWwG m47keWojG2LHU1FnBoAIq9X+Fkrd5Jjr8f6tDo9pGU/2ilPTJmALeB6Z2c6FfWSDVp kcnhzcEu7Sn447yW0CerVS8bNy8SbHAcJUGKZD0rRH9uKIOh4T8ypYgbPMkjRg2AlN RZY4iayneA5Y4fPh3KY582mrmFONwVCuzZZZEddLKJ0i4jqohN4tuaJhaSz20qestH KNixtcFQRR6mw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, rex-bc.chen@mediatek.com, AngeloGioacchino Del Regno Subject: [PATCH v2] soc: mediatek: mmsys: Add sw0_rst_offset for MT8192 Date: Wed, 23 Mar 2022 10:19:32 +0100 Message-Id: <20220323091932.10648-1-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT8192 has the same sw0 reset offset as MT8186: add the parameter to be able to use mmsys as a reset controller for managing at least the DSI reset line. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- v2: Change the offset to 0x160 (as defined for MT8186). Thanks, Rex-BC! drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 4fc4c2c9ea20..f69521fabcce 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -70,6 +70,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_dr= iver_data =3D { .clk_driver =3D "clk-mt8192-mm", .routes =3D mmsys_mt8192_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8192_routing_table), + .sw0_rst_offset =3D MT8186_MMSYS_SW0_RST_B, }; =20 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =3D { --=20 2.35.1