From nobody Mon Jun 22 15:46:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14F78C43219 for ; Mon, 21 Mar 2022 14:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243440AbiCUOeN (ORCPT ); Mon, 21 Mar 2022 10:34:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350104AbiCUOd7 (ORCPT ); Mon, 21 Mar 2022 10:33:59 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1983A5D1A8 for ; Mon, 21 Mar 2022 07:32:34 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id j18so11334280wrd.6 for ; Mon, 21 Mar 2022 07:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jPNbf4VBXaKauQrD5GdOw/7C1sM2aDR3HnxDjhZ0elg=; b=K04KZ2llvCIBVjpLXRbj+FItZXFlk4ZVLcXMU/n3uOzyXQkjIt2p8UQRjAN1JRYeHw odN5bc3b7y61QwvNr5Voo9HYGe+n6sUBYkPIHRCLkL2b8MpipkOPtqLac92fMqy93U/2 9Xve7ZthNZPcBZUKdMEkBljxtgCh7T6f6FGbg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jPNbf4VBXaKauQrD5GdOw/7C1sM2aDR3HnxDjhZ0elg=; b=qAFkZ8w9rZzE+yAha0gbw05EpebRUjYC1oPY4Ldx+fRz5O9Wmo/Gvn5Gt8fkb7DLFU w6AmuVM7U/W6cbEP29juEdfO3Qf6b38ql0k6i+1k3UXZZOb4MMfMitVwdeCYgBVToVQP yJozQ8NSNVHM5E3Kei1jfe/s6Aj67lzUQPpenWyQNQ5dSowp1VlOcKGQjaJXswJAG8fk GNtW6QsOZiYaD7hdmXOEpkP/Iht2tnSdKKReJE3h4jBCxNcppUQuIgpg1HMfm1DsftRh 2Y4Eh/2JyLQhOtKb/xEKqz2X9+hsBS+Z/nyuaFungKwQ3+pNfGtT1ALAyPReFEnIHS1x IqSw== X-Gm-Message-State: AOAM532oCuBz45hUgHAz+bu0DsPKS4CBUewzr8roWxekkmk6uzT4GD5a QzNCFxaSqaTFvgEd3ig/nYnqqA== X-Google-Smtp-Source: ABdhPJxAUNMAkxYkB4uOST35byIe9LqZT6SPgd/wDbe3ZFo/1vnlqpEDwMr6f9llJhrZuMausBRxrg== X-Received: by 2002:adf:ea06:0:b0:203:ed67:6093 with SMTP id q6-20020adfea06000000b00203ed676093mr15652317wrm.596.1647873152722; Mon, 21 Mar 2022 07:32:32 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:32 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 1/4] dt-bindings: add mfd/cros_ec definitions Date: Mon, 21 Mar 2022 14:32:19 +0000 Message-Id: <20220321143222.2523373-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cr= os_ec.h new file mode 100644 index 000000000000..e02414eae622 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif --=20 2.35.1.894.gb6a874cedc-goog From nobody Mon Jun 22 15:46:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE677C433EF for ; Mon, 21 Mar 2022 14:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346823AbiCUOfQ (ORCPT ); Mon, 21 Mar 2022 10:35:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350117AbiCUOeC (ORCPT ); Mon, 21 Mar 2022 10:34:02 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 858A55D66F for ; Mon, 21 Mar 2022 07:32:36 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id bg31-20020a05600c3c9f00b00381590dbb33so8496607wmb.3 for ; Mon, 21 Mar 2022 07:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=327v7tDtO2GmRxGp/EXz/K90M6uOA2heqpeDOYqPsME=; b=Gme6ELhnFvcMetNZIUvxqYQsfLCOlxkDNaNo+piNbLOzDEbxYZBKO6vEpqZAaB1WnN 81V4Ep3yPDZjGFeOmzqqRtolKOxSDjPAHW/wEE0CCraGO1m2C9LiWpUNwrBLOJV9kAnJ q2gkGbLvZoDdcx7pc6uK07DEGKdqU8qh23TAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=327v7tDtO2GmRxGp/EXz/K90M6uOA2heqpeDOYqPsME=; b=sHMCVaIaalnvE2btAYT/3lonBJdKrMTsxIRdPcDlFO0axCuzR9LjGF8J7hdTUvVLwf 3z+9dr494qlcZ5AUlu3z8QosMFIhrPW9kaxT6cl/eYts0qPPykTB4zHPkvc0NwR7H4iQ yCp7xl/n9JZ3h4IGqKxc3yGi4K5bzb8Gs8zR5OBdVNXcBxNsydcDN+eXtyNRWQZZyIwN zGlrL3zQFnKNUIRWfVFOaqsBkRZYqmsrUFYqhF7kE1HIqIaBmaNcTfrgG974qcnMlo/S vuGjSvcYc7msso6Pdhz3tpjRblCo9ULHPWLUaWn/amAIB7Jxa0wOPrwxkAGd9i/M/gll 3ncg== X-Gm-Message-State: AOAM533xL5YSbR3gx4ThsjEOsDwBBzSNQ55LLHdLSGjx+KkIm2O0Ou5w Cj5cnb0lXW4+27mRTEQMQ2dv3g== X-Google-Smtp-Source: ABdhPJwzl2vh0K7GQ4OXRU1D1Fb+QB9pHhfF1JMG2/3unQTFxnQYcqU9FeomC+1Y42B7ORX5cObwuQ== X-Received: by 2002:a1c:e915:0:b0:37b:d847:e127 with SMTP id q21-20020a1ce915000000b0037bd847e127mr20044602wmc.180.1647873154996; Mon, 21 Mar 2022 07:32:34 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:34 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 2/4] drivers: pwm: pwm-cros-ec: add channel type support Date: Mon, 21 Mar 2022 14:32:20 +0000 Message-Id: <20220321143222.2523373-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. Signed-off-by: Fabio Baltieri --- drivers/pwm/pwm-cros-ec.c | 80 +++++++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..77867fd16c49 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -12,17 +12,21 @@ #include #include =20 +#include + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; =20 /** @@ -58,14 +62,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, str= uct pwm_device *pwm) kfree(channel); } =20 -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 d= uty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type =3D EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type =3D EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x, + u16 duty) +{ + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params =3D &buf.params; struct cros_ec_command *msg =3D &buf.msg; + int ret; =20 memset(&buf, 0, sizeof(buf)); =20 @@ -75,14 +96,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *= ec, u8 index, u16 duty) msg->outsize =3D sizeof(*params); =20 params->duty =3D duty; - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 return cros_ec_cmd_xfer_status(ec, msg); } =20 -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x) { + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +134,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device = *ec, u8 index) msg->insize =3D sizeof(*resp); msg->outsize =3D sizeof(*params); =20 - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 ret =3D cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +174,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, */ duty_cycle =3D state->enabled ? state->duty_cycle : 0; =20 - ret =3D cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret =3D cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; =20 @@ -149,7 +190,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip= , struct pwm_device *pwm, struct cros_ec_pwm *channel =3D pwm_get_chip_data(pwm); int ret; =20 - ret =3D cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret =3D cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +245,13 @@ static const struct pwm_ops cros_ec_pwm_ops =3D { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; =20 /* The index field is only 8 bits */ for (i =3D 0; i <=3D U8_MAX; i++) { - ret =3D cros_ec_pwm_get_duty(ec, i); + ret =3D cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -251,17 +292,26 @@ static int cros_ec_pwm_probe(struct platform_device *= pdev) chip =3D &ec_pwm->chip; ec_pwm->ec =3D ec; =20 + ec_pwm->use_pwm_type =3D of_property_read_bool( + dev->of_node, "google,use_pwm_type"); + /* PWM chip */ chip->dev =3D dev; chip->ops =3D &cros_ec_pwm_ops; chip->of_xlate =3D cros_ec_pwm_xlate; chip->of_pwm_n_cells =3D 1; - ret =3D cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm =3D CROS_EC_PWM_DT_COUNT; + } else { + ret =3D cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm =3D ret; } - chip->npwm =3D ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); =20 ret =3D pwmchip_add(chip); --=20 2.35.1.894.gb6a874cedc-goog From nobody Mon Jun 22 15:46:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92382C433F5 for ; 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Mon, 21 Mar 2022 07:32:36 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 3/4] dt-bindings: update google,cros-ec-pwm documentation Date: Mon, 21 Mar 2022 14:32:21 +0000 Message-Id: <20220321143222.2523373-4-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update google,cros-ec-pwm node documentation to mention the google,use_pwm_type property. Signed-off-by: Fabio Baltieri --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml = b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 4cfbffd8414a..2224e8e07029 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -19,6 +19,12 @@ description: | properties: compatible: const: google,cros-ec-pwm + + google,use_pwm_type: + description: + Use PWM types (CROS_EC_PWM_DT_<...>) instead of generic channels. + type: boolean + "#pwm-cells": description: The cell specifies the PWM index. const: 1 --=20 2.35.1.894.gb6a874cedc-goog From nobody Mon Jun 22 15:46:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BABDC433EF for ; Mon, 21 Mar 2022 14:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349373AbiCUOfL (ORCPT ); Mon, 21 Mar 2022 10:35:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350130AbiCUOeH (ORCPT ); Mon, 21 Mar 2022 10:34:07 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A89EA5DE45 for ; Mon, 21 Mar 2022 07:32:39 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id t11so20983306wrm.5 for ; Mon, 21 Mar 2022 07:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RccDfbuFs/Yz2WrfhL+KkjoyAgUu2DNhvPj6SzPznLY=; b=MTu7SXp2mMCpLDiDwJeKrjiCt7ymx7U0UG1x1U6bTcaLMpAK5p8CBpfjbxlZvnr36d maBuFhYOfQZReSuaI9sCQW4R/chbZxL9lDaimRIeZ2mhkIgo0yiaaGr3nf1tGZJy7yQW 7CdcJCwmF/gQa/Miq1bugA74rDusfk870DyVw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RccDfbuFs/Yz2WrfhL+KkjoyAgUu2DNhvPj6SzPznLY=; b=lTUTVmZTyHScq6Ag6poV/TH0JeUbB/I9ureGcpCRfApBWFrf6czY2CA3P8cfMLmHFl ymCSFKWRPPquWz2TPvJVMDtob4Lue1Q77BNTXYx9rEF6CAPFXRP1N8pmOYXYxatge0C1 8fKh+9U32tyneJLJJca7I1uedw6MuIMx1p401U3cLmjnW82z2LBBUUoTVDQRU4tkKm6I WIBJLuDCGAgLAzkmmhRZxVZ1cw3LQViTv7jo/+UvJgOl+2DOAeP14EmwkDUaMuacACpm pbunGgLAdiLhIrb1u1gTQo9UiWIefddzhQmiAT/F1zUsaMe1D3+Y9IDabdLkXOPgpL0S x4YQ== X-Gm-Message-State: AOAM531rCV3tWBdz6evp4D9j0xtpck0gkWhbYZyK9MGk0rhg2X0haUQk l1ZkJjiZPJH5OXlXr/DrVNtKBZUBOawzGA== X-Google-Smtp-Source: ABdhPJwOqVlJwIVTX5II/TL9iAxFRONy6Vxcp8R+6SJpH47T6+n5NfKeVrNnW5xISpuY3ByAgkxtJg== X-Received: by 2002:a5d:4e89:0:b0:204:2ee:d87 with SMTP id e9-20020a5d4e89000000b0020402ee0d87mr8406009wru.9.1647873158156; Mon, 21 Mar 2022 07:32:38 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id u11-20020a05600c19cb00b00389efe9c512sm19092793wmq.23.2022.03.21.07.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 07:32:37 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Mon, 21 Mar 2022 14:32:22 +0000 Message-Id: <20220321143222.2523373-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.894.gb6a874cedc-goog In-Reply-To: <20220321143222.2523373-1-fabiobaltieri@chromium.org> References: <20220321143222.2523373-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 3 ++- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 +++++--- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 6 ++++-- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 4 +++- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.= dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible =3D "pwm-leds"; keyboard_backlight: keyboard-backlight { label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; }; =20 -&cros_ec_pwm { +&cros_ec_pwm_type { status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/= arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..eaea09d0f8cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,10 +92,11 @@ volume_up { }; =20 &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; status =3D "disabled"; + google,use_pwm_type; }; }; =20 diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 14ed09f30a73..bcdfabe1860d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status =3D "okay"; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &camcc { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index bd5909ffb3dc..3deddbf97cb3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include =20 @@ -222,7 +223,7 @@ backlight: backlight { num-interpolated-steps =3D <64>; default-brightness-level =3D <951>; =20 - pwms =3D <&cros_ec_pwm 1>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -260,7 +261,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -543,9 +544,10 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; + google,use_pwm_type; }; =20 i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index 4619fa9fcacd..8676c8a677b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include =20 @@ -379,7 +380,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -771,9 +772,10 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; + google,use_pwm_type; }; =20 i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index 0896a6151817..48bb2159e126 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,9 +20,10 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; + google,use_pwm_type; }; =20 i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index 4a6285a25f77..e6dc4bc57f01 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include "sdm845.dtsi" =20 @@ -27,7 +28,7 @@ chosen { =20 backlight: backlight { compatible =3D "pwm-backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -708,9 +709,10 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; + google,use_pwm_type; }; =20 i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/b= oot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature =3D <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch= /arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..324bb8871fe2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply =3D <&pp3300_disp>; pinctrl-names =3D "default"; pinctrl-0 =3D <&bl_en>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us =3D <10000>; }; =20 @@ -462,9 +463,10 @@ ap_i2c_tp: &i2c5 { }; =20 &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible =3D "google,cros-ec-pwm"; #pwm-cells =3D <1>; + google,use_pwm_type; }; =20 usbc_extcon1: extcon1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64= /boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names =3D "default"; pinctrl-0 =3D <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi" =20 --=20 2.35.1.894.gb6a874cedc-goog