From nobody Mon Jun 22 18:10:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB927C433FE for ; Fri, 18 Mar 2022 22:44:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241353AbiCRWpV (ORCPT ); Fri, 18 Mar 2022 18:45:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241342AbiCRWpP (ORCPT ); Fri, 18 Mar 2022 18:45:15 -0400 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FEDB19B07E; Fri, 18 Mar 2022 15:43:53 -0700 (PDT) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22IK15Lm027630; Fri, 18 Mar 2022 22:43:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=v6iZXwA2Am8swC6551Es3v1s4q+s9epkgRTwcKxjD5I=; b=ZKmXMzKAjSa1mG8zimYXg3cPnPYnqgGlgznfrG9o3jVlxuqzXFPIa7+nfXsRiU5toM7k LsCXeSzmaGGhAHBeblEAeUdF+dhtP3yMsT9nqJ9OhYdzmeZZSGORSQ5P0YwbCdFcPnEQ mZaNiVWrt284+hlO+nzNfVBc1231vXrP9T7tW8gANBuOLikY4K7W7367Noz//fyR5EGa KZwi89lEq8VnciKLkarFaq9rp5z5r7n78P91i8G0yocg6j4aZRVZV7aEuuB4tT9dUiY9 gUlPL3C0dJt5dUxvZnACEriUs7my+2T/DWIeLJcOYhAUx/ZDevw6gYajJx77pP0Lqdf0 dg== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3evu2wc1hq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 22:43:13 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id D8C1858; Fri, 18 Mar 2022 22:43:12 +0000 (UTC) Received: from dog.eag.rdlabs.hpecorp.net (dog.eag.rdlabs.hpecorp.net [128.162.243.181]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id F00C74A; Fri, 18 Mar 2022 22:43:11 +0000 (UTC) From: Mike Travis To: Borislav Petkov , Ingo Molnar , Thomas Gleixner , Steve Wahl , x86@kernel.org Cc: Mike Travis , Dimitri Sivanich , Andy Shevchenko , Darren Hart , "H. Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH v3 1/3] x86/platform/uv: Update NMI Handler for UV5 Date: Fri, 18 Mar 2022 17:43:02 -0500 Message-Id: <20220318224304.174967-2-mike.travis@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220318224304.174967-1-mike.travis@hpe.com> References: <20220318224304.174967-1-mike.travis@hpe.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: wEbrajT8OG6Uao5moFn5UQOCwWD0lOv3 X-Proofpoint-GUID: wEbrajT8OG6Uao5moFn5UQOCwWD0lOv3 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_14,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180122 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update NMI handler to interface with UV5 hardware. This involves changing the EVENT_OCCURRED MMR used by the hardware and removes the check for which NMI function is supported by UV BIOS. The newer NMI function is assumed supported on UV5 and above. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Reviewed-by: Steve Wahl --- v3: Fix mistake in UVH_EXTIO_INT0_BROADCAST check. Use true/false in setting bool flag. v2: Use bool flag to assume NMI support for UV5 and above. --- arch/x86/platform/uv/uv_nmi.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c index 1e9ff28bc2e0..6d2e9ae8576b 100644 --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -244,8 +244,10 @@ static inline bool uv_nmi_action_is(const char *action) /* Setup which NMI support is present in system */ static void uv_nmi_setup_mmrs(void) { + bool nmi_supported =3D false; + /* First determine arch specific MMRs to handshake with BIOS */ - if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) { + if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) { /* UV2,3,4 setup */ uvh_nmi_mmrx =3D UVH_EVENT_OCCURRED0; uvh_nmi_mmrx_clear =3D UVH_EVENT_OCCURRED0_ALIAS; uvh_nmi_mmrx_shift =3D UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT; @@ -255,26 +257,25 @@ static void uv_nmi_setup_mmrs(void) uvh_nmi_mmrx_req =3D UVH_BIOS_KERNEL_MMR_ALIAS_2; uvh_nmi_mmrx_req_shift =3D 62; =20 - } else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) { + } else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) { /* UV5+ setup */ uvh_nmi_mmrx =3D UVH_EVENT_OCCURRED1; uvh_nmi_mmrx_clear =3D UVH_EVENT_OCCURRED1_ALIAS; uvh_nmi_mmrx_shift =3D UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT; uvh_nmi_mmrx_type =3D "OCRD1-EXTIO_INT0"; =20 - uvh_nmi_mmrx_supported =3D UVH_EXTIO_INT0_BROADCAST; - uvh_nmi_mmrx_req =3D UVH_BIOS_KERNEL_MMR_ALIAS_2; - uvh_nmi_mmrx_req_shift =3D 62; + nmi_supported =3D true; /* assume sync valid on UV5+ */ + uvh_nmi_mmrx_req =3D 0; /* no request bit to clear */ =20 } else { - pr_err("UV:%s:cannot find EVENT_OCCURRED*_EXTIO_INT0\n", - __func__); + pr_err("UV:%s:NMI support not available on this system\n", __func__); return; } =20 /* Then find out if new NMI is supported */ - if (likely(uv_read_local_mmr(uvh_nmi_mmrx_supported))) { - uv_write_local_mmr(uvh_nmi_mmrx_req, - 1UL << uvh_nmi_mmrx_req_shift); + if (likely(nmi_supported) || (uv_read_local_mmr(uvh_nmi_mmrx_supported)))= { + if (uvh_nmi_mmrx_req) + uv_write_local_mmr(uvh_nmi_mmrx_req, + 1UL << uvh_nmi_mmrx_req_shift); nmi_mmr =3D uvh_nmi_mmrx; nmi_mmr_clear =3D uvh_nmi_mmrx_clear; nmi_mmr_pending =3D 1UL << uvh_nmi_mmrx_shift; --=20 2.26.2 From nobody Mon Jun 22 18:10:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AE69C433EF for ; Fri, 18 Mar 2022 22:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241390AbiCRWpa (ORCPT ); Fri, 18 Mar 2022 18:45:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241343AbiCRWpP (ORCPT ); Fri, 18 Mar 2022 18:45:15 -0400 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80A7819B087; Fri, 18 Mar 2022 15:43:53 -0700 (PDT) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22IMbsiP020011; Fri, 18 Mar 2022 22:43:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=BqkAywTgWdlW1+XBiXg5Rfy8g9DvAfqYPHFJLBdTzOk=; b=ja2jcvQw1ZuQnneZx5pTsQ7ncsg2jrUi8WGCyRij34aRr4/nw/QSmFQli4ATQfjfdcjm xlZmolnOnQiTORyC9vRo7yhile1VX07gsUvqAWNzN0pIa+9LaSEsX2QNmtcBHAcWMzhH lbZ9TegffocGLCiz5QJhV0maQYZnp0kVIYERpfR+jTu262FQfeWvSy36XN+LSZYSjVUO 9j1Kkl6ccFQ2y4UgbqlK3+5Y+UbKw4ls/87OGrd1BWO8MN8nerQn28OePeXDj53ymAVV H0XckecD1aNdO28Ff9VU17Gy4GzMhfxZdDzIpCdkU1mOsL15CIM0t5RrNSHVMMdVg5KT 2A== Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3evu2wc1hs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 22:43:14 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id D6B904E; Fri, 18 Mar 2022 22:43:13 +0000 (UTC) Received: from dog.eag.rdlabs.hpecorp.net (dog.eag.rdlabs.hpecorp.net [128.162.243.181]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id ED66149; Fri, 18 Mar 2022 22:43:12 +0000 (UTC) From: Mike Travis To: Borislav Petkov , Ingo Molnar , Thomas Gleixner , Steve Wahl , x86@kernel.org Cc: Mike Travis , Dimitri Sivanich , Andy Shevchenko , Darren Hart , "H. Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH v3 2/3] x86/platform/uv: Update TSC sync state for UV5 Date: Fri, 18 Mar 2022 17:43:03 -0500 Message-Id: <20220318224304.174967-3-mike.travis@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220318224304.174967-1-mike.travis@hpe.com> References: <20220318224304.174967-1-mike.travis@hpe.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: HHwULhifDUkZaLVnbF7EARGsKPn2ztiA X-Proofpoint-GUID: HHwULhifDUkZaLVnbF7EARGsKPn2ztiA X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_14,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180122 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update TSC to not check TSC sync state for uv5+ as it is not available. It is assumed that TSC will always be in sync for multiple chassis and will pass the tests for the kernel to accept it as the clocksource. To disable this check use the kernel start options tsc=3Dreliable clocksource=3Dtsc. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Reviewed-by: Steve Wahl --- v2: Update patch description to be more explanatory. --- arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2ap= ic_uv_x.c index f5a48e66e4f5..387d6533549a 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; =20 - /* Different returns from different UV BIOS versions */ + /* UV5+, sync state from bios not available, assumed valid */ + if (!is_uv(UV2|UV3|UV4)) { + pr_debug("UV: TSC sync state for UV5+ assumed valid\n"); + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr =3D uv_early_read_mmr(UVH_TSC_SYNC_MMR); - mmr_shift =3D - is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; + mmr_shift =3D is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; sync_state =3D (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; =20 /* Check if TSC is valid for all sockets */ --=20 2.26.2 From nobody Mon Jun 22 18:10:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3931C433FE for ; Fri, 18 Mar 2022 22:43:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241349AbiCRWpR (ORCPT ); Fri, 18 Mar 2022 18:45:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239855AbiCRWpN (ORCPT ); Fri, 18 Mar 2022 18:45:13 -0400 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 334E719ABFC; Fri, 18 Mar 2022 15:43:53 -0700 (PDT) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22IK8nqX006179; Fri, 18 Mar 2022 22:43:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=EqEV7oOPRCwvP9zFRtxS2amJ0sojOOK340QCkQmT5GQ=; b=aNZYkWYWwcR7VJkVNzzSycraQGqJP0sUYxaB36QIqtnImttRLPr2TMB41QSamHjAfvU6 TKm64ThsVAnmf/xlAIPuyk4empBDcVpen8ZfoiC0pHAHNtaaikwyUcdtR07kDZNyGfPz E/uRsji8UL3XlQ6kkn4fUW02VRsyepmcJDd+KgEj5yjJ8CXRvSZ+O+17QP+vxiE9aOZj muwPq1l/9S0XEe+6v109X+rTrfwAtb31ry4DCj7e7LQmBpXX2yV4zAFBOqrsoCRha5QL FZl69jQic5Lljum2ne84F9cfaPC6+hss0xj30vLGF0OiXZ/vIVTx8pEo0gYoDkxYiQaQ SQ== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3ew0uv8taq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 22:43:15 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 0847B9A; Fri, 18 Mar 2022 22:43:14 +0000 (UTC) Received: from dog.eag.rdlabs.hpecorp.net (dog.eag.rdlabs.hpecorp.net [128.162.243.181]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id EC52446; Fri, 18 Mar 2022 22:43:13 +0000 (UTC) From: Mike Travis To: Borislav Petkov , Ingo Molnar , Thomas Gleixner , Steve Wahl , x86@kernel.org Cc: Mike Travis , Andy Shevchenko , Darren Hart , Dimitri Sivanich , "H. Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH v3 3/3] x86/platform/uv: Log gap hole end size Date: Fri, 18 Mar 2022 17:43:04 -0500 Message-Id: <20220318224304.174967-4-mike.travis@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220318224304.174967-1-mike.travis@hpe.com> References: <20220318224304.174967-1-mike.travis@hpe.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: XthJuZlICJRUDg7xca5Bd0RWlQ30Wwnd X-Proofpoint-GUID: XthJuZlICJRUDg7xca5Bd0RWlQ30Wwnd X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_14,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 suspectscore=0 mlxlogscore=901 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 impostorscore=0 mlxscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180122 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Show value of gap end in the kernel log which equates to number of physical address bits used by system. The end address of the gap holds PA bits 56:26 which gives the range up to 64PB max size with 64MB of granularity. Signed-off-by: Mike Travis Reviewed-by: Steve Wahl --- v2: Update patch description to be more explanatory. --- arch/x86/kernel/apic/x2apic_uv_x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2ap= ic_uv_x.c index 387d6533549a..146f0f63a43b 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -1346,7 +1346,7 @@ static void __init decode_gam_params(unsigned long pt= r) static void __init decode_gam_rng_tbl(unsigned long ptr) { struct uv_gam_range_entry *gre =3D (struct uv_gam_range_entry *)ptr; - unsigned long lgre =3D 0; + unsigned long lgre =3D 0, gend =3D 0; int index =3D 0; int sock_min =3D 999999, pnode_min =3D 99999; int sock_max =3D -1, pnode_max =3D -1; @@ -1380,6 +1380,9 @@ static void __init decode_gam_rng_tbl(unsigned long p= tr) flag, size, suffix[order], gre->type, gre->nasid, gre->sockid, gre->pnode); =20 + if (gre->type =3D=3D UV_GAM_RANGE_TYPE_HOLE) + gend =3D (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; + /* update to next range start */ lgre =3D gre->limit; if (sock_min > gre->sockid) @@ -1397,7 +1400,8 @@ static void __init decode_gam_rng_tbl(unsigned long p= tr) _max_pnode =3D pnode_max; _gr_table_len =3D index; =20 - pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x= )\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); + pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%= x), gap_end(%d)\n", + index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); } =20 /* Walk through UVsystab decoding the fields */ --=20 2.26.2