From nobody Mon Jun 22 21:20:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83BB3C433FE for ; Thu, 17 Mar 2022 00:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354768AbiCQA7h (ORCPT ); Wed, 16 Mar 2022 20:59:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345483AbiCQA7e (ORCPT ); Wed, 16 Mar 2022 20:59:34 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D987F13CCD for ; Wed, 16 Mar 2022 17:58:18 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id l8so5569691pfu.1 for ; Wed, 16 Mar 2022 17:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iVaSiMrGUBcuxr+BXheMhCpTwOTEdY3UKmynqOZB7GE=; b=laiMa1UGEj7YbxyVRZ7aUO9i2EcvkGLOGcVqw5do55ZZ0ighV06QEkme6Dd7iBf3nF qSL3a1C7XNtfO27iCLFd13f3TDzDZJC9+J7gM6ug1YOavfLB/h5sFsrmO/JLPkOXn7vM FkrYbi7f5hydijrpe6WfdHplPq9VFdm15W61Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iVaSiMrGUBcuxr+BXheMhCpTwOTEdY3UKmynqOZB7GE=; b=Pmj3ggZ8lypqTLQQrg3tBS9DQg7bCrBP6v740p9PhA00v1olLvgtuhos/l2XuukaRm eW8YyJvHvnnevZMSUkBuSDMUguVYe4RlLzNmGZ6ekJ9UmjnRyvtyHe+XNMtOVVsybPwN tVkAVBZSt7AAhtDfU9944bmKYWpqBHvqm219ptZkI/p/vowynZaO/5GCc6+EPcFcBWuJ yF1Tu4rBv4Fl7KMNhPaoF1qP+m9XSCizXL7poOQcDsJUwGcZ+RyYzFQmUDJB70OOv9B7 shvRPCaM96qYT1uJAA1Yv7ueYkl5NUZCrtEPxnXmWqq6Zqu488l/LWdjOhQVwj+hob7E JiRA== X-Gm-Message-State: AOAM533u++quR+R/fNWhaDAwOh9eg5xkXJhagTtoC8loJyg4XBmWxQCm G/SrWF0SVeI/nsAGYfasNLPyzQ== X-Google-Smtp-Source: ABdhPJw5GSVzk93O9AbsNKLeH45njGoSIqITsaIK4AQ+v4ZD3t8POB/0cPylVtYlqcqNRymomj4wGw== X-Received: by 2002:a05:6a00:1146:b0:4c9:ede0:725a with SMTP id b6-20020a056a00114600b004c9ede0725amr2144828pfm.35.1647478698387; Wed, 16 Mar 2022 17:58:18 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:dec5:e3f8:cbd7:f5a7]) by smtp.gmail.com with ESMTPSA id l20-20020a056a00141400b004f65cedfb09sm4433445pfu.48.2022.03.16.17.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 17:58:18 -0700 (PDT) From: Stephen Boyd To: Benson Leung Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Rob Herring , devicetree@vger.kernel.org, Guenter Roeck , Douglas Anderson , Craig Hesling , Tom Hughes , Alexandru M Stan , Tzung-Bi Shih Subject: [PATCH v2 1/3] dt-bindings: chrome: Add ChromeOS fingerprint binding Date: Wed, 16 Mar 2022 17:58:12 -0700 Message-Id: <20220317005814.2496302-2-swboyd@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220317005814.2496302-1-swboyd@chromium.org> References: <20220317005814.2496302-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a binding to describe the fingerprint processor found on Chromebooks with a fingerprint sensor. Cc: Rob Herring Cc: Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Signed-off-by: Stephen Boyd --- .../bindings/chrome/google,cros-ec-fp.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/chrome/google,cros-ec= -fp.yaml diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yam= l b/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml new file mode 100644 index 000000000000..ba4212e6b583 --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-fp.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,cros-ec-fp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChromeOS Embedded Fingerprint Controller + +description: + Google's ChromeOS embedded fingerprint controller is a device which + implements fingerprint functionality such as unlocking a Chromebook + without typing a password. + +maintainers: + - Tom Hughes + +properties: + compatible: + const: google,cros-ec-fp + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 3000000 + + interrupts: + maxItems: 1 + + reset-gpios: true + boot0-gpios: + maxItems: 1 + description: Assert for bootloader mode. + + vdd-supply: true + + google,cros-ec-spi-pre-delay: + description: + This property specifies the delay in usecs between the + assertion of the CS and the first clock pulse. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - default: 0 + - minimum: 0 + + google,cros-ec-spi-msg-delay: + description: + This property specifies the delay in usecs between messages. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - default: 0 + - minimum: 0 + +required: + - compatible + - reg + - interrupts + - reset-gpios + - boot0-gpios + - vdd-supply + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include + #include + spi { + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + ec@0 { + compatible =3D "google,cros-ec-fp"; + reg =3D <0>; + interrupt-parent =3D <&gpio_controller>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <3000000>; + google,cros-ec-spi-msg-delay =3D <37>; + google,cros-ec-spi-pre-delay =3D <5>; + reset-gpios =3D <&gpio_controller 5 GPIO_ACTIVE_LOW>; + boot0-gpios =3D <&gpio_controller 10 GPIO_ACTIVE_HIGH>; + vdd-supply =3D <&pp3300_fp_mcu>; + }; + }; +... --=20 https://chromeos.dev From nobody Mon Jun 22 21:20:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D0F6C433EF for ; Thu, 17 Mar 2022 00:58:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354729AbiCQA7m (ORCPT ); Wed, 16 Mar 2022 20:59:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240010AbiCQA7f (ORCPT ); Wed, 16 Mar 2022 20:59:35 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D856513E81 for ; Wed, 16 Mar 2022 17:58:19 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id o23so1447201pgk.13 for ; Wed, 16 Mar 2022 17:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ozEwxbhS5CJ9GBcAAvnujKd841/J1GSZd5stO5HqEjg=; b=lo0d5tF/rK43t4wYULaadPTcwiYjzT503duKa/wadkni0wAlDUtkjc3hBPNwZ651jb pylYMJmLs0li6nZfG46yutukJ5dpRILnAC/cCyy9fDEBTGaCwRuI7uV2QeM2xKP61NlS Ls3/+5hGfssJMzw2v0cYQE7gzcQ3KR50+CbbI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ozEwxbhS5CJ9GBcAAvnujKd841/J1GSZd5stO5HqEjg=; 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charset="utf-8" Add the fingerprint cros-ec compatible and spi_device_id so that we can pro= be fingerprint devices. Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke --- drivers/platform/chrome/cros_ec_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrom= e/cros_ec_spi.c index 14c4046fa04d..d0f9496076d6 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -813,12 +813,14 @@ static SIMPLE_DEV_PM_OPS(cros_ec_spi_pm_ops, cros_ec_= spi_suspend, cros_ec_spi_resume); =20 static const struct of_device_id cros_ec_spi_of_match[] =3D { + { .compatible =3D "google,cros-ec-fp", }, { .compatible =3D "google,cros-ec-spi", }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, cros_ec_spi_of_match); =20 static const struct spi_device_id cros_ec_spi_id[] =3D { + { "cros-ec-fp", 0 }, { "cros-ec-spi", 0 }, { } }; --=20 https://chromeos.dev From nobody Mon Jun 22 21:20:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8F99C433EF for ; Thu, 17 Mar 2022 00:58:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355958AbiCQA7s (ORCPT ); Wed, 16 Mar 2022 20:59:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354372AbiCQA7g (ORCPT ); Wed, 16 Mar 2022 20:59:36 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 997E513E31 for ; Wed, 16 Mar 2022 17:58:21 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id c11so1447370pgu.11 for ; Wed, 16 Mar 2022 17:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z1n9UVVKMRQXDGbxIDzUh2jfKVbWO78ULBsARLp7tcY=; b=jfxExfhHKLLo+nlGGwg/kE8Wp98nbRHDe7mpV6j9ryWVuWNtR5aVsotE7/Y+oBCKrU TSlfbZSGBsJgcuxaFYUd76kKS3SAAYiW9XaHU0b2oEdS57zl/AFIJUdv5NJ9tP/q47MG UN6RbggXW88VoY+3jOyluiBheLsz+/pqAt4CU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z1n9UVVKMRQXDGbxIDzUh2jfKVbWO78ULBsARLp7tcY=; b=JFla2k6mIG+xhasMUpycsIR35RFtvDdB59020VCaYo05CeLlLTWGON8dgfmX30HQgz Bip0sazFYaPhaNhUcdEqfOHrYg6n8pCDsACBZpBAOr6ImZQAmItNsbskIwpGhOmwNUt0 pLWtxwY5SK74/R6nxDGCTODrWnsMvY9X2uoPqcsRMBshvm9l2sW1QvjLGWLIrL6Z6GBU xALiiCuP7CLUkio8CF1eXZNJfzwLcDPdAYWkywBqZfKoPJzuVLN/NzMOCTM+CyhlMqiH F45AkWrqe4zX+LMPrCWyvXvZYQi5nhMBs95UvaDkb5Y6CZDVXacenWsKiJ+2Rk9Ua3Uk NoyQ== X-Gm-Message-State: AOAM530kvzfWeO+3mnfoLJ+bHWDtxDoq8Hqx07jRjy2DBaagDtQQht8g K+Jfk+DSvthBmLrcJEs6TcdKsw== X-Google-Smtp-Source: ABdhPJwS+9f+tcwKXhz47Sw1tD3D6y77gcriRiKA8DMzgNiPiuYcnTfpw9IDP0DyDkMLvXrtVFWTng== X-Received: by 2002:a05:6a00:2131:b0:4f7:b6da:9ed0 with SMTP id n17-20020a056a00213100b004f7b6da9ed0mr2254839pfj.69.1647478700537; Wed, 16 Mar 2022 17:58:20 -0700 (PDT) Received: from smtp.gmail.com ([2620:15c:202:201:dec5:e3f8:cbd7:f5a7]) by smtp.gmail.com with ESMTPSA id l20-20020a056a00141400b004f65cedfb09sm4433445pfu.48.2022.03.16.17.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 17:58:20 -0700 (PDT) From: Stephen Boyd To: Benson Leung Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, Guenter Roeck , Douglas Anderson , Craig Hesling , Tom Hughes , Alexandru M Stan , Tzung-Bi Shih Subject: [PATCH v2 3/3] platform/chrome: cros_ec_spi: Boot fingerprint processor during probe Date: Wed, 16 Mar 2022 17:58:14 -0700 Message-Id: <20220317005814.2496302-4-swboyd@chromium.org> X-Mailer: git-send-email 2.35.1.723.g4982287a31-goog In-Reply-To: <20220317005814.2496302-1-swboyd@chromium.org> References: <20220317005814.2496302-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add gpio control to this driver so that the fingerprint device can be booted if the BIOS isn't doing it already. This eases bringup of new hardware as we don't have to wait for the BIOS to be ready, supports kexec where the GPIOs may not be configured by the previous boot stage, and is all around good hygiene because we control GPIOs for this device from the device driver. Cc: Guenter Roeck Cc: Douglas Anderson Cc: Craig Hesling Cc: Tom Hughes Cc: Alexandru M Stan Cc: Tzung-Bi Shih Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke --- drivers/platform/chrome/cros_ec_spi.c | 42 +++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrom= e/cros_ec_spi.c index d0f9496076d6..13d413a2fe46 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -4,6 +4,7 @@ // Copyright (C) 2012 Google, Inc =20 #include +#include #include #include #include @@ -77,6 +78,8 @@ struct cros_ec_spi { unsigned int start_of_msg_delay; unsigned int end_of_msg_delay; struct kthread_worker *high_pri_worker; + struct gpio_desc *boot0; + struct gpio_desc *reset; }; =20 typedef int (*cros_ec_xfer_fn_t) (struct cros_ec_device *ec_dev, @@ -690,7 +693,7 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device *= ec_dev, return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_cmd_xfer_spi); } =20 -static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device= *dev) +static int cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device = *dev) { struct device_node *np =3D dev->of_node; u32 val; @@ -703,6 +706,37 @@ static void cros_ec_spi_dt_probe(struct cros_ec_spi *e= c_spi, struct device *dev) ret =3D of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val); if (!ret) ec_spi->end_of_msg_delay =3D val; + + if (!of_device_is_compatible(np, "google,cros-ec-fp")) + return 0; + + ec_spi->boot0 =3D devm_gpiod_get(dev, "boot0", 0); + if (IS_ERR(ec_spi->boot0)) + return PTR_ERR(ec_spi->boot0); + + ec_spi->reset =3D devm_gpiod_get(dev, "reset", 0); + if (IS_ERR(ec_spi->reset)) + return PTR_ERR(ec_spi->reset); + + /* + * Take the FPMCU out of reset and wait for it to boot if it's in + * bootloader mode or held in reset. This isn't the normal flow because + * typically the BIOS has already powered on the device to avoid the + * multi-second delay waiting for the FPMCU to boot and be responsive. + */ + if (gpiod_get_value(ec_spi->boot0) || gpiod_get_value(ec_spi->reset)) { + /* Boot0 is sampled on reset deassertion */ + gpiod_set_value(ec_spi->boot0, 0); + gpiod_set_value(ec_spi->reset, 1); + usleep_range(1000, 2000); + gpiod_set_value(ec_spi->reset, 0); + + /* Wait for boot; there isn't a "boot done" signal */ + dev_info(dev, "Waiting for FPMCU to boot\n"); + msleep(2000); + } + + return 0; } =20 static void cros_ec_spi_high_pri_release(void *worker) @@ -754,8 +788,10 @@ static int cros_ec_spi_probe(struct spi_device *spi) if (!ec_dev) return -ENOMEM; =20 - /* Check for any DT properties */ - cros_ec_spi_dt_probe(ec_spi, dev); + /* Check for any DT properties and boot FPMCU if applicable */ + err =3D cros_ec_spi_dt_probe(ec_spi, dev); + if (err) + return err; =20 spi_set_drvdata(spi, ec_dev); ec_dev->dev =3D dev; --=20 https://chromeos.dev