From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B85A9C4167B for ; Tue, 15 Mar 2022 03:24:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344602AbiCODZg (ORCPT ); Mon, 14 Mar 2022 23:25:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344085AbiCODZc (ORCPT ); Mon, 14 Mar 2022 23:25:32 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A114235862; Mon, 14 Mar 2022 20:24:20 -0700 (PDT) X-UUID: 0983651cd3a0403c98de546432227d00-20220315 X-UUID: 0983651cd3a0403c98de546432227d00-20220315 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 505020276; Tue, 15 Mar 2022 11:24:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:14 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu , AngeloGioacchino Del Regno Subject: [PATCH V4 1/6] spi: mediatek: support tick_delay without enhance_timing Date: Tue, 15 Mar 2022 11:24:06 +0800 Message-ID: <20220315032411.2826-2-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch support tick_delay bit[31:30] without enhance_timing feature. Fixes: f84d866ab43f("spi: mediatek: add tick_delay support") Signed-off-by: Leilk Liu Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mt65xx.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index bbfeb8046c17..3fd89548ec3c 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -43,8 +43,11 @@ #define SPI_CFG1_PACKET_LOOP_OFFSET 8 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 +#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 =20 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 +#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 + #define SPI_CFG1_CS_IDLE_MASK 0xff #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 @@ -346,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *= master, =20 /* tick delay */ reg_val =3D readl(mdata->base + SPI_CFG1_REG); - reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; - reg_val |=3D ((chip_config->tick_delay & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); + if (mdata->dev_comp->enhance_timing) { + reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; + reg_val |=3D ((chip_config->tick_delay & 0x7) + << SPI_CFG1_GET_TICK_DLY_OFFSET); + } else { + reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK_V1; + reg_val |=3D ((chip_config->tick_delay & 0x3) + << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); + } writel(reg_val, mdata->base + SPI_CFG1_REG); =20 /* set hw cs timing */ --=20 2.25.1 From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05590C433EF for ; Tue, 15 Mar 2022 03:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344643AbiCODZq (ORCPT ); Mon, 14 Mar 2022 23:25:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344596AbiCODZe (ORCPT ); Mon, 14 Mar 2022 23:25:34 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E03135853; Mon, 14 Mar 2022 20:24:23 -0700 (PDT) X-UUID: 42911417488d43609c6d6ffc17c5fbbe-20220315 X-UUID: 42911417488d43609c6d6ffc17c5fbbe-20220315 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1403163055; Tue, 15 Mar 2022 11:24:17 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:15 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V4 2/6] dt-bindings: spi: Add compatible for MT7986 Date: Tue, 15 Mar 2022 11:24:07 +0800 Message-ID: <20220315032411.2826-3-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds dt-binding documentation for MT7986. Signed-off-by: Leilk Liu Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml= b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index bfa44acb1bdd..7247a177466b 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -30,6 +30,10 @@ properties: - mediatek,mt8192-spi - mediatek,mt8195-spi - const: mediatek,mt6765-spi + - items: + - enum: + - mediatek,mt7986-spi-ipm + - const: mediatek,spi-ipm - items: - enum: - mediatek,mt2701-spi --=20 2.25.1 From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F25AFC43217 for ; Tue, 15 Mar 2022 03:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344633AbiCODZm (ORCPT ); Mon, 14 Mar 2022 23:25:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344594AbiCODZe (ORCPT ); Mon, 14 Mar 2022 23:25:34 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1A2D35DF6; Mon, 14 Mar 2022 20:24:22 -0700 (PDT) X-UUID: 49d5784024f747319a9d086b58d1c6e8-20220315 X-UUID: 49d5784024f747319a9d086b58d1c6e8-20220315 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1108740857; Tue, 15 Mar 2022 11:24:17 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:16 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:16 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V4 3/6] spi: mediatek: add ipm design support for MT7986 Date: Tue, 15 Mar 2022 11:24:08 +0800 Message-ID: <20220315032411.2826-4-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch add the support of ipm design. Signed-off-by: Leilk Liu Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mt65xx.c | 102 +++++++++++++++++++++++++++++++++------ 1 file changed, 87 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 3fd89548ec3c..1a0b3208dfca 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -31,6 +31,7 @@ #define SPI_CFG2_REG 0x0028 #define SPI_TX_SRC_REG_64 0x002c #define SPI_RX_DST_REG_64 0x0030 +#define SPI_CFG3_IPM_REG 0x0040 =20 #define SPI_CFG0_SCK_HIGH_OFFSET 0 #define SPI_CFG0_SCK_LOW_OFFSET 8 @@ -51,6 +52,7 @@ #define SPI_CFG1_CS_IDLE_MASK 0xff #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 +#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) #define SPI_CFG2_SCK_HIGH_OFFSET 0 #define SPI_CFG2_SCK_LOW_OFFSET 16 =20 @@ -71,7 +73,13 @@ #define SPI_CMD_TX_ENDIAN BIT(15) #define SPI_CMD_FINISH_IE BIT(16) #define SPI_CMD_PAUSE_IE BIT(17) +#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) +#define SPI_CMD_IPM_SPIM_LOOP BIT(21) +#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 =20 +#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) +#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) +#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) #define MT8173_SPI_MAX_PAD_SEL 3 =20 #define MTK_SPI_PAUSE_INT_STATUS 0x2 @@ -81,6 +89,7 @@ =20 #define MTK_SPI_MAX_FIFO_SIZE 32U #define MTK_SPI_PACKET_SIZE 1024 +#define MTK_SPI_IPM_PACKET_SIZE SZ_64K #define MTK_SPI_32BITS_MASK (0xffffffff) =20 #define DMA_ADDR_EXT_BITS (36) @@ -96,6 +105,9 @@ struct mtk_spi_compatible { bool dma_ext; /* some IC no need unprepare SPI clk */ bool no_need_unprepare; + /* IPM design adjust and extend register to support more features */ + bool ipm_design; + }; =20 struct mtk_spi { @@ -119,6 +131,12 @@ static const struct mtk_spi_compatible mt2712_compat = =3D { .must_tx =3D true, }; =20 +static const struct mtk_spi_compatible mtk_ipm_compat =3D { + .enhance_timing =3D true, + .dma_ext =3D true, + .ipm_design =3D true, +}; + static const struct mtk_spi_compatible mt6765_compat =3D { .need_pad_sel =3D true, .must_tx =3D true, @@ -160,6 +178,9 @@ static const struct mtk_chip_config mtk_default_chip_in= fo =3D { }; =20 static const struct of_device_id mtk_spi_of_match[] =3D { + { .compatible =3D "mediatek,spi-ipm", + .data =3D (void *)&mtk_ipm_compat, + }, { .compatible =3D "mediatek,mt2701-spi", .data =3D (void *)&mtk_common_compat, }, @@ -278,12 +299,11 @@ static int mtk_spi_set_hw_cs_timing(struct spi_device= *spi) return 0; } =20 -static int mtk_spi_prepare_message(struct spi_master *master, - struct spi_message *msg) +static int mtk_spi_hw_init(struct spi_master *master, + struct spi_device *spi) { u16 cpha, cpol; u32 reg_val; - struct spi_device *spi =3D msg->spi; struct mtk_chip_config *chip_config =3D spi->controller_data; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 @@ -291,6 +311,15 @@ static int mtk_spi_prepare_message(struct spi_master *= master, cpol =3D spi->mode & SPI_CPOL ? 1 : 0; =20 reg_val =3D readl(mdata->base + SPI_CMD_REG); + if (mdata->dev_comp->ipm_design) { + /* SPI transfer without idle time until packet length done */ + reg_val |=3D SPI_CMD_IPM_NONIDLE_MODE; + if (spi->mode & SPI_LOOP) + reg_val |=3D SPI_CMD_IPM_SPIM_LOOP; + else + reg_val &=3D ~SPI_CMD_IPM_SPIM_LOOP; + } + if (cpha) reg_val |=3D SPI_CMD_CPHA; else @@ -348,23 +377,39 @@ static int mtk_spi_prepare_message(struct spi_master = *master, mdata->base + SPI_PAD_SEL_REG); =20 /* tick delay */ - reg_val =3D readl(mdata->base + SPI_CFG1_REG); if (mdata->dev_comp->enhance_timing) { - reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; - reg_val |=3D ((chip_config->tick_delay & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); + if (mdata->dev_comp->ipm_design) { + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val &=3D ~SPI_CMD_IPM_GET_TICKDLY_MASK; + reg_val |=3D ((chip_config->tick_delay & 0x7) + << SPI_CMD_IPM_GET_TICKDLY_OFFSET); + writel(reg_val, mdata->base + SPI_CMD_REG); + } else { + reg_val =3D readl(mdata->base + SPI_CFG1_REG); + reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK; + reg_val |=3D ((chip_config->tick_delay & 0x7) + << SPI_CFG1_GET_TICK_DLY_OFFSET); + writel(reg_val, mdata->base + SPI_CFG1_REG); + } } else { + reg_val =3D readl(mdata->base + SPI_CFG1_REG); reg_val &=3D ~SPI_CFG1_GET_TICK_DLY_MASK_V1; reg_val |=3D ((chip_config->tick_delay & 0x3) << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); + writel(reg_val, mdata->base + SPI_CFG1_REG); } - writel(reg_val, mdata->base + SPI_CFG1_REG); =20 /* set hw cs timing */ mtk_spi_set_hw_cs_timing(spi); return 0; } =20 +static int mtk_spi_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + return mtk_spi_hw_init(master, msg->spi); +} + static void mtk_spi_set_cs(struct spi_device *spi, bool enable) { u32 reg_val; @@ -386,13 +431,13 @@ static void mtk_spi_set_cs(struct spi_device *spi, bo= ol enable) } =20 static void mtk_spi_prepare_transfer(struct spi_master *master, - struct spi_transfer *xfer) + u32 speed_hz) { u32 div, sck_time, reg_val; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 - if (xfer->speed_hz < mdata->spi_clk_hz / 2) - div =3D DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz); + if (speed_hz < mdata->spi_clk_hz / 2) + div =3D DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); else div =3D 1; =20 @@ -423,12 +468,24 @@ static void mtk_spi_setup_packet(struct spi_master *m= aster) u32 packet_size, packet_loop, reg_val; struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 - packet_size =3D min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); + if (mdata->dev_comp->ipm_design) + packet_size =3D min_t(u32, + mdata->xfer_len, + MTK_SPI_IPM_PACKET_SIZE); + else + packet_size =3D min_t(u32, + mdata->xfer_len, + MTK_SPI_PACKET_SIZE); + packet_loop =3D mdata->xfer_len / packet_size; =20 reg_val =3D readl(mdata->base + SPI_CFG1_REG); - reg_val &=3D ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); + if (mdata->dev_comp->ipm_design) + reg_val &=3D ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; + else + reg_val &=3D ~SPI_CFG1_PACKET_LENGTH_MASK; reg_val |=3D (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; + reg_val &=3D ~SPI_CFG1_PACKET_LOOP_MASK; reg_val |=3D (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; writel(reg_val, mdata->base + SPI_CFG1_REG); } @@ -523,7 +580,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *mas= ter, mdata->cur_transfer =3D xfer; mdata->xfer_len =3D min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); mdata->num_xfered =3D 0; - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer->speed_hz); mtk_spi_setup_packet(master); =20 if (xfer->tx_buf) { @@ -556,7 +613,7 @@ static int mtk_spi_dma_transfer(struct spi_master *mast= er, mdata->cur_transfer =3D xfer; mdata->num_xfered =3D 0; =20 - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer->speed_hz); =20 cmd =3D readl(mdata->base + SPI_CMD_REG); if (xfer->tx_buf) @@ -591,6 +648,19 @@ static int mtk_spi_transfer_one(struct spi_master *mas= ter, struct spi_device *spi, struct spi_transfer *xfer) { + struct mtk_spi *mdata =3D spi_master_get_devdata(spi->master); + u32 reg_val =3D 0; + + /* prepare xfer direction and duplex mode */ + if (mdata->dev_comp->ipm_design) { + if (!xfer->tx_buf || !xfer->rx_buf) { + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_EN; + if (xfer->rx_buf) + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_DIR; + } + writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); + } + if (master->can_dma(master, spi, xfer)) return mtk_spi_dma_transfer(master, spi, xfer); else @@ -757,6 +827,8 @@ static int mtk_spi_probe(struct platform_device *pdev) =20 if (mdata->dev_comp->must_tx) master->flags =3D SPI_MASTER_MUST_TX; + if (mdata->dev_comp->ipm_design) + master->mode_bits |=3D SPI_LOOP; =20 if (mdata->dev_comp->need_pad_sel) { mdata->pad_num =3D of_property_count_u32_elems( --=20 2.25.1 From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54B93C433F5 for ; Tue, 15 Mar 2022 03:24:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344655AbiCODZ7 (ORCPT ); Mon, 14 Mar 2022 23:25:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344618AbiCODZk (ORCPT ); Mon, 14 Mar 2022 23:25:40 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB6D43587F; Mon, 14 Mar 2022 20:24:27 -0700 (PDT) X-UUID: ccad68b4b2d044b89efa990e6418a922-20220315 X-UUID: ccad68b4b2d044b89efa990e6418a922-20220315 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 604504766; Tue, 15 Mar 2022 11:24:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:17 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:16 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V4 4/6] spi: mediatek: add spi memory support for ipm design Date: Tue, 15 Mar 2022 11:24:09 +0800 Message-ID: <20220315032411.2826-5-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch add the support of spi-mem for ipm design. Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 349 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 348 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 1a0b3208dfca..8958c3fa4fea 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #define SPI_CFG0_REG 0x0000 @@ -78,8 +79,21 @@ #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 =20 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) + +#define PIN_MODE_CFG(x) ((x) / 2) + +#define SPI_CFG3_IPM_PIN_MODE_OFFSET 0 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) +#define SPI_CFG3_IPM_XMODE_EN BIT(4) +#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) +#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 +#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 + +#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) +#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) +#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) + #define MT8173_SPI_MAX_PAD_SEL 3 =20 #define MTK_SPI_PAUSE_INT_STATUS 0x2 @@ -90,6 +104,8 @@ #define MTK_SPI_MAX_FIFO_SIZE 32U #define MTK_SPI_PACKET_SIZE 1024 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K +#define MTK_SPI_IPM_PACKET_LOOP SZ_256 + #define MTK_SPI_32BITS_MASK (0xffffffff) =20 #define DMA_ADDR_EXT_BITS (36) @@ -107,7 +123,6 @@ struct mtk_spi_compatible { bool no_need_unprepare; /* IPM design adjust and extend register to support more features */ bool ipm_design; - }; =20 struct mtk_spi { @@ -123,6 +138,11 @@ struct mtk_spi { u32 tx_sgl_len, rx_sgl_len; const struct mtk_spi_compatible *dev_comp; u32 spi_clk_hz; + struct completion spimem_done; + bool use_spimem; + struct device *dev; + dma_addr_t tx_dma; + dma_addr_t rx_dma; }; =20 static const struct mtk_spi_compatible mtk_common_compat; @@ -704,6 +724,12 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *de= v_id) else mdata->state =3D MTK_SPI_IDLE; =20 + /* SPI-MEM ops */ + if (mdata->use_spimem) { + complete(&mdata->spimem_done); + return IRQ_HANDLED; + } + if (!master->can_dma(master, NULL, trans)) { if (trans->rx_buf) { cnt =3D mdata->xfer_len / 4; @@ -787,6 +813,320 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *d= ev_id) return IRQ_HANDLED; } =20 +static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) +{ + int opcode_len; + + if (op->data.dir !=3D SPI_MEM_NO_DATA) { + opcode_len =3D 1 + op->addr.nbytes + op->dummy.nbytes; + if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + op->data.nbytes =3D MTK_SPI_IPM_PACKET_SIZE - opcode_len; + /* force data buffer dma-aligned. */ + op->data.nbytes -=3D op->data.nbytes % 4; + } + } + + return 0; +} + +static bool mtk_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (op->data.buswidth > 4 || op->addr.buswidth > 4 || + op->dummy.buswidth > 4 || op->cmd.buswidth > 4) + return false; + + if (op->addr.nbytes && op->dummy.nbytes && + op->addr.buswidth !=3D op->dummy.buswidth) + return false; + + if (op->addr.nbytes + op->dummy.nbytes > 16) + return false; + + if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > + MTK_SPI_IPM_PACKET_LOOP || + op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE !=3D 0) + return false; + } + + return true; +} + +static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(master); + + writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_TX_SRC_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->tx_dma >> 32), + mdata->base + SPI_TX_SRC_REG_64); +#endif + + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_RX_DST_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->rx_dma >> 32), + mdata->base + SPI_RX_DST_REG_64); +#endif + } +} + +static int mtk_spi_transfer_wait(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(mem->spi->master); + /* + * For each byte we wait for 8 cycles of the SPI clock. + * Since speed is defined in Hz and we want milliseconds, + * so it should be 8 * 1000. + */ + u64 ms =3D 8000LL; + + if (op->data.dir =3D=3D SPI_MEM_NO_DATA) + ms *=3D 32; /* prevent we may get 0 for short transfers. */ + else + ms *=3D op->data.nbytes; + ms =3D div_u64(ms, mem->spi->max_speed_hz); + ms +=3D ms + 1000; /* 1s tolerance */ + + if (ms > UINT_MAX) + ms =3D UINT_MAX; + + if (!wait_for_completion_timeout(&mdata->spimem_done, + msecs_to_jiffies(ms))) { + dev_err(mdata->dev, "spi-mem transfer timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mtk_spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(mem->spi->master); + u32 reg_val, nio, tx_size; + char *tx_tmp_buf, *rx_tmp_buf; + int ret =3D 0; + + mdata->use_spimem =3D true; + reinit_completion(&mdata->spimem_done); + + mtk_spi_reset(mdata); + mtk_spi_hw_init(mem->spi->master, mem->spi); + mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); + + reg_val =3D readl(mdata->base + SPI_CFG3_IPM_REG); + /* opcode byte len */ + reg_val &=3D ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; + reg_val |=3D 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; + + /* addr & dummy byte len */ + reg_val &=3D ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; + if (op->addr.nbytes || op->dummy.nbytes) + reg_val |=3D (op->addr.nbytes + op->dummy.nbytes) << + SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; + + /* data byte len */ + if (op->data.dir =3D=3D SPI_MEM_NO_DATA) { + reg_val |=3D SPI_CFG3_IPM_NODATA_FLAG; + writel(0, mdata->base + SPI_CFG1_REG); + } else { + reg_val &=3D ~SPI_CFG3_IPM_NODATA_FLAG; + mdata->xfer_len =3D op->data.nbytes; + mtk_spi_setup_packet(mem->spi->master); + } + + if (op->addr.nbytes || op->dummy.nbytes) { + if (op->addr.buswidth =3D=3D 1 || op->dummy.buswidth =3D=3D 1) + reg_val |=3D SPI_CFG3_IPM_XMODE_EN; + else + reg_val &=3D ~SPI_CFG3_IPM_XMODE_EN; + } + + if (op->addr.buswidth =3D=3D 2 || + op->dummy.buswidth =3D=3D 2 || + op->data.buswidth =3D=3D 2) + nio =3D 2; + else if (op->addr.buswidth =3D=3D 4 || + op->dummy.buswidth =3D=3D 4 || + op->data.buswidth =3D=3D 4) + nio =3D 4; + else + nio =3D 1; + + reg_val &=3D ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; + reg_val |=3D PIN_MODE_CFG(nio) << SPI_CFG3_IPM_PIN_MODE_OFFSET; + + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_EN; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val |=3D SPI_CFG3_IPM_HALF_DUPLEX_DIR; + else + reg_val &=3D ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; + writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); + + tx_size =3D 1 + op->addr.nbytes + op->dummy.nbytes; + if (op->data.dir =3D=3D SPI_MEM_DATA_OUT) + tx_size +=3D op->data.nbytes; + + tx_size =3D max_t(u32, tx_size, 32); + + tx_tmp_buf =3D kzalloc(tx_size, GFP_KERNEL | GFP_DMA); + if (!tx_tmp_buf) { + mdata->use_spimem =3D false; + return -ENOMEM; + } + + tx_tmp_buf[0] =3D op->cmd.opcode; + + if (op->addr.nbytes) { + int i; + + for (i =3D 0; i < op->addr.nbytes; i++) + tx_tmp_buf[i + 1] =3D op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + } + + if (op->dummy.nbytes) + memset(tx_tmp_buf + op->addr.nbytes + 1, + 0xff, + op->dummy.nbytes); + + if (op->data.nbytes && op->data.dir =3D=3D SPI_MEM_DATA_OUT) + memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, + op->data.buf.out, + op->data.nbytes); + + mdata->tx_dma =3D dma_map_single(mdata->dev, tx_tmp_buf, + tx_size, DMA_TO_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { + ret =3D -ENOMEM; + goto err_exit; + } + + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { + rx_tmp_buf =3D kzalloc(op->data.nbytes, + GFP_KERNEL | GFP_DMA); + if (!rx_tmp_buf) { + ret =3D -ENOMEM; + goto unmap_tx_dma; + } + } else { + rx_tmp_buf =3D op->data.buf.in; + } + + mdata->rx_dma =3D dma_map_single(mdata->dev, + rx_tmp_buf, + op->data.nbytes, + DMA_FROM_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { + ret =3D -ENOMEM; + goto kfree_rx_tmp_buf; + } + } + + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val |=3D SPI_CMD_TX_DMA; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val |=3D SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + + mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); + + mtk_spi_enable_transfer(mem->spi->master); + + /* Wait for the interrupt. */ + ret =3D mtk_spi_transfer_wait(mem, op); + if (ret) + goto unmap_rx_dma; + + /* spi disable dma */ + reg_val =3D readl(mdata->base + SPI_CMD_REG); + reg_val &=3D ~SPI_CMD_TX_DMA; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + reg_val &=3D ~SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + +unmap_rx_dma: + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + dma_unmap_single(mdata->dev, mdata->rx_dma, + op->data.nbytes, DMA_FROM_DEVICE); + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) + memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); + } +kfree_rx_tmp_buf: + if (op->data.dir =3D=3D SPI_MEM_DATA_IN && + !IS_ALIGNED((size_t)op->data.buf.in, 4)) + kfree(rx_tmp_buf); +unmap_tx_dma: + dma_unmap_single(mdata->dev, mdata->tx_dma, + tx_size, DMA_TO_DEVICE); +err_exit: + kfree(tx_tmp_buf); + mdata->use_spimem =3D false; + + return ret; +} + +static const struct spi_controller_mem_ops mtk_spi_mem_ops =3D { + .adjust_op_size =3D mtk_spi_mem_adjust_op_size, + .supports_op =3D mtk_spi_mem_supports_op, + .exec_op =3D mtk_spi_mem_exec_op, +}; + +static void of_mtk_spi_parse_dt(struct spi_master *master, struct device_n= ode *nc) +{ + struct mtk_spi *mdata =3D spi_master_get_devdata(master); + u32 value; + + if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { + switch (value) { + case 1: + break; + case 2: + master->mode_bits |=3D SPI_TX_DUAL; + break; + case 4: + master->mode_bits |=3D SPI_TX_QUAD; + break; + default: + dev_warn(mdata->dev, + "spi-tx-bus-width %d not supported\n", + value); + break; + } + } + + if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { + switch (value) { + case 1: + break; + case 2: + master->mode_bits |=3D SPI_RX_DUAL; + break; + case 4: + master->mode_bits |=3D SPI_RX_QUAD; + break; + case 8: + master->mode_bits |=3D SPI_RX_OCTAL; + break; + default: + dev_warn(mdata->dev, + "spi-rx-bus-width %d not supported\n", + value); + break; + } + } +} + static int mtk_spi_probe(struct platform_device *pdev) { struct spi_master *master; @@ -830,6 +1170,13 @@ static int mtk_spi_probe(struct platform_device *pdev) if (mdata->dev_comp->ipm_design) master->mode_bits |=3D SPI_LOOP; =20 + if (mdata->dev_comp->ipm_design) { + mdata->dev =3D &pdev->dev; + master->mem_ops =3D &mtk_spi_mem_ops; + of_mtk_spi_parse_dt(master, pdev->dev.of_node); + init_completion(&mdata->spimem_done); + } + if (mdata->dev_comp->need_pad_sel) { mdata->pad_num =3D of_property_count_u32_elems( pdev->dev.of_node, --=20 2.25.1 From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 488B6C433F5 for ; Tue, 15 Mar 2022 03:24:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344627AbiCODZz (ORCPT ); Mon, 14 Mar 2022 23:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344608AbiCODZi (ORCPT ); Mon, 14 Mar 2022 23:25:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB44235DC7; Mon, 14 Mar 2022 20:24:26 -0700 (PDT) X-UUID: 8e8f667d3c7e413c8fc0d3ed25ef95be-20220315 X-UUID: 8e8f667d3c7e413c8fc0d3ed25ef95be-20220315 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 741578688; Tue, 15 Mar 2022 11:24:19 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:18 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:17 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V4 5/6] dt-bindings: spi: support hclk Date: Tue, 15 Mar 2022 11:24:10 +0800 Message-ID: <20220315032411.2826-6-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch support hclk for AHB bus. Signed-off-by: Leilk Liu --- .../devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml= b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index 7247a177466b..ecb4a5002cc1 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -53,16 +53,20 @@ properties: maxItems: 1 =20 clocks: + minItems: 3 items: - description: clock used for the parent clock - description: clock used for the muxes clock - description: clock used for the clock gate + - description: clock used for the AHB bus, this clock is optional =20 clock-names: + minItems: 3 items: - const: parent-clk - const: sel-clk - const: spi-clk + - const: hclk =20 mediatek,pad-select: $ref: /schemas/types.yaml#/definitions/uint32-array --=20 2.25.1 From nobody Sun Sep 22 07:33:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65330C433EF for ; Tue, 15 Mar 2022 03:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344658AbiCODZt (ORCPT ); Mon, 14 Mar 2022 23:25:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344603AbiCODZg (ORCPT ); Mon, 14 Mar 2022 23:25:36 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BAC235853; Mon, 14 Mar 2022 20:24:25 -0700 (PDT) X-UUID: 4029fad27efa4cad91d526e453de6fe5-20220315 X-UUID: 4029fad27efa4cad91d526e453de6fe5-20220315 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1372009443; Tue, 15 Mar 2022 11:24:20 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 15 Mar 2022 11:24:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 11:24:19 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Mar 2022 11:24:18 +0800 From: Leilk Liu To: Mark Brown CC: Rob Herring , Matthias Brugger , , , , , , Leilk Liu Subject: [PATCH V4 6/6] spi: mediatek: support hclk Date: Tue, 15 Mar 2022 11:24:11 +0800 Message-ID: <20220315032411.2826-7-leilk.liu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220315032411.2826-1-leilk.liu@mediatek.com> References: <20220315032411.2826-1-leilk.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" this patch adds hclk support. Signed-off-by: Leilk Liu --- drivers/spi/spi-mt65xx.c | 85 ++++++++++++++++++++++++++++++++-------- 1 file changed, 69 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 8958c3fa4fea..d4a602e78aa7 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -130,7 +130,7 @@ struct mtk_spi { u32 state; int pad_num; u32 *pad_sel; - struct clk *parent_clk, *sel_clk, *spi_clk; + struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; struct spi_transfer *cur_transfer; u32 xfer_len; u32 num_xfered; @@ -1252,25 +1252,38 @@ static int mtk_spi_probe(struct platform_device *pd= ev) goto err_put_master; } =20 + mdata->spi_hclk =3D devm_clk_get(&pdev->dev, "hclk"); + if (!IS_ERR(mdata->spi_hclk)) { + ret =3D clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret); + goto err_put_master; + } + } + ret =3D clk_prepare_enable(mdata->spi_clk); if (ret < 0) { dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); - goto err_put_master; + goto err_disable_spi_hclk; } =20 ret =3D clk_set_parent(mdata->sel_clk, mdata->parent_clk); if (ret < 0) { dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); - clk_disable_unprepare(mdata->spi_clk); - goto err_put_master; + goto err_disable_spi_clk; } =20 mdata->spi_clk_hz =3D clk_get_rate(mdata->spi_clk); =20 - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_disable(mdata->spi_clk); - else + if (!IS_ERR(mdata->spi_hclk)) + clk_disable(mdata->spi_hclk); + } else { clk_disable_unprepare(mdata->spi_clk); + if (!IS_ERR(mdata->spi_hclk)) + clk_disable_unprepare(mdata->spi_hclk); + } =20 pm_runtime_enable(&pdev->dev); =20 @@ -1310,6 +1323,11 @@ static int mtk_spi_probe(struct platform_device *pde= v) =20 err_disable_runtime_pm: pm_runtime_disable(&pdev->dev); +err_disable_spi_clk: + clk_disable_unprepare(mdata->spi_clk); +err_disable_spi_hclk: + if (!IS_ERR(mdata->spi_hclk)) + clk_disable_unprepare(mdata->spi_hclk); err_put_master: spi_master_put(master); =20 @@ -1325,8 +1343,11 @@ static int mtk_spi_remove(struct platform_device *pd= ev) =20 mtk_spi_reset(mdata); =20 - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_unprepare(mdata->spi_clk); + if (!IS_ERR(mdata->spi_hclk)) + clk_unprepare(mdata->spi_hclk); + } =20 return 0; } @@ -1342,8 +1363,11 @@ static int mtk_spi_suspend(struct device *dev) if (ret) return ret; =20 - if (!pm_runtime_suspended(dev)) + if (!pm_runtime_suspended(dev)) { clk_disable_unprepare(mdata->spi_clk); + if (!IS_ERR(mdata->spi_hclk)) + clk_disable_unprepare(mdata->spi_hclk); + } =20 return ret; } @@ -1360,11 +1384,23 @@ static int mtk_spi_resume(struct device *dev) dev_err(dev, "failed to enable spi_clk (%d)\n", ret); return ret; } + + if (!IS_ERR(mdata->spi_hclk)) { + clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); + clk_disable_unprepare(mdata->spi_clk); + return ret; + } + } } =20 ret =3D spi_master_resume(master); - if (ret < 0) + if (ret < 0) { clk_disable_unprepare(mdata->spi_clk); + if (!IS_ERR(mdata->spi_hclk)) + clk_disable_unprepare(mdata->spi_hclk); + } =20 return ret; } @@ -1376,10 +1412,15 @@ static int mtk_spi_runtime_suspend(struct device *d= ev) struct spi_master *master =3D dev_get_drvdata(dev); struct mtk_spi *mdata =3D spi_master_get_devdata(master); =20 - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_disable(mdata->spi_clk); - else + if (!IS_ERR(mdata->spi_hclk)) + clk_disable(mdata->spi_hclk); + } else { clk_disable_unprepare(mdata->spi_clk); + if (!IS_ERR(mdata->spi_hclk)) + clk_disable_unprepare(mdata->spi_hclk); + } =20 return 0; } @@ -1390,13 +1431,25 @@ static int mtk_spi_runtime_resume(struct device *de= v) struct mtk_spi *mdata =3D spi_master_get_devdata(master); int ret; =20 - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { ret =3D clk_enable(mdata->spi_clk); - else + if (!IS_ERR(mdata->spi_hclk)) + clk_enable(mdata->spi_hclk); + } else { ret =3D clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { - dev_err(dev, "failed to enable spi_clk (%d)\n", ret); - return ret; + if (ret < 0) { + dev_err(dev, "failed to enable spi_clk (%d)\n", ret); + return ret; + } + + if (!IS_ERR(mdata->spi_hclk)) { + ret =3D clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); + clk_disable_unprepare(mdata->spi_clk); + return ret; + } + } } =20 return 0; --=20 2.25.1