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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:00 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Anup Patel , Heiko Stuebner , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 1/6] RISC-V: Correctly print supported extensions Date: Mon, 14 Mar 2022 13:38:40 -0700 Message-Id: <20220314203845.832648-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel Tested-by: Heiko Stuebner Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include =20 +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); --=20 2.30.2 From nobody Tue Jun 23 00:45:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F820C433FE for ; Mon, 14 Mar 2022 20:39:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245098AbiCNUkV (ORCPT ); Mon, 14 Mar 2022 16:40:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245070AbiCNUkP (ORCPT ); Mon, 14 Mar 2022 16:40:15 -0400 Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38AAB39BB0 for ; Mon, 14 Mar 2022 13:39:05 -0700 (PDT) Received: by mail-qv1-xf2a.google.com with SMTP id kl20so13474272qvb.10 for ; Mon, 14 Mar 2022 13:39:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=OaQVvtun4w2HGIP+NbUQehl+w1J2Tio2m55d4PUY1yEeMnN6smYhUOucavK9Lb9jcS PUpyUt82BEQRMi6ySCQkdOVHZb75cvBnPso9NGN9fQ3YoaGNcmbXqldzbaEzJHbpuY2z ka0zMpMCr4RMho5FRue3gRVZIu6yx/Ash8Q5Ds6KL/mKeeGzi1x7zs0IY9dgOHglRYDg 2x6dSDnK/i6KZ1KjpFXhRPUA3LnQQQqp0pL68/WvLXe0sXvPosfdui0YLyTHTeXVogB0 wSpo2eRqLgE7j2fiFS4Q11apKs+B4bl7QDTD9LmRAwBcrd2B4ab9YSWRlmv4/MxU70XE bjMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=jpXXmXTjh8CGSIwIwgeHOMMii7aeTv3gZURHa9Toa6U4kYF3xeI0gY2VRKHxSWXXYV dGrXi4kqUhOH18Q7slDsV8K1TL44AM483IZJN4FjW80YuLW+vRxEk8K377xNNfPMQgWh 2rsIBnYpyG0yMBbfY7kszWedEp0MinFE0/FKRLNb+Iu/Des+Ksw2y/T9GGDFtRRnYlBa 0MspuMGLlMKdgHs7TATv24gRK1LmSSbHWsYxkpctzGc35X5NGeInXllg+Wda1Z0CEfvL 838mzw0nKi2FHObiLcQsIm4Chi6C5e1VLfqah8zW1XOUBf9/mCvIBVVyiBs4OVM1hCqc Ss6A== X-Gm-Message-State: AOAM530j+CVUZuOvsQAwL9QxKnXyROR0guMzt5aJF1JgAepzJ30xAVYf M9d2XMJd3wb+t/mzscanLXW+V6BJtgFSVg== X-Google-Smtp-Source: ABdhPJzIp/quN1QwTOXk9P7tPFbqPaO4qUcmh7aJNwAZ1GnkCu+lixNP0VfbXyz5NNIm67Pv3SCLnw== X-Received: by 2002:ad4:576c:0:b0:435:493d:98e9 with SMTP id r12-20020ad4576c000000b00435493d98e9mr19114325qvx.128.1647290344066; Mon, 14 Mar 2022 13:39:04 -0700 (PDT) Received: from rivos-atish.ba.rivosinc.com (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:03 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Mon, 14 Mar 2022 13:38:41 -0700 Message-Id: <20220314203845.832648-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI Tested-by: Heiko Stuebner Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..72c5f6ef56b5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void) continue; } =20 - i =3D 0; - isa_len =3D strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i +=3D 4; + isa +=3D 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i +=3D 4; + isa +=3D 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext =3D isa++; + const char *ext_end =3D isa; + bool ext_long =3D false, ext_err =3D false; + + switch (*ext) { + case 's': + /** + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] !=3D '_' && ext[1] =3D=3D 'u') { + ++isa; + ext_err =3D true; + break; + } + fallthrough; + case 'x': + case 'z': + ext_long =3D true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa !=3D '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err =3D true; + break; + default: + if (unlikely(!islower(*ext))) { + ext_err =3D true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + /* Skip the minor version */ + while (isdigit(*++isa)) + ; + if (*isa !=3D 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + /* Skip the major version */ + while (isdigit(*++isa)) + ; + break; + } + if (*isa !=3D '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <=3D isa[i] && isa[i] < 'x') - this_isa |=3D (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); } =20 /* --=20 2.30.2 From nobody Tue Jun 23 00:45:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B59BC433F5 for ; Mon, 14 Mar 2022 20:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245129AbiCNUk3 (ORCPT ); Mon, 14 Mar 2022 16:40:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245077AbiCNUkU (ORCPT ); Mon, 14 Mar 2022 16:40:20 -0400 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65B1D3AA5F for ; Mon, 14 Mar 2022 13:39:09 -0700 (PDT) Received: by mail-qk1-x72a.google.com with SMTP id k125so8460172qkf.0 for ; Mon, 14 Mar 2022 13:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=RSQTwbMTlvf/XdTqYO8yvJZyz1/z+kSqX7ohzLBcVXa38yJV0hhUloVCQYRq6ujmIA 1cYw+Qz0pz0ig3z21KfyxAF4wuZdIjqUCD1nZNzev4zKBsAc844/u04qkmilCVeIda69 69+HG1rhQvW+SWGgf9KBGiy+9NU4OlGDr5ehIrJeatZ2TwB4eyZh7WTtKYZ3EM44qWjp oiztRuPBGGY2Oyh4IZmc2Q7p993UmfEGaUxuWkpEO4xcn/S+Op9RJnpbv4U1jwb/qrfB RbUquhN7Jq2jUlky5oVLorpXAlR1sbmgGdwKhlb/IHjmGYf5JFbdCo224DC5xz2sgncV HvMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=kRDZwb9U9cD2aRq/8EuFJdfAKMBqZfByAZZaN+Grn6B6BNKEo6NvB6gaxVn06frTlb 1T63Ex8ClVdsjCynnoVyIptpNWq0yqop2qwbcMCrmvE0bx6yHRVFVqEbcWbAyvZe4Ul9 phH7IsZjqEKf2lOfG4kVXoAlNouHbiIRi73uXmr0ImOfxqaAeBa1SLki779PCRf39ggI 325HdxQ2UlqVIUib5VX6ChDL65aJW6ZIROPZiwaeP9OrHL0GRQrwJtN8QzaEyoH9ieLS K8uiKcW/FWDnEuGgVPHjOq8ttyaRonWRDYz4xs5z6T0loPIjV67yLgXYDfx/wxp7J57l dCTg== X-Gm-Message-State: AOAM531vXgG977zkGUE2teyH1Y8bokH6iKQmTrKUXUYhlnbAsuDnOIRV Y+Qs8WJHUWQw5Wk/owqcGdJwZbVPZkFJeQ== X-Google-Smtp-Source: ABdhPJyo2wKJnYHR1OhUhhyhMQ4ds5vaGNsAWSD7I6VKTRF9r/58irDDodxIqoeGfB0DsyRbNRTMLQ== X-Received: by 2002:a05:620a:1a92:b0:67d:b2c2:8311 with SMTP id bl18-20020a05620a1a9200b0067db2c28311mr6926282qkb.594.1647290348212; Mon, 14 Mar 2022 13:39:08 -0700 (PDT) Received: from rivos-atish.ba.rivosinc.com (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:07 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Heiko Stuebner , Anup Patel , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Date: Mon, 14 Mar 2022 13:38:42 -0700 Message-Id: <20220314203845.832648-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: Heiko Stuebner Reviewed-by: Anup Patel Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 72c5f6ef56b5..b0df7eff47f7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -124,8 +124,28 @@ void __init riscv_fill_hwcap(void) ext_long =3D true; /* Multi-letter extension must be delimited */ for (; *isa && *isa !=3D '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err =3D true; + /* Parse backwards */ + ext_end =3D isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] !=3D 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: if (unlikely(!islower(*ext))) { @@ -151,14 +171,13 @@ void __init riscv_fill_hwcap(void) } if (*isa !=3D '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); + } } =20 /* --=20 2.30.2 From nobody Tue Jun 23 00:45:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 285DBC433EF for ; Mon, 14 Mar 2022 20:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245100AbiCNUkc (ORCPT ); Mon, 14 Mar 2022 16:40:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245117AbiCNUk1 (ORCPT ); Mon, 14 Mar 2022 16:40:27 -0400 Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 441183B036 for ; Mon, 14 Mar 2022 13:39:13 -0700 (PDT) Received: by mail-qt1-x833.google.com with SMTP id s11so5241868qtc.3 for ; Mon, 14 Mar 2022 13:39:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZKxcoiW2sFrGr3ldNCNu9wCCT4Ol89xMsxiQLGmBKoY=; b=NafqdwqBPqX1R63OZ/hAYGvoxQ/pek6BrUiwCv2wZ6cM99CFM236CS3evld1rZqbWQ fBrkYF/Gy/oOr10gKs/wxTkI0V5OetnpRZE2+wOJd6sA9PDuWCBVEeLlpoYTae9GPFBL s+ZhZJOUUMYcrMiKGQ07qSQXfsZP1SOi8YClR9x3F6lmwrmBfJm+Y0B617J590+xydoW ZcvshNTrD8o3XreqIaUYs5dq1k5QxpvSTGxinYU3Syxe2kRiOnTAcp5UzsRZ0yh7GWGw sKca4VdMAMawR2GSOi1zSJNge2UMCxdd953NrAbClfFO2GP0cYIlUYH1S57X8vukyQVv MK8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZKxcoiW2sFrGr3ldNCNu9wCCT4Ol89xMsxiQLGmBKoY=; b=jggbLbkV0cZ32jyTJ7/83MsRVaG5/DOpcWFC9kJXPZ6RQRR5V+ICLQMtdwhf8bfNhV N3FxNkAaplBM9PgmWd/YnMY9ShCEKdZp36Fxm0BnS8E9XNNVeuLk/t9SmHxxxKOyvYmo isdgIqWioCtDuL4ni3w6dQ8XqehiIn4VgjQ+WbXHFyMnlIBYz1q3Kj41TEYtieeEBzMq yvTP98PjqFtnX56x3D46QBWeMG642X+o5EbzR4p+CWCAul4d/xc130l0CEQdT8DM8hQV hTnTaMOY7rMnF6owS25CHmq3a7qyHwoxNcMLnpnh/vFz4lSvsSLnk7jWjZXulGsqWTC5 RVXA== X-Gm-Message-State: AOAM533Tj1dKTfowcp5AYKHvqRsl5k+HRjcQrzkm0eGBQ1hYe7O+6BpM cbAUhSXFxULEe/cS326OymoEs6nG3Ahyeg== X-Google-Smtp-Source: ABdhPJx87e8zvfeKGO0DgQLIPimSPq8sUch7uYeU6/3YirRmK8X3plKE2KVFWpNvipVAyavaY4RInw== X-Received: by 2002:a05:622a:107:b0:2e1:d655:cc4c with SMTP id u7-20020a05622a010700b002e1d655cc4cmr3852217qtw.669.1647290351876; Mon, 14 Mar 2022 13:39:11 -0700 (PDT) Received: from rivos-atish.ba.rivosinc.com (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:11 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Mon, 14 Mar 2022 13:38:43 -0700 Message-Id: <20220314203845.832648-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 22 ++++++++++++++++------ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') =20 +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +}; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b0df7eff47f7..3455fdfd680e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) =20 for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; - unsigned long this_isa =3D 0; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; @@ -172,12 +173,20 @@ void __init riscv_fill_hwcap(void) if (*isa !=3D '_') --isa; =20 +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) \ + set_bit(bit, this_isa); \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + set_bit(*ext - 'a', this_isa); } +#undef SET_ISA_EXT_MAP } =20 /* @@ -190,10 +199,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap =3D this_hwcap; =20 - if (riscv_isa[0]) - riscv_isa[0] &=3D this_isa; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else - riscv_isa[0] =3D this_isa; + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } =20 /* We don't support systems with F but without D, so mask those out @@ -207,7 +217,7 @@ void __init riscv_fill_hwcap(void) for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); + pr_info("riscv: base ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) --=20 2.30.2 From nobody Tue Jun 23 00:45:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC75C433FE for ; Mon, 14 Mar 2022 20:39:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236256AbiCNUkj (ORCPT ); Mon, 14 Mar 2022 16:40:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245116AbiCNUk2 (ORCPT ); Mon, 14 Mar 2022 16:40:28 -0400 Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 813E43E5F6 for ; Mon, 14 Mar 2022 13:39:16 -0700 (PDT) Received: by mail-qt1-x833.google.com with SMTP id 10so11756806qtz.11 for ; Mon, 14 Mar 2022 13:39:16 -0700 (PDT) DKIM-Signature: v=1; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:14 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Mon, 14 Mar 2022 13:38:44 -0700 Message-Id: <20220314203845.832648-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3455fdfd680e..a43c08af5f4b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + const char *temp; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } =20 + temp =3D isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa +=3D 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp =3D=3D isa) + continue; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; --=20 2.30.2 From nobody Tue Jun 23 00:45:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D8FFC433F5 for ; Mon, 14 Mar 2022 20:39:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245142AbiCNUkn (ORCPT ); Mon, 14 Mar 2022 16:40:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245110AbiCNUka (ORCPT ); Mon, 14 Mar 2022 16:40:30 -0400 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BE443AA79 for ; Mon, 14 Mar 2022 13:39:19 -0700 (PDT) Received: by mail-qk1-x72e.google.com with SMTP id v13so13361076qkv.3 for ; Mon, 14 Mar 2022 13:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NrEmpomOHclDV+kQuj0wjvwONyoQAm3AKPhEX1ax17s=; b=H5jqZD+ybOPj9jvOGT1khK8EOCXznxHjM7UW3eRCvg1JuQYYgw/3R+pQmi8EHWtWzc 4KI9pDN1Ghpgzgglw9kOBN+tyh9VPInf28WNsFo9MJkp6FZEh4EV90UWqAixUqe5AnMZ 1+v+ds82XgLi03xfOBbcZP9UOu/4sComMDe2Bg46lqGZvcETO8YitlTCtzcPbdFDhbQb J+q0GWqnlKQ8IlgA1niXGO2RItdxbWCu0XlAs0qWE1Eyg6hJSj61YiRQrW65+heH/PJp N6QGyveZbHaXwuxcQUa2jHIsF+4n5IsjQo/Rx8DlP92qM3JzpfdBFx/ecoLTWvDYPUH+ zAgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NrEmpomOHclDV+kQuj0wjvwONyoQAm3AKPhEX1ax17s=; b=D9Mm0khBdc6brnON8wT+Itl2JVg7xBu4fS033KHMEEq4Bmb3wAoiRZQ+LSqH6yLEEU WlMmaOJ+RBuXr8WoU6Kc9cpvH6uHOfDVrvs21MVARqu0OM4XASq2uuQnCOnJ59Bb8TkV kRh84sGRoQXuO8Jbq1oE6E33JSH+xM1njLxdDT66o9vhTCSqX0aPSV/gT7LeZ/l92GUo 19nipNyO4xVT9Qc8YuXTC/+PD82zhINptOSBitXhp+sSk46Ri7uOKAAP2QuGBBwuLoGb ngWvUrOk1cdETSsD1nYcz28GZm9OjX/rtexYpATZjAqTa3T4J/3nvoL8MnWCtTJm7Q+C NfWg== X-Gm-Message-State: AOAM530lx26qwMJGeFe6AVn2FvqPaQxHpe3qiglI/rGAiXW8EfuWTmG3 zQsWcGsdtf0eaAzMjDqXxIoTByqECo8Qlw== X-Google-Smtp-Source: ABdhPJwVXuvZmuG1IiPfArhVLDTUd60rYoPE5F9UgA8JVB+HYCUAnjh6XvDRJvRl58UiYBwc2HxQgw== X-Received: by 2002:a05:620a:28c4:b0:67d:c400:a9d7 with SMTP id l4-20020a05620a28c400b0067dc400a9d7mr5186069qkp.369.1647290357916; Mon, 14 Mar 2022 13:39:17 -0700 (PDT) Received: from rivos-atish.ba.rivosinc.com (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id j188-20020a3755c5000000b0067d1c76a09fsm8597023qkb.74.2022.03.14.13.39.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Mar 2022 13:39:17 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Mon, 14 Mar 2022 13:38:45 -0700 Message-Id: <20220314203845.832648-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com> References: <20220314203845.832648-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Same goes for the single letter extensions as well which prints the entire ISA string. Some of they may not be valid ISA extensions as well (e.g 'su') Parse only the valid & enabled ISA extension and print them. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 7 ++++ arch/riscv/kernel/cpu.c | 65 ++++++++++++++++++++++++++++++++-- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..fc115e307ef5 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -63,12 +64,72 @@ int riscv_of_parent_hartid(struct device_node *node) } =20 #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } +/** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter extensions + * from other multi-letter extensions by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered first + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after all + * standard extensions. They must be separated from other multi-letter + * extensions by an underscore. + */ +static struct riscv_isa_ext_data isa_ext_arr[] =3D { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i =3D 0, arr_sz; + + arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <=3D 0) + return; + + for (i =3D 0; i <=3D arr_sz; i++) { + edata =3D &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "_%s", edata->uprop); + } +} + +/** + * These are the only valid base (single letter) ISA extensions as per the= spec. + * It also specifies the canonical order in which it appears in the spec. + * Some of the extension may just be a place holder for now (B, K, P, J). + * This should be updated once corresponding extensions are ratified. + */ +static const char base_riscv_exts[13] =3D "imafdqcbkjpvh"; =20 static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + int i; + seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + /* Print the rv[64/32] part */ + seq_write(f, isa, 4); + for (i =3D 0; i < sizeof(base_riscv_exts); i++) { + if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) + /* Print only enabled the base ISA extensions */ + seq_write(f, &base_riscv_exts[i], 1); + } + print_isa_ext(f); seq_puts(f, "\n"); } =20 --=20 2.30.2