From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A63C433F5 for ; Sun, 13 Mar 2022 19:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235321AbiCMTGR (ORCPT ); Sun, 13 Mar 2022 15:06:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235063AbiCMTGN (ORCPT ); Sun, 13 Mar 2022 15:06:13 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C16D04B40B; Sun, 13 Mar 2022 12:05:03 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id m12so17003316edc.12; Sun, 13 Mar 2022 12:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FipcY+lkDnxvWbnpTUMABHmi8LHo7/IC+P6HwGjY488=; b=U2tU+HYy5lbcm/0aqa4m9mdzYpiIHgL7Pe3kFb2jPZobjl6e9Mx/+N2rJYnJFvo18k Z96PQcY0rfyd8qk4ng6xDwH0vPsaQBDUpigqBXkaUEeCCXth4mDG5z1lsVAIRyRSlSKq +OLGn5FH3JkfWk1mcbhv0FeVf8YUKkWLAi9ZqBDm5uxY0Gadr02jaaVO7xxN8JM5/ltC BzIwY+q7UWisCaRcyBr4yR8zNHw6PU5hG7uH2tpFEsaiyCPcXO3TWAEQKxjHYG/kehA3 zIcvZFTpkqMv2NNkvqpz25bSptgv5GhxOMaU7bUd6NIwst1W+SgmaS1XuyurtySOxgIe UfGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FipcY+lkDnxvWbnpTUMABHmi8LHo7/IC+P6HwGjY488=; b=iPrtCP9AMw5Zh/GtcyZJZM2JlguvOTXnLjTKrQAQQv0aPC+IysoimMHG5d8/0d1fUy +3ChqQAsM7lFgR0ApuLcHEida8pQMhAM5z49XFe1orRi9kudsnjCNFHHqaUjczPkE6gU vffGTqwrs9XWV8ohvDaWkUFIaFmwH3YjDLA8IpN6DszMlc4aomCdueWWWUAnQA6Df6Ap zAvq+DfKAFuyk3eBwQT104aRW40dBfT2GdiTG6PhB5fnJEGIzWGT7OMdqwi1942o6kT1 K0L0sjC7T9/JUYhHXBKUkiUlrjgEx6bO1xjQ41ErajNAOEEn+6asXrMEuz0T8wf2yJT1 IuCQ== X-Gm-Message-State: AOAM532YyglyxXXgPlZ32/y7cMM1CM5gKPxFppCDYMbBb7/GnWLuwIRh RSjmJhokktf7Ope1t84i4sI= X-Google-Smtp-Source: ABdhPJxYD9W6GHhYeKFQdJKjnbUP6tqfeGRYBy5Kuw4m0kblar/Mdnlkft6bgMegPd67bTBBYxowcQ== X-Received: by 2002:aa7:d313:0:b0:416:8fba:835f with SMTP id p19-20020aa7d313000000b004168fba835fmr17204808edq.354.1647198302090; Sun, 13 Mar 2022 12:05:02 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:01 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 01/16] clk: permit to define a custom parent for clk_hw_get_parent_index Date: Sun, 13 Mar 2022 20:04:04 +0100 Message-Id: <20220313190419.2207-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clk can have multiple parents. Some clk may require to get the cached index of other parent that are not current associated with the clk. Extend clk_hw_get_parent_index() with an optional parent to permit a driver to get the cached index. If parent is NULL, the parent associated with the provided hw clk is used. Signed-off-by: Ansuel Smith --- drivers/clk/clk.c | 14 +++++++++----- drivers/clk/tegra/clk-periph.c | 2 +- drivers/clk/tegra/clk-sdmmc-mux.c | 2 +- drivers/clk/tegra/clk-super.c | 4 ++-- include/linux/clk-provider.h | 2 +- 5 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..fe42f56bfbdf 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1711,15 +1711,19 @@ static int clk_fetch_parent_index(struct clk_core *= core, /** * clk_hw_get_parent_index - return the index of the parent clock * @hw: clk_hw associated with the clk being consumed + * @parent: optional clk_hw of the parent to be fetched * - * Fetches and returns the index of parent clock. Returns -EINVAL if the g= iven - * clock does not have a current parent. + * Fetches and returns the index of parent clock. If parent is not + * provided the parent of hw is used. + * Returns -EINVAL if the given clock does not have a current parent. */ -int clk_hw_get_parent_index(struct clk_hw *hw) +int clk_hw_get_parent_index(struct clk_hw *hw, struct clk_hw *parent) { - struct clk_hw *parent =3D clk_hw_get_parent(hw); + /* With parent NULL get the current parent of hw */ + if (!parent) + parent =3D clk_hw_get_parent(hw); =20 - if (WARN_ON(parent =3D=3D NULL)) + if (WARN_ON(!parent)) return -EINVAL; =20 return clk_fetch_parent_index(hw->core, parent->core); diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 79ca3aa072b7..0fecdbbaca8f 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -116,7 +116,7 @@ static void clk_periph_restore_context(struct clk_hw *h= w) struct clk_hw *div_hw =3D &periph->divider.hw; int parent_id; =20 - parent_id =3D clk_hw_get_parent_index(hw); + parent_id =3D clk_hw_get_parent_index(hw, NULL); if (WARN_ON(parent_id < 0)) return; =20 diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmm= c-mux.c index 4f2c3309eea4..6013ca8444f4 100644 --- a/drivers/clk/tegra/clk-sdmmc-mux.c +++ b/drivers/clk/tegra/clk-sdmmc-mux.c @@ -210,7 +210,7 @@ static void clk_sdmmc_mux_restore_context(struct clk_hw= *hw) unsigned long rate =3D clk_hw_get_rate(hw); int parent_id; =20 - parent_id =3D clk_hw_get_parent_index(hw); + parent_id =3D clk_hw_get_parent_index(hw, NULL); if (WARN_ON(parent_id < 0)) return; =20 diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c index a98a420398fa..27cbbc09ef68 100644 --- a/drivers/clk/tegra/clk-super.c +++ b/drivers/clk/tegra/clk-super.c @@ -128,7 +128,7 @@ static void clk_super_mux_restore_context(struct clk_hw= *hw) { int parent_id; =20 - parent_id =3D clk_hw_get_parent_index(hw); + parent_id =3D clk_hw_get_parent_index(hw, NULL); if (WARN_ON(parent_id < 0)) return; =20 @@ -180,7 +180,7 @@ static void clk_super_restore_context(struct clk_hw *hw) struct clk_hw *div_hw =3D &super->frac_div.hw; int parent_id; =20 - parent_id =3D clk_hw_get_parent_index(hw); + parent_id =3D clk_hw_get_parent_index(hw, NULL); if (WARN_ON(parent_id < 0)) return; =20 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..65b2850c09be 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1198,7 +1198,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_= hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); -int clk_hw_get_parent_index(struct clk_hw *hw); +int clk_hw_get_parent_index(struct clk_hw *hw, struct clk_hw *parent); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6931EC4167B for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:02 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 02/16] clk: qcom: gcc-ipq806x: skip pxo/cxo fixed clk if already present Date: Sun, 13 Mar 2022 20:04:05 +0100 Message-Id: <20220313190419.2207-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Skip pxo/cxo clock registration if they are already defined in DTS as fixed clock. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..27f6d7626abb 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -3061,15 +3062,22 @@ static int gcc_ipq806x_probe(struct platform_device= *pdev) { struct device *dev =3D &pdev->dev; struct regmap *regmap; + struct clk *clk; int ret; =20 - ret =3D qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); - if (ret) - return ret; + clk =3D clk_get(dev, "cxo"); + if (IS_ERR(clk)) { + ret =3D qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); + if (ret) + return ret; + } =20 - ret =3D qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); - if (ret) - return ret; + clk =3D clk_get(dev, "pxo"); + if (IS_ERR(clk)) { + ret =3D qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); + if (ret) + return ret; + } =20 ret =3D qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCE48C433EF for ; Sun, 13 Mar 2022 19:05:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235339AbiCMTGV (ORCPT ); Sun, 13 Mar 2022 15:06:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235320AbiCMTGR (ORCPT ); Sun, 13 Mar 2022 15:06:17 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 128EF4BFD2; Sun, 13 Mar 2022 12:05:06 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id kt27so29712064ejb.0; Sun, 13 Mar 2022 12:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=D2y43uQNu2B9yDOF3YS3L8VYNVn6768Gl3ngt+1HuCil5SpthBL2RL8oGAbbQ/bjx6 ak1cP31XU1tdsTT17466uxqN6UdZi/zchiSDQpSxPIwBUJ+XjMDyhmHxT//rSRlYVodq 1AizAPq3jDiSeE8daDw7zL5ZghbpWO3858OyiAN47TjfKzLEu52MzNCsbw50B6IjyIMp wVNYphBWpACAGHJ5oc6wuJnXZROaxTXQSxyFcqBnRoen3tU7qTg9hI6Itth/sK39tb4E stlhNwl96F4NN8QNEz4V6EMIEp8O0abMJ22Zi0hrrFvm8dMFVrBC5NNayZr2IURR06C8 raUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XhL5PcXPAVYZIaqVjbCyrF3IgCwpUk1BeN4L/hsgGTo=; b=BETsvQ1XQXYvS3yVZJunptrFMDS2neKy0j9JxlIrK90pKB+F+GMmz0thFKcy4Rfkt9 KHHd67M3N8pN0/wLNIuhxhRfiGoVbg/BIkWWVNCcom4ZgfLThBxoRtw6fcsDKBxpx60w RGb7prBt1QdXdCukpeLIJdEBt+TL3WeLT32+m8Rwj3WVPl0ELT9bgFrf3xROA/w1Ru3C 1oD19UXe2oYoHH4SoVkAC0sjndQMkb25JmdUctiwngpgOjGEJXzstmhWfARydc1ddbBE AYrHlI7z7D23QZvva6CoVjCTxUu5w9I+RWs3o2DM6BK9tXeTqWmCOQ9BT6ZYTK1/Og3c 9sww== X-Gm-Message-State: AOAM532cTvz2q2UKntUqoWJnJJjGMqmDVA1YRQeS7j8gWhiiwCHgalF4 2G3ExgRqpCd6zhf9rmB3OaQ= X-Google-Smtp-Source: ABdhPJwyjTA7JsQ7NVKZF5OlzDXji+GJxq4tntg0MoUAznuP+aKEgxBAXZAj0YpBe5WB4AdcTdiZGw== X-Received: by 2002:a17:906:4fc4:b0:6da:b4c6:fadb with SMTP id i4-20020a1709064fc400b006dab4c6fadbmr17160389ejw.282.1647198304451; Sun, 13 Mar 2022 12:05:04 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:04 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 03/16] clk: qcom: gcc-ipq806x: add PXO_SRC in clk table Date: Sun, 13 Mar 2022 20:04:06 +0100 Message-Id: <20220313190419.2207-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PXO_SRC is currently defined in the gcc include and referenced in the ipq8064 DTSI. Correctly provide a clk after gcc probe to fix kernel panic if a driver starts to actually use it. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 27f6d7626abb..7271d3afdc89 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -26,6 +26,8 @@ #include "clk-hfpll.h" #include "reset.h" =20 +static struct clk_regmap pxo =3D { }; + static struct clk_pll pll0 =3D { .l_reg =3D 0x30c4, .m_reg =3D 0x30c8, @@ -2754,6 +2756,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk =3D { }; =20 static struct clk_regmap *gcc_ipq806x_clks[] =3D { + [PXO_SRC] =3D NULL, [PLL0] =3D &pll0.clkr, [PLL0_VOTE] =3D &pll0_vote, [PLL3] =3D &pll3.clkr, @@ -3083,6 +3086,10 @@ static int gcc_ipq806x_probe(struct platform_device = *pdev) if (ret) return ret; =20 + clk =3D clk_get(dev, "pxo"); + pxo.hw =3D *__clk_get_hw(clk); + gcc_ipq806x_clks[PXO_SRC] =3D &pxo; + regmap =3D dev_get_regmap(dev, NULL); if (!regmap) return -ENODEV; --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EA2EC46467 for ; Sun, 13 Mar 2022 19:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235375AbiCMTG3 (ORCPT ); Sun, 13 Mar 2022 15:06:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235331AbiCMTGT (ORCPT ); Sun, 13 Mar 2022 15:06:19 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B7D24C7B5; Sun, 13 Mar 2022 12:05:07 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id t1so16836989edc.3; Sun, 13 Mar 2022 12:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=fTZnAXUYeZUwUee4NNITJDgsbxWYwAQoG/PGVk3BVITqzJRM2B26EaS6H9Yn+xeLOW i+NVYI2pBj2MkklsM3/9DyssGo9vfdbueNZd+Sg8+Bf696+rKJBmP5TWauHlQrN0lTGH IagMD2jwPspZz6XvTLiRhmWngCZhWpIqSihNi+XycGs8Tp79jlAqQhKduD1YZKm+c/pR c6OnVAhsrOvFsAEigFXHBaw5pILlpvGBOfoM6Z7sP8DZ7m49+Fj3jFTk7MwdsMevruKB SPYhWZIThu9OaMKG8FldOj84uXfkp5OKl3A7ItCQm0Rok675LBjVDIkStbHfCviFc2CD J+zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8h0dp/sRCWnE/SzxqBhwWtp3OCJwunZ7486W2HMfBko=; b=BgtPPxeMmeALm2VYvC+a1p3IMjexEAwCRceDAtbOXjDaH5JvZMM+5CsN4sq53kV0g9 MwwEWmT6yMxV/1Rq4UiN4zhi1+HGaMh/+dCy4JR8MLljNuFjyV5IPpoGmtsGaaWr5ht6 GOrVLS8tm8Tz1Y6/3ee08rvRsFOoerzl6z8hTkWZHhyN7hjNP4CuvyTwAI55o24y2bTW jwTws2iE3rDM+iI3QrMMqdhcxB6Z/mmgAzHOS5k5s5Y9IU94wXecBbCMdKIo+GjVAcPc n2ZsRxoHxnhVwNQjZr/TcRzhKyL7dw4KcdAo1Dip8sOTf40DN7JH5W7lAC/GYbbjMejR bo6Q== X-Gm-Message-State: AOAM533lPqXrzCSsikOw5p2/19VI7SNRCqxgPhxxx7ZQdjeogbUb9aI2 xWYWyqFrxfYa56Ed/tVK5Kw= X-Google-Smtp-Source: ABdhPJwYxPIShgzFqu9DIExRZEI3B0Qg1ODsH5xSucqCFcL2oZov01PvEvnKI71D+RrrLT7jHyrb6A== X-Received: by 2002:a50:ab53:0:b0:415:d2cc:de46 with SMTP id t19-20020a50ab53000000b00415d2ccde46mr17268064edc.193.1647198305679; Sun, 13 Mar 2022 12:05:05 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:05 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 04/16] clk: qcom: clk-hfpll: use poll_timeout macro Date: Sun, 13 Mar 2022 20:04:07 +0100 Message-Id: <20220313190419.2207-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use regmap_read_poll_timeout macro instead of do-while structure. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-hfpll.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index e847d586a73a..a4e347eb4d4d 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -12,6 +12,8 @@ #include "clk-regmap.h" #include "clk-hfpll.h" =20 +#define HFPLL_BUSY_WAIT_TIMEOUT 100 + #define PLL_OUTCTRL BIT(0) #define PLL_BYPASSNL BIT(1) #define PLL_RESET_N BIT(2) @@ -72,13 +74,12 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); =20 /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), USEC_PER_MSEC * 2, + HFPLL_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); + else udelay(60); - } =20 /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F05C433F5 for ; Sun, 13 Mar 2022 19:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235381AbiCMTGd (ORCPT ); Sun, 13 Mar 2022 15:06:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235333AbiCMTGU (ORCPT ); Sun, 13 Mar 2022 15:06:20 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860764D26E; Sun, 13 Mar 2022 12:05:08 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id qt6so29527006ejb.11; Sun, 13 Mar 2022 12:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=RhjoKg2TAtw2kRjJHA3327WIjt7HBO2PZad5agpL27SQmL0gIx9ul6/DCku/ZDrRLw wqTUHvktBYFAyXbwzV7T9U+jx4EpMuaZnwc+RhFzE8eEMJB1uTfeO84+w9jTQAQT18Wm SzMzYR4KtBhlrkiXR+08o7nyuZGvS5DEJaYGaV8HrTsTBuAwwnZwE/yvunhq/LMIyxdZ lAG65bhgQP40a1UwWoxzx8Tyg2d+t24+s5DMY2XyFyTiL0EYWRB31GBZuo0FyF2QhJkQ HxSSQIipexM27lemK6XwI7iP6oO+0Ln9r8TAgcjnZplnJD8N0anFqPlHf5uuIpr1Fie0 L4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KJy+bVD9Yq3kRrz9Gx7NWpfnxrb/beBV0JaHxbyWaTA=; b=MdjhCPUYJ/sx68W+8q8/LjNxOjSa3HNWX2+OtFLMgzI+q0DtZBm0ClZ6L2/XmvD2Jn XC9y7bSPN5YZlB73MO4yL5ex0a1rbwgqvBcC1ROQY26B8iksOVMiY0UTC3sBeXmljavi J7Q9UUc1ev0tOsOdkBH/eeelAkaa8OARiDi87HELQDR8D6lZ5M9XwQ0t94niBQMc0xSc wPcBf8QPWQZUx8ItqJm5ke3oe2ZqSulInf78aaU5zRiWZW+Kz8UQ3l7cfygHlZbQIT2m Wuw3fJ5mUBHESp6Y/XpladAJbrq6wV8NhG1Se8jtQ1hv749D+xEQ+yDnEquhuefuLdtC BAFw== X-Gm-Message-State: AOAM530EcCUW6Jk2HxSFAmRolKU6zAEreQ/AWceTJyja0bNPeIqu+pe2 CNwKJzCtW04vnG4gyVIWImEjTxLPN9g= X-Google-Smtp-Source: ABdhPJyQJEvHRc6MxKB+uK8bAiCI+Qm3tlTDPdqbpqUaQE99wDwsEotW2XQ4RapLeZS4mZKIRpuiXQ== X-Received: by 2002:a17:907:7685:b0:6db:67:7218 with SMTP id jv5-20020a170907768500b006db00677218mr16323326ejc.461.1647198306882; Sun, 13 Mar 2022 12:05:06 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:06 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 05/16] clk: qcom: kpss-xcc: convert to parent data API Date: Sun, 13 Mar 2022 20:04:08 +0100 Message-Id: <20220313190419.2207-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. Name is still used to save regression on old definition. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/kpss-xcc.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..347f70e9f5fe 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -12,9 +12,9 @@ #include #include =20 -static const char *aux_parents[] =3D { - "pll8_vote", - "pxo", +static const struct clk_parent_data aux_parents[] =3D { + { .name =3D "pll8_vote", .fw_name =3D "pll8_vote" }, + { .name =3D "pxo", .fw_name =3D "pxo" }, }; =20 static unsigned int aux_parent_map[] =3D { @@ -32,8 +32,8 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); static int kpss_xcc_driver_probe(struct platform_device *pdev) { const struct of_device_id *id; - struct clk *clk; void __iomem *base; + struct clk_hw *hw; const char *name; =20 id =3D of_match_device(kpss_xcc_match_table, &pdev->dev); @@ -55,24 +55,15 @@ static int kpss_xcc_driver_probe(struct platform_device= *pdev) base +=3D 0x28; } =20 - clk =3D clk_register_mux_table(&pdev->dev, name, aux_parents, - ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, - 0, aux_parent_map, NULL); + hw =3D __devm_clk_hw_register_mux(&pdev->dev, NULL, name, ARRAY_SIZE(aux_= parents), + NULL, NULL, aux_parents, 0, base, 0, 0x3, + 0, aux_parent_map, NULL); =20 - platform_set_drvdata(pdev, clk); - - return PTR_ERR_OR_ZERO(clk); -} - -static int kpss_xcc_driver_remove(struct platform_device *pdev) -{ - clk_unregister_mux(platform_get_drvdata(pdev)); - return 0; + return PTR_ERR_OR_ZERO(hw); } =20 static struct platform_driver kpss_xcc_driver =3D { .probe =3D kpss_xcc_driver_probe, - .remove =3D kpss_xcc_driver_remove, .driver =3D { .name =3D "kpss-xcc", .of_match_table =3D kpss_xcc_match_table, --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2214CC433EF for ; Sun, 13 Mar 2022 19:05:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235402AbiCMTGl (ORCPT ); Sun, 13 Mar 2022 15:06:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235349AbiCMTGX (ORCPT ); Sun, 13 Mar 2022 15:06:23 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95C0D4D62F; Sun, 13 Mar 2022 12:05:09 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id y22so17068149eds.2; Sun, 13 Mar 2022 12:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=XskXl0dWUiZDjMV75GJUYOdUWBNXrTgYu3bGRKZZHL/+ZwJh7A/WyRWEvg+41zTqsV qxLLxzmxJi+YTjhjtYk487wsoQxY5JPW1XSV5ediPlSVPsDFDaPtFSu6ee9IUFFRmwTj B0uQ6b0pQS+32RbOmmq4z1lAuC3iFQQzQCjvKAA+GAT5Q6nl/FfMFMgqsyV9HncLZnHl XpbYDf/SpNJu6F36zqsjILb/Fm0SW3Ku3psCk6OBAXgrGGP8HQR3jFImQkBMQumpwWkY fWpw9bSnZfT1Q3AZlRmNj2/59fufsDT9tRiG4vwUMq6D4C3BlWvfE8p83mIJYbSpzrFw pqjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fDLuIDyRCuRCH3Dc/gWWNAl91bj4g20Fwm4jwXMbE5A=; b=f3KnQj09xxe25KBVYCrysu1NX+l20TAYaTvrFvbHIkqwJU7yBa8o3Lk1sObqmJGY5+ hfAivoA88309Evw8U8LBCBUV8/431KFELdom/s9CefprwzD7rSz/mr8vW7hJSChvE1YN Va6s2F4s08O/dmeGa0TjmXpnl7hhe126kONWQWluPxPVhE4CGfrC1AR0zK3sTPON1aX3 L/5EgYgpDv6iXvEMTcYcSyHfamBfj6vO37F3zmx0Vtk5ICKKMjTHmlS8ZPUGfPVHW4pc w6DGRq62cS3mHQ+6I8vUoISUOr7msntx2gfF5ga0zkFPUxwHyFjUUjfCkf0rFNaimlZY cVBQ== X-Gm-Message-State: AOAM530npi/3xMc6LI2a0Ouqe1fymzgbzsXwQJi9sXkMpYWgapB6cvpD su6rjC+uVRN44mxIF51w9j4= X-Google-Smtp-Source: ABdhPJxEd19rUdqjOvPTG3FNBKH26QTry81M7HjqFvgqGaJxNmoVRMrAdqyNY1orYsRzigbHw4UWDQ== X-Received: by 2002:aa7:ce1a:0:b0:416:460:9df5 with SMTP id d26-20020aa7ce1a000000b0041604609df5mr17215194edv.277.1647198308027; Sun, 13 Mar 2022 12:05:08 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:07 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 06/16] clk: qcom: clk-krait: unlock spin after mux completion Date: Sun, 13 Mar 2022 20:04:09 +0100 Message-Id: <20220313190419.2207-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Unlock spinlock after the mux switch is completed to prevent any corner case of mux request while the switch still needs to be done. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 59f1af415b58..e447fcc3806d 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -32,11 +32,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *m= ux, int sel) regval |=3D (sel & mux->mask) << (mux->shift + LPL_SHIFT); } krait_set_l2_indirect_reg(mux->offset, regval); - spin_unlock_irqrestore(&krait_clock_reg_lock, flags); =20 /* Wait for switch to complete. */ mb(); udelay(1); + + spin_unlock_irqrestore(&krait_clock_reg_lock, flags); } =20 static int krait_mux_set_parent(struct clk_hw *hw, u8 index) --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EEE2C4167E for ; Sun, 13 Mar 2022 19:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235372AbiCMTGg (ORCPT ); Sun, 13 Mar 2022 15:06:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235352AbiCMTGX (ORCPT ); Sun, 13 Mar 2022 15:06:23 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA5604DF60; Sun, 13 Mar 2022 12:05:10 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id dr20so29343598ejc.6; Sun, 13 Mar 2022 12:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sGj8B8j9Pw2IR/o72q6EjCl5T3t+1bmUyf2kYodPsRM=; b=atWc/wRl6k9wbdttykqBYuayRGkmafCvguTkpFh/NTsuYcyCynxRq2J5/yiB0HoesP RiBSVNUJUFLNVMoppLV57K+5OuY0dlBVIbF1dx33ya95GNhsAkCCU9DJ34IcVzxZ3KQk PvjlaMQ0785VqScIP10aR8OPk/fgnVDVvA3+6Z8951/6Nw50KP4C5skLDjE9vHDj3a9O faMf5NhhBmsDWxqlW4mSRDZQueLBGhla1/TSBVQ1CD018KV4UrxV7ioW4Naue4rm67i6 D5aqlVCnXrnFFbdx16zxlqXYaDp3GWKUGXXfgeQMeP/nohBD+Q0jfKg0T8f0w8WwY3g+ 2Q2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sGj8B8j9Pw2IR/o72q6EjCl5T3t+1bmUyf2kYodPsRM=; b=AdJo1zqHAS/nOGg55v0KOyEwvPpRN/kB+DJ435LYRzrSsEmysa4mIBdO0NXqk+Jbb2 B9nC57nc89v7sX/VTtwqne/h9SfJ/5L9jmJ5MHsgGLrvvN963LiHv0/d9QORHShmw3FW H+eRG4ZBMvskuYBh6hp2IVTBYEk/5tRMJKuWDDgHH2kEx0Ek679vBd7i1fT0tH9Jr9Uf n81wWZvvY4q7IyGIaK1JgCxTSpxn57Ox9i0LpA/MgO7iwLLk5SBz02d+sBrY9T7CpWi6 a0krnSVcnpf2Y8wbvY/rK9K1bclSf7NqfcqukFHcjuTGRJRYMJjd7dFewXhg6ApaBHgY dXyw== X-Gm-Message-State: AOAM533pjdgsWOdDSFyk1inlBsIzZ9leLoqcRIs/G5mbClRl44QlD7FC VmIb6xY+3qb9ZNPHJzGT5iA= X-Google-Smtp-Source: ABdhPJwpivhqHoJiBwRPTccXKrxYpEY1DhxDRe7t541Uwi34g8eEKRcRYpX2e15BDHR/DumidDT6mA== X-Received: by 2002:a17:907:9483:b0:6da:a26b:2d44 with SMTP id dm3-20020a170907948300b006daa26b2d44mr16756955ejc.337.1647198309215; Sun, 13 Mar 2022 12:05:09 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:08 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 07/16] clk: qcom: clk-krait: add hw_parent check for div2_round_rate Date: Sun, 13 Mar 2022 20:04:10 +0100 Message-Id: <20220313190419.2207-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Check if hw_parent is present before calculating the round_rate to prevent kernel panic. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index e447fcc3806d..d8af281eba0e 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -80,7 +80,12 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - *parent_rate =3D clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); + struct clk_hw *hw_parent =3D clk_hw_get_parent(hw); + + if (!hw_parent) + return -1; + + *parent_rate =3D clk_hw_round_rate(hw_parent, rate * 2); return DIV_ROUND_UP(*parent_rate, 2); } =20 --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0C97C43219 for ; Sun, 13 Mar 2022 19:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235415AbiCMTGo (ORCPT ); Sun, 13 Mar 2022 15:06:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231400AbiCMTGZ (ORCPT ); Sun, 13 Mar 2022 15:06:25 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05FFE4ECCD; Sun, 13 Mar 2022 12:05:11 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id m12so17003573edc.12; Sun, 13 Mar 2022 12:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=oIxoijt3zP8XJcuwIbWWk0ZqG42rCNQQeUcVB1jEt8bBxPjtkGfQg9/M8oViRsNm+B UUBJywclv0FdRv2179GvV6XB7J7+IR53sDj8HPcvJEt8Gq8XZ+4S9qNlyqBO0uyj9wiS e5M35cfY3VspdpoYskady1uf1jCHAFgg9aW3yallGKLoGM5DcWgx5yMPL6LiHUaNjLP7 U7uoBELO3usRmQYxSogIrhtjwX7uzJjXNOkA/T5AmCiifAaNHX/ahQoHf5w6p6uUiue8 T7FK5dn55UMJL29KadZHW+/L8v2CmSyMs04wv3u4hofuemnRUekpMUyPnFM6v0rJ6ORL rHTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tacB+H58ZcVKBVcWE3u+TMM2y65iIDEoWk8hI94hWs=; b=DnfepViLzqV+0sAQi88b6YSGD2wsPPO9K1qI4HuOCgncVcQmhzLLBHaiFjeitNOaB/ oXVzehBfd7cA09h+4ZlwUy+hw1FqT42snQPafDQhnBXj709yIE3Hk8jJSU4PZ4cVlCRy MD8re3Qh21A4RlBt+SDAsWw2nstRbAFJz8CqzxYLjUzuFjpRPFai1QKnoTNP9F40YmmI E0X3UcBJNTFmwG6MGv5odKALtEbKmb5VADTN95fYSJG5EbMz9f/hU31/z/wDAGNIiv3w fkN/r3ePoupskgbRJvLFDhLahwiISLWptARlVhTLMe4eQkUV+TC3Swkg1+L+OLBsCYin FhZw== X-Gm-Message-State: AOAM530W62p+NCJOVQOxZZuisVfzdzsZF0x7pr9FoAO25vgM2UtSA7Do Q4ckH6+fIb8jPN4NHiijewc= X-Google-Smtp-Source: ABdhPJyoFrdFHVwLiFxDlmnXTecCfhREO4r3X1G0IFC4wJ/LIVm0nWuMjUxBaDl01F4L+FHncaraZQ== X-Received: by 2002:a05:6402:40c4:b0:416:3e66:1825 with SMTP id z4-20020a05640240c400b004163e661825mr17473985edb.284.1647198310324; Sun, 13 Mar 2022 12:05:10 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:09 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 08/16] clk: qcom: krait-cc: convert to parent_data API Date: Sun, 13 Mar 2022 20:04:11 +0100 Message-Id: <20220313190419.2207-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modernize the krait-cc driver to parent-data API and refactor to drop any use of clk_names. From Documentation all the required clocks should be declared in DTS so fw_name can be correctly used to get the parents for all the muxes. Name is also declared to save compatibility with old implementation. Also fix the parent order of the sec_mux that was wrong and incorrectly report the wrong safe parent if it's not hardcoded. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 126 +++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 4d4b657d33c3..645ad9e8dd73 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -69,21 +69,22 @@ static int krait_notifier_register(struct device *dev, = struct clk *clk, return ret; } =20 -static int +static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offs= et) { struct krait_div2_clk *div; + static struct clk_parent_data p_data[1]; struct clk_init_data init =3D { - .num_parents =3D 1, + .num_parents =3D ARRAY_SIZE(p_data), .ops =3D &krait_div2_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; - const char *p_names[1]; struct clk *clk; + char *parent_name; =20 div =3D devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 div->width =3D 2; div->shift =3D 6; @@ -93,43 +94,49 @@ krait_add_div(struct device *dev, int id, const char *s= , unsigned int offset) =20 init.name =3D kasprintf(GFP_KERNEL, "hfpll%s_div", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 - init.parent_names =3D p_names; - p_names[0] =3D kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { - kfree(init.name); - return -ENOMEM; + init.parent_data =3D p_data; + parent_name =3D kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!parent_name) { + clk =3D ERR_PTR(-ENOMEM); + goto err_parent_name; } =20 + p_data[0].fw_name =3D parent_name; + p_data[0].name =3D parent_name; + clk =3D devm_clk_register(dev, &div->hw); - kfree(p_names[0]); + + kfree(parent_name); +err_parent_name: kfree(init.name); =20 - return PTR_ERR_OR_ZERO(clk); + return clk; } =20 -static int +static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { int ret; struct krait_mux_clk *mux; - static const char *sec_mux_list[] =3D { - "acpu_aux", - "qsb", + static struct clk_parent_data sec_mux_list[2] =3D { + { .name =3D "qsb", .fw_name =3D "qsb" }, + {}, }; struct clk_init_data init =3D { - .parent_names =3D sec_mux_list, + .parent_data =3D sec_mux_list, .num_parents =3D ARRAY_SIZE(sec_mux_list), .ops =3D &krait_mux_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; struct clk *clk; + char *parent_name; =20 mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 mux->offset =3D offset; mux->lpl =3D id >=3D 0; @@ -141,44 +148,51 @@ krait_add_sec_mux(struct device *dev, int id, const c= har *s, =20 init.name =3D kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 if (unique_aux) { - sec_mux_list[0] =3D kasprintf(GFP_KERNEL, "acpu%s_aux", s); - if (!sec_mux_list[0]) { + parent_name =3D kasprintf(GFP_KERNEL, "acpu%s_aux", s); + if (!parent_name) { clk =3D ERR_PTR(-ENOMEM); goto err_aux; } + sec_mux_list[1].fw_name =3D parent_name; + sec_mux_list[1].name =3D parent_name; + } else { + sec_mux_list[1].name =3D "apu_aux"; } =20 clk =3D devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; =20 ret =3D krait_notifier_register(dev, clk, mux); if (ret) - goto unique_aux; + clk =3D ERR_PTR(ret); =20 -unique_aux: +err_clk: if (unique_aux) - kfree(sec_mux_list[0]); + kfree(parent_name); err_aux: kfree(init.name); - return PTR_ERR_OR_ZERO(clk); + return clk; } =20 static struct clk * -krait_add_pri_mux(struct device *dev, int id, const char *s, - unsigned int offset) +krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *s= ec_mux, + int id, const char *s, unsigned int offset) { int ret; struct krait_mux_clk *mux; - const char *p_names[3]; + static struct clk_parent_data p_data[3]; struct clk_init_data init =3D { - .parent_names =3D p_names, - .num_parents =3D ARRAY_SIZE(p_names), + .parent_data =3D p_data, + .num_parents =3D ARRAY_SIZE(p_data), .ops =3D &krait_mux_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; struct clk *clk; + char *hfpll_name; =20 mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -196,36 +210,29 @@ krait_add_pri_mux(struct device *dev, int id, const c= har *s, if (!init.name) return ERR_PTR(-ENOMEM); =20 - p_names[0] =3D kasprintf(GFP_KERNEL, "hfpll%s", s); - if (!p_names[0]) { + hfpll_name =3D kasprintf(GFP_KERNEL, "hfpll%s", s); + if (!hfpll_name) { clk =3D ERR_PTR(-ENOMEM); - goto err_p0; + goto err_hfpll; } =20 - p_names[1] =3D kasprintf(GFP_KERNEL, "hfpll%s_div", s); - if (!p_names[1]) { - clk =3D ERR_PTR(-ENOMEM); - goto err_p1; - } + p_data[0].fw_name =3D hfpll_name; + p_data[0].name =3D hfpll_name; =20 - p_names[2] =3D kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); - if (!p_names[2]) { - clk =3D ERR_PTR(-ENOMEM); - goto err_p2; - } + p_data[1].hw =3D __clk_get_hw(hfpll_div); + p_data[2].hw =3D __clk_get_hw(sec_mux); =20 clk =3D devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + goto err_clk; =20 ret =3D krait_notifier_register(dev, clk, mux); if (ret) - goto err_p3; -err_p3: - kfree(p_names[2]); -err_p2: - kfree(p_names[1]); -err_p1: - kfree(p_names[0]); -err_p0: + clk =3D ERR_PTR(ret); + +err_clk: + kfree(hfpll_name); +err_hfpll: kfree(init.name); return clk; } @@ -233,11 +240,10 @@ krait_add_pri_mux(struct device *dev, int id, const c= har *s, /* id < 0 for L2, otherwise id =3D=3D physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_= aux) { - int ret; unsigned int offset; void *p =3D NULL; const char *s; - struct clk *clk; + struct clk *hfpll_div, *sec_mux, *clk; =20 if (id >=3D 0) { offset =3D 0x4501 + (0x1000 * id); @@ -249,19 +255,19 @@ static struct clk *krait_add_clks(struct device *dev,= int id, bool unique_aux) s =3D "_l2"; } =20 - ret =3D krait_add_div(dev, id, s, offset); - if (ret) { - clk =3D ERR_PTR(ret); + hfpll_div =3D krait_add_div(dev, id, s, offset); + if (IS_ERR(hfpll_div)) { + clk =3D hfpll_div; goto err; } =20 - ret =3D krait_add_sec_mux(dev, id, s, offset, unique_aux); - if (ret) { - clk =3D ERR_PTR(ret); + sec_mux =3D krait_add_sec_mux(dev, id, s, offset, unique_aux); + if (IS_ERR(sec_mux)) { + clk =3D sec_mux; goto err; } =20 - clk =3D krait_add_pri_mux(dev, id, s, offset); + clk =3D krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset); err: kfree(p); return clk; --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 269CEC433FE for ; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:11 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 09/16] clk: qcom: krait-cc: drop pr_info and register qsb only if needed Date: Sun, 13 Mar 2022 20:04:12 +0100 Message-Id: <20220313190419.2207-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop pr_info and change them to dev_info. Register qsb fixed clk only if it's not declared in DTS. Also reorganize variable order. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 42 +++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 645ad9e8dd73..50352ff0ac67 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -34,9 +34,10 @@ static int krait_notifier_cb(struct notifier_block *nb, unsigned long event, void *data) { - int ret =3D 0; struct krait_mux_clk *mux =3D container_of(nb, struct krait_mux_clk, clk_nb); + int ret =3D 0; + /* Switch to safe parent */ if (event =3D=3D PRE_RATE_CHANGE) { mux->old_index =3D krait_mux_clk_ops.get_parent(&mux->hw); @@ -59,7 +60,7 @@ static int krait_notifier_cb(struct notifier_block *nb, static int krait_notifier_register(struct device *dev, struct clk *clk, struct krait_mux_clk *mux) { - int ret =3D 0; + int ret; =20 mux->clk_nb.notifier_call =3D krait_notifier_cb; ret =3D clk_notifier_register(clk, &mux->clk_nb); @@ -72,15 +73,15 @@ static int krait_notifier_register(struct device *dev, = struct clk *clk, static struct clk * krait_add_div(struct device *dev, int id, const char *s, unsigned int offs= et) { - struct krait_div2_clk *div; static struct clk_parent_data p_data[1]; struct clk_init_data init =3D { .num_parents =3D ARRAY_SIZE(p_data), .ops =3D &krait_div2_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; - struct clk *clk; + struct krait_div2_clk *div; char *parent_name; + struct clk *clk; =20 div =3D devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) @@ -119,8 +120,6 @@ static struct clk * krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned int offset, bool unique_aux) { - int ret; - struct krait_mux_clk *mux; static struct clk_parent_data sec_mux_list[2] =3D { { .name =3D "qsb", .fw_name =3D "qsb" }, {}, @@ -131,8 +130,10 @@ krait_add_sec_mux(struct device *dev, int id, const ch= ar *s, .ops =3D &krait_mux_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; - struct clk *clk; + struct krait_mux_clk *mux; char *parent_name; + struct clk *clk; + int ret; =20 mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -182,8 +183,6 @@ static struct clk * krait_add_pri_mux(struct device *dev, struct clk *hfpll_div, struct clk *s= ec_mux, int id, const char *s, unsigned int offset) { - int ret; - struct krait_mux_clk *mux; static struct clk_parent_data p_data[3]; struct clk_init_data init =3D { .parent_data =3D p_data, @@ -191,8 +190,10 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpl= l_div, struct clk *sec_mux .ops =3D &krait_mux_clk_ops, .flags =3D CLK_SET_RATE_PARENT, }; - struct clk *clk; + struct krait_mux_clk *mux; char *hfpll_name; + struct clk *clk; + int ret; =20 mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) @@ -240,10 +241,10 @@ krait_add_pri_mux(struct device *dev, struct clk *hfp= ll_div, struct clk *sec_mux /* id < 0 for L2, otherwise id =3D=3D physical CPU number */ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_= aux) { + struct clk *hfpll_div, *sec_mux, *clk; unsigned int offset; void *p =3D NULL; const char *s; - struct clk *hfpll_div, *sec_mux, *clk; =20 if (id >=3D 0) { offset =3D 0x4501 + (0x1000 * id); @@ -295,20 +296,21 @@ MODULE_DEVICE_TABLE(of, krait_cc_match_table); =20 static int krait_cc_probe(struct platform_device *pdev) { + unsigned long cur_rate, aux_rate; + struct clk *l2_pri_mux_clk, *clk; struct device *dev =3D &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; - struct clk *clk; struct clk **clks; - struct clk *l2_pri_mux_clk; + int cpu; =20 id =3D of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; =20 /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk =3D clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk_get(dev, "qsb"))) + clk =3D clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + if (IS_ERR(clk)) return PTR_ERR(clk); =20 @@ -363,25 +365,25 @@ static int krait_cc_probe(struct platform_device *pde= v) cur_rate =3D clk_get_rate(l2_pri_mux_clk); aux_rate =3D 384000000; if (cur_rate =3D=3D 1) { - pr_info("L2 @ QSB rate. Forcing new rate.\n"); + dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate =3D aux_rate; } clk_set_rate(l2_pri_mux_clk, aux_rate); clk_set_rate(l2_pri_mux_clk, 2); clk_set_rate(l2_pri_mux_clk, cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); + dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); for_each_possible_cpu(cpu) { clk =3D clks[cpu]; cur_rate =3D clk_get_rate(clk); if (cur_rate =3D=3D 1) { - pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); + dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate =3D aux_rate; } =20 clk_set_rate(clk, aux_rate); clk_set_rate(clk, 2); clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); + dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); } =20 of_clk_add_provider(dev->of_node, krait_of_get, clks); --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40425C433F5 for ; Sun, 13 Mar 2022 19:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234795AbiCMTG5 (ORCPT ); Sun, 13 Mar 2022 15:06:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235305AbiCMTGd (ORCPT ); Sun, 13 Mar 2022 15:06:33 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A98D5006C; Sun, 13 Mar 2022 12:05:14 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id p15so29580790ejc.7; Sun, 13 Mar 2022 12:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q3b6ElFuNAjEzox0VnbXAUoCVQRKSTTTamOGAckJEC4=; b=K022jRyjFjm8Ok5yoeqDM32OVXzRct5OUuieKyISOdxr22+ycrTGo5K3KHX+6LU6wT 6IVQtnRAKscm9CPZyPaRnH81Wydx/ChpEJ0MHpXoZpXgk69qAM+hrXcci9rhvFdedQHq tIEbaUyZXsgHvEWVETGT1VLUgDzHddjzcYudS1O22621dEb/IJuJHMSMAOD4Dt/drlmK JcSpPvyc/ZkADj1zIWDUwYyHkYWbMd1vA7l6jYNBgs872GP7CLPPxHvMsaKERm1xo08D vkj3v6h0L5d7D7OsdZgrcOi/gIURKDHZ39DE8ZjR2lk3NXP0kiJabI0+nJM9ckbrzW2c 1Tjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q3b6ElFuNAjEzox0VnbXAUoCVQRKSTTTamOGAckJEC4=; b=pKSGf743lqWvpi19uSoqaEQLVtQA4UnwYhgi9Sa1te8oqLHUtAWRJZ0OHPCrbzd4Hr 49NRjfgd+Nks4nGUuQNvOdRSBH00ajZbhE0y7CTSGq7qZ+/UTxwyug/eBX3TwWDqNpxU sKJAj29W05QG5D8LI1I8vtId1Y85OaLG5ULbwgufS3mcvozcIDRrXBlyGKotu5+9pM3t wr1GH81Mdoh2iahiI0QuCnX+vfWofnOgVth25/MixwWN6cS9/pZmVOUGziHZrbjmrm0D BaAHJzDXOB5V1XUtwI5WJs6qMiYKpoe381RWniPXaKTBcFxP1ldfrVmv1HLAT3FbSImO XymA== X-Gm-Message-State: AOAM533MSwA5qWHmkj5nXb6Wv28KRggVSKamiCPg/cKIE6Yy8Lb3D9qf whMfuNwTgkyaJbamJOHK6fw= X-Google-Smtp-Source: ABdhPJy9z9Eor0s/HxJ4petV2/EuaBbA89rk6mQ7GAunlGLTlMHPvl9J1+ArysqMKsvzzVwT0deoQw== X-Received: by 2002:a17:906:7706:b0:6d6:e521:5471 with SMTP id q6-20020a170906770600b006d6e5215471mr16050002ejm.387.1647198312484; Sun, 13 Mar 2022 12:05:12 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:12 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 10/16] clk: qcom: krait-cc: drop hardcoded safe_sel Date: Sun, 13 Mar 2022 20:04:13 +0100 Message-Id: <20220313190419.2207-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop hardcoded safe_sel definition and use helper to correctly calculate it. We assume qsb clk is always present as it should be declared in DTS per Documentation and in the absence of that, it's declared as a fixed clk. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 50352ff0ac67..6530f10a546f 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -26,6 +26,13 @@ static unsigned int pri_mux_map[] =3D { 0, }; =20 +static u8 krait_get_mux_sel(struct krait_mux_clk *mux, struct clk *safe_cl= k) +{ + struct clk_hw *safe_hw =3D __clk_get_hw(safe_clk); + + return clk_hw_get_parent_index(&mux->hw, safe_hw); +} + /* * Notifier function for switching the muxes to safe parent * while the hfpll is getting reprogrammed. @@ -117,8 +124,8 @@ krait_add_div(struct device *dev, int id, const char *s= , unsigned int offset) } =20 static struct clk * -krait_add_sec_mux(struct device *dev, int id, const char *s, - unsigned int offset, bool unique_aux) +krait_add_sec_mux(struct device *dev, struct clk *qsb, int id, + const char *s, unsigned int offset, bool unique_aux) { static struct clk_parent_data sec_mux_list[2] =3D { { .name =3D "qsb", .fw_name =3D "qsb" }, @@ -145,7 +152,6 @@ krait_add_sec_mux(struct device *dev, int id, const cha= r *s, mux->shift =3D 2; mux->parent_map =3D sec_mux_map; mux->hw.init =3D &init; - mux->safe_sel =3D 0; =20 init.name =3D kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) @@ -167,6 +173,7 @@ krait_add_sec_mux(struct device *dev, int id, const cha= r *s, if (IS_ERR(clk)) goto err_clk; =20 + mux->safe_sel =3D krait_get_mux_sel(mux, qsb); ret =3D krait_notifier_register(dev, clk, mux); if (ret) clk =3D ERR_PTR(ret); @@ -205,7 +212,6 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll= _div, struct clk *sec_mux mux->lpl =3D id >=3D 0; mux->parent_map =3D pri_mux_map; mux->hw.init =3D &init; - mux->safe_sel =3D 2; =20 init.name =3D kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); if (!init.name) @@ -227,6 +233,7 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll= _div, struct clk *sec_mux if (IS_ERR(clk)) goto err_clk; =20 + mux->safe_sel =3D krait_get_mux_sel(mux, sec_mux); ret =3D krait_notifier_register(dev, clk, mux); if (ret) clk =3D ERR_PTR(ret); @@ -239,7 +246,9 @@ krait_add_pri_mux(struct device *dev, struct clk *hfpll= _div, struct clk *sec_mux } =20 /* id < 0 for L2, otherwise id =3D=3D physical CPU number */ -static struct clk *krait_add_clks(struct device *dev, int id, bool unique_= aux) +static struct clk * +krait_add_clks(struct device *dev, struct clk *qsb, int id, + bool unique_aux) { struct clk *hfpll_div, *sec_mux, *clk; unsigned int offset; @@ -262,7 +271,7 @@ static struct clk *krait_add_clks(struct device *dev, i= nt id, bool unique_aux) goto err; } =20 - sec_mux =3D krait_add_sec_mux(dev, id, s, offset, unique_aux); + sec_mux =3D krait_add_sec_mux(dev, qsb, id, s, offset, unique_aux); if (IS_ERR(sec_mux)) { clk =3D sec_mux; goto err; @@ -296,8 +305,8 @@ MODULE_DEVICE_TABLE(of, krait_cc_match_table); =20 static int krait_cc_probe(struct platform_device *pdev) { + struct clk *l2_pri_mux_clk, *qsb, *clk; unsigned long cur_rate, aux_rate; - struct clk *l2_pri_mux_clk, *clk; struct device *dev =3D &pdev->dev; const struct of_device_id *id; struct clk **clks; @@ -308,11 +317,12 @@ static int krait_cc_probe(struct platform_device *pde= v) return -ENODEV; =20 /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - if (IS_ERR(clk_get(dev, "qsb"))) - clk =3D clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + qsb =3D clk_get(dev, "qsb"); + if (IS_ERR(qsb)) + qsb =3D clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); =20 - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(qsb)) + return PTR_ERR(qsb); =20 if (!id->data) { clk =3D clk_register_fixed_factor(dev, "acpu_aux", @@ -327,13 +337,13 @@ static int krait_cc_probe(struct platform_device *pde= v) return -ENOMEM; =20 for_each_possible_cpu(cpu) { - clk =3D krait_add_clks(dev, cpu, id->data); + clk =3D krait_add_clks(dev, qsb, cpu, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); clks[cpu] =3D clk; } =20 - l2_pri_mux_clk =3D krait_add_clks(dev, -1, id->data); + l2_pri_mux_clk =3D krait_add_clks(dev, qsb, -1, id->data); if (IS_ERR(l2_pri_mux_clk)) return PTR_ERR(l2_pri_mux_clk); clks[4] =3D l2_pri_mux_clk; --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B27C433EF for ; Sun, 13 Mar 2022 19:06:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233044AbiCMTHE (ORCPT ); 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:13 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 11/16] clk: qcom: krait-cc: force sec_mux to QSB Date: Sun, 13 Mar 2022 20:04:14 +0100 Message-Id: <20220313190419.2207-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that we have converted every driver to parent_data, it was notice that the bootloader can't really leave the system in a strange state where l2 or the cpu0/1 can be sourced in a number of ways for example cpu1 sourcing out of qsb, l2 sourcing out of pxo. To correctly reset the mux and the HFPLL force the sec_mux to QSB. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/krait-cc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 6530f10a546f..1bdc89c097e6 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -15,6 +15,8 @@ =20 #include "clk-krait.h" =20 +#define QSB_RATE 1 + static unsigned int sec_mux_map[] =3D { 2, 0, @@ -178,6 +180,12 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb,= int id, if (ret) clk =3D ERR_PTR(ret); =20 + /* Force the sec_mux to be set to QSB rate. + * This is needed to correctly set the parents and + * to later reset mux and HFPLL to a known freq. + */ + clk_set_rate(clk, QSB_RATE); + err_clk: if (unique_aux) kfree(parent_name); @@ -374,7 +382,7 @@ static int krait_cc_probe(struct platform_device *pdev) */ cur_rate =3D clk_get_rate(l2_pri_mux_clk); aux_rate =3D 384000000; - if (cur_rate =3D=3D 1) { + if (cur_rate =3D=3D QSB_RATE) { dev_info(dev, "L2 @ QSB rate. Forcing new rate.\n"); cur_rate =3D aux_rate; } @@ -385,7 +393,7 @@ static int krait_cc_probe(struct platform_device *pdev) for_each_possible_cpu(cpu) { clk =3D clks[cpu]; cur_rate =3D clk_get_rate(clk); - if (cur_rate =3D=3D 1) { + if (cur_rate =3D=3D QSB_RATE) { dev_info(dev, "CPU%d @ QSB rate. Forcing new rate.\n", cpu); cur_rate =3D aux_rate; } --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2D5AC4332F for ; Sun, 13 Mar 2022 19:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235471AbiCMTHP (ORCPT ); Sun, 13 Mar 2022 15:07:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235349AbiCMTGl (ORCPT ); Sun, 13 Mar 2022 15:06:41 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BEE9506E5; Sun, 13 Mar 2022 12:05:16 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id qa43so29422021ejc.12; Sun, 13 Mar 2022 12:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sEQR7AHep43bwZwVHXAE2cEONvRXMp4DrDQG9qka08M=; b=Sz87HYVsoKtiiOuHvJ2WAz9s27Dc7vz6VwvczrwWbn33hJLQ7c5xQzRrqfHvgoitpp MOq1Y5c6rlONCTvZt1iU0y/TC4L4L6bKo9tfo0kHqWffk1ILj2AbeHq/2lwgV5kmxAtg kARmmXJOO5Aq5tSsaOF9gJCValwDoMB1lirS392xbQJdDHUKEMquUNhecxBCldbJD51/ pkyNNtXjDv4204rz52OLTKHwP4GT6UlY1dz3q26FIkbvo36wSST3OmrouGVc9JAkvEYq 8OYJ+QgwTnIrUiH0dH42LT7aC2c8cK7jhQ7JTyB80/JHvYSlTWIXTfAQJqWFNPUwtsah Q/Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sEQR7AHep43bwZwVHXAE2cEONvRXMp4DrDQG9qka08M=; b=Z1319PC1eM9zndNBBaBXKkKRwwXG42F7lploNSPkz+n7aCLeX2u0lPyLEB0txhKzTA PxXPHtDJg+8qPbMwvSB0CQWb7n0AatFzduX8Zo+CyANVkSNBD4YRk3a06g7rOG6r534b bjcjT4xVVYUYxXbdT6rbPwUe3mWAhXP5OzY2ogt2hUnCcJ5r8IdaLywPa6T4uA7sC6ca aZMF97Nn/xPQI8LNOZeKdR4+LDpwr/nR831ro3NZeAMdqtO6Mpg8N4X6E9PqC/3usqvr SwvPu/TpNaB1XxE3+3X91hJZtHlHnwnmvejgwzIvBWkQGDYBMsKmX/Mb2MrUhq8oQUcE Vxjg== X-Gm-Message-State: AOAM531MVnEiO4/9xHUQ8zAIk1qoYn/kD3WEmm5mvOBa94KwTKGIzviv kOO0OJwarSo3DI8dxwlcZUo= X-Google-Smtp-Source: ABdhPJzJSvZYpZkmGjsnohew5wdo1ux3J5zVQpqlGhuzOBMbIRj96up6V93GUgT0NEoWBVVpsA1piw== X-Received: by 2002:a17:906:7954:b0:6da:9ee0:2e54 with SMTP id l20-20020a170906795400b006da9ee02e54mr16921227ejo.630.1647198314701; Sun, 13 Mar 2022 12:05:14 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:14 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 12/16] clk: qcom: clk-krait: add 8064 errata workaround Date: Sun, 13 Mar 2022 20:04:15 +0100 Message-Id: <20220313190419.2207-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add 8064 errata workaround where the sec_src clock gating needs to be disabled during switching. To enable this set disable_sec_src_gating in the mux struct. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++ drivers/clk/qcom/clk-krait.h | 1 + drivers/clk/qcom/krait-cc.c | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index d8af281eba0e..82fe7031e1f4 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -18,13 +18,23 @@ static DEFINE_SPINLOCK(krait_clock_reg_lock); =20 #define LPL_SHIFT 8 +#define SECCLKAGD BIT(4) + static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) { unsigned long flags; u32 regval; =20 spin_lock_irqsave(&krait_clock_reg_lock, flags); + regval =3D krait_get_l2_indirect_reg(mux->offset); + + /* 8064 Errata: disable sec_src clock gating during switch. */ + if (mux->disable_sec_src_gating) { + regval |=3D SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + regval &=3D ~(mux->mask << mux->shift); regval |=3D (sel & mux->mask) << mux->shift; if (mux->lpl) { @@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct krait_mux_clk *mu= x, int sel) } krait_set_l2_indirect_reg(mux->offset, regval); =20 + /* 8064 Errata: re-enabled sec_src clock gating. */ + if (mux->disable_sec_src_gating) { + regval &=3D ~SECCLKAGD; + krait_set_l2_indirect_reg(mux->offset, regval); + } + /* Wait for switch to complete. */ mb(); udelay(1); diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h index 9120bd2f5297..f930538c539e 100644 --- a/drivers/clk/qcom/clk-krait.h +++ b/drivers/clk/qcom/clk-krait.h @@ -15,6 +15,7 @@ struct krait_mux_clk { u8 safe_sel; u8 old_index; bool reparent; + bool disable_sec_src_gating; =20 struct clk_hw hw; struct notifier_block clk_nb; diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 1bdc89c097e6..533a770332be 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -154,6 +154,7 @@ krait_add_sec_mux(struct device *dev, struct clk *qsb, = int id, mux->shift =3D 2; mux->parent_map =3D sec_mux_map; mux->hw.init =3D &init; + mux->disable_sec_src_gating =3D true; =20 init.name =3D kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); if (!init.name) --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17FD2C43219 for ; Sun, 13 Mar 2022 19:06:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235460AbiCMTHK (ORCPT ); Sun, 13 Mar 2022 15:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235404AbiCMTGl (ORCPT ); Sun, 13 Mar 2022 15:06:41 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 806BB50B13; Sun, 13 Mar 2022 12:05:17 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a8so29583203ejc.8; Sun, 13 Mar 2022 12:05:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ULORFmB1Gv653NhwYAC6GyuMCDu1OWN34Ide113fYeY=; b=jLZx6wHRAQlKhDJq8r1pf+twX5RsUltvQMFTKUyaZOIJHmvCGm60JM5AWPsMmoo9kf 4f2Zh1MzbE5QaCzShn8HEoVMDNi+Iwe9y1GR7uPw/9ddI8tbEZLFnAT37eb6rPn4NA2i Z6MztMJafR88Nmu4cUhShdLBFS6s1GhpnbhbOmJn19eqfP2JTZ3pK8HVQavg0SwjBurd AEP7MqUReH6kgOEE8xR3Er930To+yPqhshHnGUTWaqxqGkdLGM+oF8SpbGwWpmSylEOX ONYf3wzXmrwd6X1XaNNjvL0hWZju7iMng6aYOIAqTSvhmBoHWrOvLzWQOpRLnLFVh8PN Xbsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ULORFmB1Gv653NhwYAC6GyuMCDu1OWN34Ide113fYeY=; b=39o98h+pZPqhWehlVh62zZwciQ4J+JmxWZ1yafDeg3Hg0KfngA7Lmti7nJxivZPzQ/ KW7VDej7gDwSVwdO+2twHyvInJSc6npb8gImHGCDYja1U3ACpRQSPxZiNu8LQt8Z2Z6j 9jcYQ4nTMhN4LIJS4EWNhW5Y0EdxmOqDlOw2clslc01yy/Qb3z99QBZHy11thOUhDrnb aPTuUqdDSuMpVG07oor48SQcrvgd0zGvpuCce++Z8DF1PX/wEvccpwrSC3zbNahX32oR kkXDNRkE6/bJLwRslSdciM0N1Hn6t5eluT3fCmw/iLYWIKuzp6ayGyqNb3+pgi3Q9JED ZDxw== X-Gm-Message-State: AOAM5329zy5sS7fo3LMkoP8vRV3a/IgiBjwnmhmYYBTS/edThzbbB2vq BmlJFJhdTodwQuQpEN3hY1o= X-Google-Smtp-Source: ABdhPJxRL8RZcsidjudMbrw77ttd/RNpbT/GvMdVejgX0mXy/oMdLgL07Djq6C91LDW0EBoL1481gQ== X-Received: by 2002:a17:906:9b8f:b0:6db:ab62:4713 with SMTP id dd15-20020a1709069b8f00b006dbab624713mr9662533ejc.738.1647198315903; Sun, 13 Mar 2022 12:05:15 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:15 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 13/16] clk: qcom: clk-krait: add enable disable ops Date: Sun, 13 Mar 2022 20:04:16 +0100 Message-Id: <20220313190419.2207-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add enable/disable ops for krait mux. On disable the mux is set to the safe selection. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/clk-krait.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index 82fe7031e1f4..fc277fe3841c 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -85,7 +85,25 @@ static u8 krait_mux_get_parent(struct clk_hw *hw) return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); } =20 +static int krait_mux_enable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux =3D to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->en_mask); + + return 0; +} + +static void krait_mux_disable(struct clk_hw *hw) +{ + struct krait_mux_clk *mux =3D to_krait_mux_clk(hw); + + __krait_mux_set_sel(mux, mux->safe_sel); +} + const struct clk_ops krait_mux_clk_ops =3D { + .enable =3D krait_mux_enable, + .disable =3D krait_mux_disable, .set_parent =3D krait_mux_set_parent, .get_parent =3D krait_mux_get_parent, .determine_rate =3D __clk_mux_determine_rate_closest, --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A678C433F5 for ; Sun, 13 Mar 2022 19:06:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235492AbiCMTHY (ORCPT ); Sun, 13 Mar 2022 15:07:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235430AbiCMTGs (ORCPT ); Sun, 13 Mar 2022 15:06:48 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1401751336; Sun, 13 Mar 2022 12:05:19 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id d10so29556480eje.10; Sun, 13 Mar 2022 12:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fMAOn8pwa3go68WYxvsLY0rJlkkqdpP8FjSo1TfU57o=; b=iaD4nEn8TP5faC6pEMwcRqU4nV8uFaV9PEQjF0q819n6g75l3gqLEmvDn6SR6sYuV+ DCgflnLnhDNhSzN5eiK+Q7VHwoGya248hwgVjixVOL9qKnZ75yervrC1g1kdnPqne20P AM3Ew2vYgv5Hzo1tDItHRm2Y6gSqHM1tnabgWPs9jcwGPk7WDh9aK9I8MbKNurHbmxgI sVM3CW3AyTXWXrcXWAxk/YP7AaSibMyJhBWIqDN47jDKVtoSSqH5G63Fy+KEBund/KBB GhQZ/kl0gKvA508xxGZAn8yydbF2gDyMLr60+0TdzARkz06lnHaEfEQgI0ozOU3V4lkW OhHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fMAOn8pwa3go68WYxvsLY0rJlkkqdpP8FjSo1TfU57o=; b=TH2BxIWsWTZGzc2ScvfhWobX0cG8OU8eXHPbsZLN7+U3UoakaBHWWyLTiKCtCA+Mj9 UEFeyLiCbcIuNd+C1EWcHY7/tgHy4gFB/z+vRsBozvWiNUzr2hRftgK/cJPVc2FL9LfS QjEGRjx/fCq3orLlQYPI/td+Hi0jRdXSrq/rzaBjNLj0cxeI6P7Jm4KbiMXX0zT2h1cJ EpS4subBKt2HE4GTxgS+r2UPgtJTdlvwvjduKoiY3MfRY17k+Kk2hvCRMgr9wmjKhmAd S5FwqKpCChrXSkmyg44Vgh2FKS6o/ujExsOwCq9znjYTciI/wtQR39qBa12RwLnxFgzh ivug== X-Gm-Message-State: AOAM532Wz6VpCRrt5oM0s4AaEwcQaMJf66gMqKWuRCi4c3GDA/k9U5fG jNJeXukRe6vhYxAX0QNR3SU= X-Google-Smtp-Source: ABdhPJzf4xDkkfnpb+RM9j0/iSL/WQMVi2u50zBYUZftCYGQ6lnYQdMtI5BTO8qZKzaTYy27FrYP6A== X-Received: by 2002:a17:907:8a0d:b0:6d6:dae9:7263 with SMTP id sc13-20020a1709078a0d00b006d6dae97263mr16380785ejc.671.1647198317421; Sun, 13 Mar 2022 12:05:17 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:17 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 14/16] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Sun, 13 Mar 2022 20:04:17 +0100 Message-Id: <20220313190419.2207-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert qcom,krait-cc to yaml and add missing l2 clocks and names definiton. Signed-off-by: Ansuel Smith --- .../bindings/clock/qcom,krait-cc.txt | 34 ---------- .../bindings/clock/qcom,krait-cc.yaml | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.t= xt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.y= aml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Do= cumentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible =3D "qcom,krait-cc-v1"; - clocks =3D <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names =3D "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells =3D <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/D= ocumentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..f89b70ab01ae --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Ansuel Smith + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the = L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to hfpll for L2 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to L2 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: hfpll_l2 + - const: acpu0_aux + - const: acpu1_aux + - const: acpu_l2_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible =3D "qcom,krait-cc-v1"; + clocks =3D <&hfpll0>, <&hfpll1>, <&hfpll_l2>, + <&acpu0_aux>, <&acpu1_aux>, <&acpu_l2_aux>, <&qsb>; + clock-names =3D "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", "qsb"; + #clock-cells =3D <1>; + }; +... --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9889BC433EF for ; Sun, 13 Mar 2022 19:06:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235450AbiCMTHT (ORCPT ); Sun, 13 Mar 2022 15:07:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234615AbiCMTHG (ORCPT ); Sun, 13 Mar 2022 15:07:06 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ED4E51E4B; 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[93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:18 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 15/16] dts: qcom-ipq8064: add missing krait-cc compatible and clocks Date: Sun, 13 Mar 2022 20:04:18 +0100 Message-Id: <20220313190419.2207-16-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add missing krait-cc clock-controller and define missing aux clock for CPUs. Also change phandle for l2cc node to point to pxo_board instead of gcc PXO_SRC. Signed-off-by: Ansuel Smith --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-i= pq8064.dtsi index 996f4458d9fc..888f17d64283 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -468,11 +468,19 @@ IRQ_TYPE_EDGE_RISING)>, acc0: clock-controller@2088000 { compatible =3D "qcom,kpss-acc-v1"; reg =3D <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names =3D "acpu0_aux"; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + #clock-cells =3D <0>; }; =20 acc1: clock-controller@2098000 { compatible =3D "qcom,kpss-acc-v1"; reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names =3D "acpu1_aux"; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + #clock-cells =3D <0>; }; =20 adm_dma: dma-controller@18300000 { @@ -782,11 +790,21 @@ tcsr: syscon@1a400000 { l2cc: clock-controller@2011000 { compatible =3D "qcom,kpss-gcc", "syscon"; reg =3D <0x2011000 0x1000>; - clocks =3D <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; clock-names =3D "pll8_vote", "pxo"; clock-output-names =3D "acpu_l2_aux"; }; =20 + kraitcc: clock-controller { + compatible =3D "qcom,krait-cc-v1"; + clocks =3D <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>, + <&acc0>, <&acc1>, <&l2cc>, <&qsb>; + clock-names =3D "hfpll0", "hfpll1", "hfpll_l2", + "acpu0_aux", "acpu1_aux", "acpu_l2_aux", + "qsb"; + #clock-cells =3D <1>; + }; + lcc: clock-controller@28000000 { compatible =3D "qcom,lcc-ipq8064"; reg =3D <0x28000000 0x1000>; --=20 2.34.1 From nobody Tue Jun 23 02:05:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0793AC433EF for ; Sun, 13 Mar 2022 19:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231449AbiCMTH3 (ORCPT ); Sun, 13 Mar 2022 15:07:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235439AbiCMTHH (ORCPT ); Sun, 13 Mar 2022 15:07:07 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69450522F8; Sun, 13 Mar 2022 12:05:21 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id c25so14890967edj.13; Sun, 13 Mar 2022 12:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JKvRH6qETF7tlJx+dsXAKSPYL+SWlaM9ukoK0I4vd0Y=; b=HOg380wgKBY11dC56PSqlnJRAWm0g0eKLM6MS9EErmqMYvsPALeL5n0fAfcn0hnj+A RsD0ImwNt5CMOjrHnMtJdOmVfuoyE9DYBX63nOGFN4YWYDsVSFwAp7+f2rDbqe6/qfiw HsahrzeDrO+FUpOOTavGLlDQIHLCUGVERUuQrT6RA0jVN+ka2qbBnu5WLQqZzGkyj6em wmxGE8eYN2pEmK8bBjS0fZA8JzuNyBykYjZd61Sve0T+RKzk1/ExGbBUyoqpLTgco+YA roPReKgBfRrdEGtjRFyD3aW9OmcrqBukNk3gt8bUXxupmAhQRr1TAY756l4OWAJBpVuZ Px5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JKvRH6qETF7tlJx+dsXAKSPYL+SWlaM9ukoK0I4vd0Y=; b=Luk13BsAMwt4HnXKXRH3FyFM/JAjiWVuko93nugNsDpP2TDvNACY17JgdY+NkviACO lJgPyK04QLESy6h/pWJS6h4qaqeqlhFX21BhjxKXiOkzZAa76lKwGEiSBm1FqabmYnwK hXD2fksnycVjIl5wQL+JzGBcfGpVlCCxSVU/BD5zCBCU7ePE8h1js8dTHMzRFHlL9t94 63PRHn6LPCoWhR60XtJFrux0f3G3aBSn/kqtG2iTzfgnpSzUh92m5qCcALEbzBJ7STYo T3/T79vOn/1Acu9uSwPyfgbfGbKTqOFTeFaZ1j6Fn6L7v/+l4I8rzGkpKpkISr7YNzMD aa0Q== X-Gm-Message-State: AOAM531AuHC41auvSyuxeqkDCEHnBKWdLlxJjfEW/w5iEfLs3UdflD2z KKZ6ghuKpl4LCaUpV5im6g0= X-Google-Smtp-Source: ABdhPJxs+nfgAzGM4p+i4X9YMiFAOiMeFYrAnRJILHkWAeKTBnmcY2vUaKyN8+URhUYmZUnU5vntWw== X-Received: by 2002:a05:6402:5173:b0:415:f1e2:8d53 with SMTP id d19-20020a056402517300b00415f1e28d53mr17417672ede.95.1647198319607; Sun, 13 Mar 2022 12:05:19 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-42-71-246.ip85.fastwebnet.it. [93.42.71.246]) by smtp.googlemail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm5856697ejk.119.2022.03.13.12.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 12:05:19 -0700 (PDT) From: Ansuel Smith To: Rob Herring , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ansuel Smith , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 16/16] dt-bindings: arm: msm: Convert kpss driver Documentation to yaml Date: Sun, 13 Mar 2022 20:04:19 +0100 Message-Id: <20220313190419.2207-17-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220313190419.2207-1-ansuelsmth@gmail.com> References: <20220313190419.2207-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert kpss-acc and kpss-gcc Documentation to yaml. Fix multiple Documentation error and provide additional example for kpss-gcc-v2. Signed-off-by: Ansuel Smith --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ---------- .../bindings/arm/msm/qcom,kpss-acc.yaml | 97 +++++++++++++++++++ .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 --------- .../bindings/arm/msm/qcom,kpss-gcc.yaml | 62 ++++++++++++ 4 files changed, 159 insertions(+), 93 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc= .txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc= .yaml delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc= .txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc= .yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/= Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CP= U. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible =3D "qcom,kpss-acc-v2"; - reg =3D <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks =3D <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names =3D "pll8_vote", "pxo"; - clock-output-names =3D "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml b= /Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml new file mode 100644 index 000000000000..6e8ef4f85eab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-acc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +maintainers: + - Ansuel Smith + +description: | + The KPSS ACC provides clock, power domain, and reset control to a Krait = CPU. + There is one ACC register region per CPU within the KPSS remapped region= as + well as an alias register region that remaps accesses to the ACC associa= ted + with the CPU accessing the region. + +properties: + compatible: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register = region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,kpss-acc-v1 + then: + required: + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible =3D "qcom,kpss-acc-v1"; + reg =3D <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + clock-output-names =3D "acpu0_aux"; + #clock-cells =3D <0>; + }; + + clock-controller@2098000 { + compatible =3D "qcom,kpss-acc-v1"; + reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names =3D "acpu1_aux"; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + #clock-cells =3D <0>; + }; + + - | + clock-controller@f9088000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/= Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible =3D "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg =3D <0x2011000 0x1000>; - clocks =3D <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names =3D "pll8_vote", "pxo"; - clock-output-names =3D "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b= /Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..3a2b54cc6a7c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Ansuel Smith + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation). + +properties: + compatible: + const: qcom,kpss-gcc + + reg: + items: + - description: Base address and size of the register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + const: acpu_l2_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible =3D "qcom,kpss-gcc"; + reg =3D <0x2011000 0x1000>; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + clock-output-names =3D "acpu_l2_aux"; + #clock-cells =3D <0>; + }; +... \ No newline at end of file --=20 2.34.1