From nobody Sun Sep 22 07:30:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEC02C433F5 for ; Fri, 11 Mar 2022 13:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348921AbiCKNgq (ORCPT ); Fri, 11 Mar 2022 08:36:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348894AbiCKNgo (ORCPT ); Fri, 11 Mar 2022 08:36:44 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AF7419BE63; Fri, 11 Mar 2022 05:35:36 -0800 (PST) X-UUID: db0f0db475c74c00aebf51a8dad6331c-20220311 X-UUID: db0f0db475c74c00aebf51a8dad6331c-20220311 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 880253415; Fri, 11 Mar 2022 21:35:33 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 21:35:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 21:35:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 21:35:31 +0800 From: Jianjun Wang To: Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger CC: Jianjun Wang , , , , , , , , , , , Subject: [PATCH 1/2] phy: mediatek: Add PCIe PHY driver Date: Fri, 11 Mar 2022 21:35:26 +0800 Message-ID: <20220311133527.5914-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311133527.5914-1-jianjun.wang@mediatek.com> References: <20220311133527.5914-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCIe GEN3 PHY driver support on MediaTek chipsets. Signed-off-by: Jianjun Wang --- drivers/phy/mediatek/Kconfig | 11 ++ drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-pcie.c | 198 ++++++++++++++++++++++++++++ 3 files changed, 210 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 55f8e6c048ab..387ed1b3f2cc 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -55,3 +55,14 @@ config PHY_MTK_MIPI_DSI select GENERIC_PHY help Support MIPI DSI for Mediatek SoCs. + +config PHY_MTK_PCIE + tristate "MediaTek PCIe-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN3 port, it supports software efuse + initialization. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index ace660fbed3a..788c13147f63 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_MTK_TPHY) +=3D phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) +=3D phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) +=3D phy-mtk-xsphy.o +obj-$(CONFIG_PHY_MTK_PCIE) +=3D phy-mtk-pcie.o =20 phy-mtk-hdmi-drv-y :=3D phy-mtk-hdmi.o phy-mtk-hdmi-drv-y +=3D phy-mtk-hdmi-mt2701.o diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy= -mtk-pcie.c new file mode 100644 index 000000000000..45a67d9171f6 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-pcie.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Jianjun Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-mtk-io.h" + +#define PEXTP_ANA_GLB_00_REG 0x9000 +#define PEXTP_ANA_LN0_TX_REG 0xA004 +#define PEXTP_ANA_LN0_RX_REG 0xA03C +#define PEXTP_ANA_LN1_TX_REG 0xA104 +#define PEXTP_ANA_LN1_RX_REG 0xA13c + +/* PEXTP_GLB_00_RG[28:24] Internal Resistor Selection of TX Bias Current */ +#define EFUSE_GLB_INTR_SEL GENMASK(28, 24) +#define EFUSE_GLB_INTR_VAL(x) ((0x1f & (x)) << 24) + +/* PEXTP_ANA_LN_RX_RG[3:0] LN0 RX impedance selection */ +#define EFUSE_LN_RX_SEL GENMASK(3, 0) +#define EFUSE_LN_RX_VAL(x) (0xf & (x)) + +/* PEXTP_ANA_LN_TX_RG[5:2] LN0 TX PMOS impedance selection */ +#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2) +#define EFUSE_LN_TX_PMOS_VAL(x) ((0xf & (x)) << 2) + +/* PEXTP_ANA_LN_TX_RG[11:8] LN0 TX NMOS impedance selection */ +#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8) +#define EFUSE_LN_TX_NMOS_VAL(x) ((0xf & (x)) << 8) + +struct mtk_pcie_phy { + struct device *dev; + struct phy *phy; + void __iomem *sif_base; +}; + +static int mtk_pcie_phy_init(struct phy *phy) +{ + struct mtk_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + struct device *dev =3D pcie_phy->dev; + bool nvmem_enabled; + u32 glb_intr, tx_pmos, tx_nmos, rx_data; + int ret; + + nvmem_enabled =3D device_property_read_bool(dev, "nvmem-cells"); + if (!nvmem_enabled) + return 0; + + /* Set efuse value for lane0 */ + ret =3D nvmem_cell_read_variable_le_u32(dev, "tx_ln0_pmos", &tx_pmos); + if (ret) { + dev_err(dev, "%s: Failed to read tx_ln0_pmos\n", __func__); + return ret; + } + + ret =3D nvmem_cell_read_variable_le_u32(dev, "tx_ln0_nmos", &tx_nmos); + if (ret) { + dev_err(dev, "%s: Failed to read tx_ln0_nmos\n", __func__); + return ret; + } + + ret =3D nvmem_cell_read_variable_le_u32(dev, "rx_ln0", &rx_data); + if (ret) { + dev_err(dev, "%s: Failed to read rx_ln0\n", __func__); + return ret; + } + + /* Don't wipe the old data if there is no data in efuse cell */ + if (!(tx_pmos || tx_nmos || rx_data)) { + dev_warn(dev, "%s: No efuse data found, but dts enable it\n", + __func__); + return 0; + } + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN0_TX_REG, + EFUSE_LN_TX_PMOS_SEL, + EFUSE_LN_TX_PMOS_VAL(tx_pmos)); + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN0_TX_REG, + EFUSE_LN_TX_NMOS_SEL, + EFUSE_LN_TX_NMOS_VAL(tx_nmos)); + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN0_RX_REG, + EFUSE_LN_RX_SEL, EFUSE_LN_RX_VAL(rx_data)); + + /* Set global data */ + ret =3D nvmem_cell_read_variable_le_u32(dev, "glb_intr", &glb_intr); + if (ret) { + dev_err(dev, "%s: Failed to read glb_intr\n", __func__); + return ret; + } + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, + EFUSE_GLB_INTR_SEL, EFUSE_GLB_INTR_VAL(glb_intr)); + + /* + * Set efuse value for lane1, only available for the platform which + * supports two lane. + */ + ret =3D nvmem_cell_read_variable_le_u32(dev, "tx_ln1_pmos", &tx_pmos); + if (ret) { + dev_err(dev, "%s: Failed to read tx_ln1_pmos, efuse value not support fo= r lane 1\n", + __func__); + return 0; + } + + ret =3D nvmem_cell_read_variable_le_u32(dev, "tx_ln1_nmos", &tx_nmos); + if (ret) { + dev_err(dev, "%s: Failed to read tx_ln1_pmos\n", __func__); + return ret; + } + + ret =3D nvmem_cell_read_variable_le_u32(dev, "rx_ln1", &rx_data); + if (ret) { + dev_err(dev, "%s: Failed to read rx_ln1\n", __func__); + return ret; + } + + if (!(tx_pmos || tx_nmos || rx_data)) + return 0; + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN1_TX_REG, + EFUSE_LN_TX_PMOS_SEL, + EFUSE_LN_TX_PMOS_VAL(tx_pmos)); + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN1_TX_REG, + EFUSE_LN_TX_NMOS_SEL, + EFUSE_LN_TX_NMOS_VAL(tx_nmos)); + + mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_LN1_RX_REG, + EFUSE_LN_RX_SEL, EFUSE_LN_RX_VAL(rx_data)); + + return 0; +} + +static const struct phy_ops mtk_pcie_phy_ops =3D { + .init =3D mtk_pcie_phy_init, + .owner =3D THIS_MODULE, +}; + +static int mtk_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct phy_provider *provider; + struct mtk_pcie_phy *pcie_phy; + + pcie_phy =3D devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); + if (!pcie_phy) + return -ENOMEM; + + pcie_phy->dev =3D dev; + + pcie_phy->sif_base =3D devm_platform_ioremap_resource_byname(pdev, "sif"); + if (IS_ERR(pcie_phy->sif_base)) { + dev_err(dev, "%s: Failed to map phy-sif base\n", __func__); + return PTR_ERR(pcie_phy->sif_base); + } + + pcie_phy->phy =3D devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops); + if (IS_ERR(pcie_phy->phy)) { + dev_err(dev, "%s: Failed to create PCIe phy\n", __func__); + return PTR_ERR(pcie_phy->phy); + } + + phy_set_drvdata(pcie_phy->phy, pcie_phy); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id mtk_pcie_phy_of_match[] =3D { + { .compatible =3D "mediatek,pcie-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match); + +static struct platform_driver mtk_pcie_phy_driver =3D { + .probe =3D mtk_pcie_phy_probe, + .driver =3D { + .name =3D "mtk-pcie-phy", + .of_match_table =3D mtk_pcie_phy_of_match, + }, +}; +module_platform_driver(mtk_pcie_phy_driver); + +MODULE_DESCRIPTION("MediaTek PCIe PHY driver"); +MODULE_AUTHOR("Jianjun Wang "); +MODULE_LICENSE("GPL v2"); --=20 2.18.0 From nobody Sun Sep 22 07:30:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B986C433F5 for ; Fri, 11 Mar 2022 13:35:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348942AbiCKNgy (ORCPT ); Fri, 11 Mar 2022 08:36:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348929AbiCKNgt (ORCPT ); Fri, 11 Mar 2022 08:36:49 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64D8F1B71A7; Fri, 11 Mar 2022 05:35:41 -0800 (PST) X-UUID: d736edb4ef314125a9b867d32331608a-20220311 X-UUID: d736edb4ef314125a9b867d32331608a-20220311 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 442944019; Fri, 11 Mar 2022 21:35:34 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 11 Mar 2022 21:35:33 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 21:35:33 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 21:35:32 +0800 From: Jianjun Wang To: Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger CC: Jianjun Wang , , , , , , , , , , , Subject: [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Date: Fri, 11 Mar 2022 21:35:27 +0800 Message-ID: <20220311133527.5914-3-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311133527.5914-1-jianjun.wang@mediatek.com> References: <20220311133527.5914-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang --- .../bindings/phy/mediatek,pcie-phy.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy= .yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b= /Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..da15b4bf3117 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY Device Tree Binding + +maintainers: + - Jianjun Wang + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 7 + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + pciephy: phy@11e80000 { + compatible =3D "mediatek,pcie-phy"; + #phy-cells =3D <0>; + reg =3D <0x11e80000 0x10000>; + reg-names =3D "sif"; + nvmem-cells =3D <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names =3D "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + }; --=20 2.18.0