From nobody Sun Sep 22 09:39:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D116C433F5 for ; Fri, 11 Mar 2022 13:08:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348796AbiCKNJI (ORCPT ); Fri, 11 Mar 2022 08:09:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348764AbiCKNIw (ORCPT ); Fri, 11 Mar 2022 08:08:52 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCC8A3A1AA; Fri, 11 Mar 2022 05:07:46 -0800 (PST) X-UUID: a4bad6654b6b4aa88e7967eb20d47652-20220311 X-UUID: a4bad6654b6b4aa88e7967eb20d47652-20220311 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 39198414; Fri, 11 Mar 2022 21:07:37 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Mar 2022 21:07:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 21:07:36 +0800 From: Allen-KH Cheng To: Rob Herring , Matthias Brugger , Kishon Vijay Abraham I , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile Date: Fri, 11 Mar 2022 21:07:32 +0800 Message-ID: <20220311130732.22706-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220311130732.22706-1-allen-kh.cheng@mediatek.com> References: <20220311130732.22706-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Allen-KH Cheng Add basic chip support for Mediatek MT8186. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++ 3 files changed, 381 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 8c1e18032f9f..d32fdcf9afc6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-kodama-sku3= 2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000000..eb23d1f19f87 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" + +/ { + model =3D "MediaTek MT8186 evaluation board"; + compatible =3D "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + memory { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi new file mode 100644 index 000000000000..aa45c75b18c7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng + */ +/dts-v1/; + +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8186"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clk13m: oscillator0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <13000000>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk32k: oscillator2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + clock-output-names =3D "clk32k"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@000 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0000>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0100>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0200>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0300>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0400>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55", "arm,armv8"; + reg =3D <0x0500>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + cpu-idle-states =3D <&cpuoff_l &clusteroff_l>; + next-level-cache =3D <&l2_0>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a75", "arm,armv8"; + reg =3D <0x0600>; + enable-method =3D "psci"; + clock-frequency =3D <2050000000>; + cpu-idle-states =3D <&cpuoff_b &clusteroff_b>; + next-level-cache =3D <&l2_1>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a75", "arm,armv8"; + reg =3D <0x0700>; + enable-method =3D "psci"; + clock-frequency =3D <2050000000>; + cpu-idle-states =3D <&cpuoff_b &clusteroff_b>; + next-level-cache =3D <&l2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "arm,psci"; + + cpuoff_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <100>; + min-residency-us =3D <1600>; + }; + + cpuoff_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010001>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <100>; + min-residency-us =3D <1400>; + }; + + clusteroff_l: cluster-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <100>; + exit-latency-us =3D <250>; + min-residency-us =3D <2100>; + }; + + clusteroff_b: cluster-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010001>; + local-timer-stop; + entry-latency-us =3D <100>; + exit-latency-us =3D <250>; + min-residency-us =3D <1900>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + next-level-cache =3D <&l3_0>; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + clock-frequency =3D <13000000>; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #redistributor-regions =3D <1>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x40000>, // distributor + <0 0x0c040000 0 0x200000>; // redistributor + interrupts =3D ; + }; + + watchdog: watchdog@10007000 { + compatible =3D "mediatek,mt8186-wdt", + "mediatek,mt6589-wdt"; + mediatek,disable-extrst; + reg =3D <0 0x10007000 0 0x1000>; + #reset-cells =3D <1>; + }; + + systimer: timer@10017000 { + compatible =3D "mediatek,mt8186-timer", + "mediatek,mt6765-timer"; + reg =3D <0 0x10017000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk13m>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "baud", "bus"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart2: serial@11018000 { + compatible =3D "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg =3D <0 0x11018000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>, <&clk26m>, + <&clk26m>; + clock-names =3D "source", "hclk", "source_cg", "ahb_clk"; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>, <&clk26m>; + clock-names =3D "source", "hclk", "source_cg"; + status =3D "disabled"; + }; + + u3phy0: t-phy@11c80000 { + compatible =3D "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11c80000 0x1000>; + + u2port1: usb2-phy1@0 { + reg =3D <0x0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + + u3port1: usb3-phy1@700 { + reg =3D <0x700 0x900>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + + u3phy1: t-phy@11ca0000 { + compatible =3D "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11ca0000 0x1000>; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + mediatek,discth =3D <0x8>; + }; + }; + }; +}; --=20 2.18.0