From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FA40C433F5 for ; Fri, 11 Mar 2022 10:22:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347850AbiCKKXs (ORCPT ); Fri, 11 Mar 2022 05:23:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347820AbiCKKXj (ORCPT ); Fri, 11 Mar 2022 05:23:39 -0500 X-Greylist: delayed 64 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 11 Mar 2022 02:22:34 PST Received: from esa12.hc1455-7.c3s2.iphmx.com (esa12.hc1455-7.c3s2.iphmx.com [139.138.37.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C95E6B5D for ; Fri, 11 Mar 2022 02:22:34 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="45621046" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="45621046" Received: from unknown (HELO yto-r2.gw.nic.fujitsu.com) ([218.44.52.218]) by esa12.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:27 +0900 Received: from yto-m2.gw.nic.fujitsu.com (yto-nat-yto-m2.gw.nic.fujitsu.com [192.168.83.65]) by yto-r2.gw.nic.fujitsu.com (Postfix) with ESMTP id D0011C68A4 for ; Fri, 11 Mar 2022 19:21:26 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by yto-m2.gw.nic.fujitsu.com (Postfix) with ESMTP id 08F8AF36ED for ; Fri, 11 Mar 2022 19:21:26 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id BA77A406139C9; Fri, 11 Mar 2022 19:21:25 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 1/8] drivers: base: Add hardware prefetch control core driver Date: Fri, 11 Mar 2022 19:19:33 +0900 Message-Id: <20220311101940.3403607-2-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver adds the register/unregister function to create the "prefetch_control" directory and some attribute files in every CPU's cache/index[0,2] directory. Each attribute file exists depending on kind of processor and cache level. For example, on an INTEL_FAM6_BROADWELL_X: /sys/devices/system/cpu/cpu0/cache/index0/prefetch_control hardware_prefetcher_enable ip_prefetcher_enable /sys/devices/system/cpu/cpu0/cache/index2/prefetch_control adjacent_cache_line_prefetcher_enable hardware_prefetcher_enable If the architecture has control of the CPU's hardware prefetcher behavior, use this function to create sysfs. When registering, it is necessary to provide what type of hardware prefetcher is supported and how to read/write to the register. Following patches add support for ARM64 and x86. Signed-off-by: Kohei Tarumizu --- drivers/base/pfctl.c | 412 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pfctl.h | 41 +++++ 2 files changed, 453 insertions(+) create mode 100644 drivers/base/pfctl.c create mode 100644 include/linux/pfctl.h diff --git a/drivers/base/pfctl.c b/drivers/base/pfctl.c new file mode 100644 index 000000000000..9335d513f55f --- /dev/null +++ b/drivers/base/pfctl.c @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 FUJITSU LIMITED + * + * This driver provides tunable sysfs interface for Hardware Prefetch Cont= rol. + * See Documentation/ABI/testing/sysfs-devices-system-cpu for more informa= tion. + * + * This code provides architecture-independent functions such as create and + * remove attribute file. + * The implementation of reads and writes to the Hardware Prefetch Control + * register is architecture-dependent. Therefore, each architecture regist= er + * a callback to read and write the register via pfctl_register_driver(). + */ + +#include +#include +#include +#include +#include +#include + +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +static DEFINE_PER_CPU(struct device *, cache_device_pcpu); +#define per_cpu_cache_device(cpu) (per_cpu(cache_device_pcpu, cpu)) + +struct pfctl_driver *pdriver; +enum cpuhp_state hp_online; + +static const char dist_auto_string[] =3D "auto"; + +static bool prefetcher_is_available(unsigned int level, enum cache_type ty= pe, + int prefetcher) +{ + if ((level =3D=3D 1) && (type =3D=3D CACHE_TYPE_DATA)) { + if (pdriver->supported_l1d_prefetcher & prefetcher) + return true; + } else if ((level =3D=3D 2) && (type =3D=3D CACHE_TYPE_UNIFIED)) { + if (pdriver->supported_l2_prefetcher & prefetcher) + return true; + } + + return false; +} + +#define pfctl_enable_show(prefetcher, pattr) \ +static ssize_t \ +prefetcher##_enable_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + int ret; \ + u64 val; \ + unsigned int cpu; \ + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); \ + \ + cpu =3D dev->parent->parent->parent->id; \ + \ + ret =3D pdriver->read_pfreg(pattr, cpu, this_leaf->level, &val); \ + if (ret < 0) \ + return ret; \ + \ + if ((val =3D=3D PFCTL_ENABLE_VAL) || (val =3D=3D PFCTL_DISABLE_VAL)) \ + return sysfs_emit(buf, "%llu\n", val); \ + else \ + return -EINVAL; \ +} + +pfctl_enable_show(hardware_prefetcher, HWPF_ENABLE); +pfctl_enable_show(ip_prefetcher, IPPF_ENABLE); +pfctl_enable_show(adjacent_cache_line_prefetcher, ACLPF_ENABLE); +pfctl_enable_show(stream_detect_prefetcher, SDPF_ENABLE); + +static ssize_t +stream_detect_prefetcher_strong_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + u64 val; + unsigned int cpu; + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); + + cpu =3D dev->parent->parent->parent->id; + + ret =3D pdriver->read_pfreg(SDPF_STRONG, cpu, this_leaf->level, &val); + if (ret < 0) + return ret; + + if ((val =3D=3D PFCTL_STRONG_VAL) || (val =3D=3D PFCTL_WEAK_VAL)) + return sysfs_emit(buf, "%llu\n", val); + else + return -EINVAL; + +} + +static ssize_t +stream_detect_prefetcher_dist_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + u64 val; + unsigned int cpu; + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); + + cpu =3D dev->parent->parent->parent->id; + + ret =3D pdriver->read_pfreg(SDPF_DIST, cpu, this_leaf->level, &val); + if (ret < 0) + return ret; + + if (val =3D=3D PFCTL_DIST_AUTO_VAL) + return sysfs_emit(buf, "%s\n", dist_auto_string); + else + return sysfs_emit(buf, "%llu\n", val); +} + +#define pfctl_enable_store(prefetcher, pattr) \ +static ssize_t \ +prefetcher##_enable_store(struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, size_t count) \ +{ \ + int ret; \ + u64 val; \ + unsigned int cpu; \ + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); \ + \ + ret =3D kstrtoull(buf, 10, &val); \ + if (ret < 0) \ + return -EINVAL; \ + \ + if ((val !=3D PFCTL_ENABLE_VAL) && (val !=3D PFCTL_DISABLE_VAL)) \ + return -EINVAL; \ + \ + cpu =3D dev->parent->parent->parent->id; \ + \ + ret =3D pdriver->write_pfreg(pattr, cpu, this_leaf->level, val); \ + if (ret < 0) \ + return ret; \ + \ + return count; \ +} + +pfctl_enable_store(hardware_prefetcher, HWPF_ENABLE); +pfctl_enable_store(ip_prefetcher, IPPF_ENABLE); +pfctl_enable_store(adjacent_cache_line_prefetcher, ACLPF_ENABLE); +pfctl_enable_store(stream_detect_prefetcher, SDPF_ENABLE); + +static ssize_t +stream_detect_prefetcher_strong_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + u64 val; + unsigned int cpu; + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); + + ret =3D kstrtoull(buf, 10, &val); + if (ret < 0) + return -EINVAL; + + if ((val !=3D PFCTL_STRONG_VAL) && (val !=3D PFCTL_WEAK_VAL)) + return -EINVAL; + + cpu =3D dev->parent->parent->parent->id; + + ret =3D pdriver->write_pfreg(SDPF_STRONG, cpu, this_leaf->level, val); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t +stream_detect_prefetcher_dist_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + u64 val; + unsigned int cpu; + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); + + if (sysfs_streq(buf, dist_auto_string)) { + val =3D PFCTL_DIST_AUTO_VAL; + } else { + ret =3D kstrtoull(buf, 10, &val); + if (ret < 0) + return -EINVAL; + } + + cpu =3D dev->parent->parent->parent->id; + + ret =3D pdriver->write_pfreg(SDPF_DIST, cpu, this_leaf->level, val); + if (ret < 0) + return ret; + + return count; +} + +static DEVICE_ATTR_ADMIN_RW(hardware_prefetcher_enable); +static DEVICE_ATTR_ADMIN_RW(ip_prefetcher_enable); +static DEVICE_ATTR_ADMIN_RW(adjacent_cache_line_prefetcher_enable); +static DEVICE_ATTR_ADMIN_RW(stream_detect_prefetcher_enable); +static DEVICE_ATTR_ADMIN_RW(stream_detect_prefetcher_strong); +static DEVICE_ATTR_ADMIN_RW(stream_detect_prefetcher_dist); + +static umode_t +pfctl_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int u= nused) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct cacheinfo *this_leaf =3D dev_get_drvdata(dev->parent); + umode_t mode =3D attr->mode; + + if ((attr =3D=3D &dev_attr_hardware_prefetcher_enable.attr) && + (prefetcher_is_available(this_leaf->level, this_leaf->type, HWPF))) + return mode; + + if ((attr =3D=3D &dev_attr_ip_prefetcher_enable.attr) && + (prefetcher_is_available(this_leaf->level, this_leaf->type, IPPF))) + return mode; + + if ((attr =3D=3D &dev_attr_adjacent_cache_line_prefetcher_enable.attr) && + (prefetcher_is_available(this_leaf->level, this_leaf->type, ACLPF))) + return mode; + + if (((attr =3D=3D &dev_attr_stream_detect_prefetcher_enable.attr) || + (attr =3D=3D &dev_attr_stream_detect_prefetcher_strong.attr) || + (attr =3D=3D &dev_attr_stream_detect_prefetcher_dist.attr)) && + (prefetcher_is_available(this_leaf->level, this_leaf->type, SDPF))) + return mode; + + return 0; +} + +static struct attribute *pfctl_attrs[] =3D { + &dev_attr_hardware_prefetcher_enable.attr, + &dev_attr_ip_prefetcher_enable.attr, + &dev_attr_adjacent_cache_line_prefetcher_enable.attr, + &dev_attr_stream_detect_prefetcher_enable.attr, + &dev_attr_stream_detect_prefetcher_strong.attr, + &dev_attr_stream_detect_prefetcher_dist.attr, + NULL, +}; + +static const struct attribute_group pfctl_group =3D { + .attrs =3D pfctl_attrs, + .is_visible =3D pfctl_attrs_is_visible, +}; + +static const struct attribute_group *pfctl_groups[] =3D { + &pfctl_group, + NULL, +}; + +static int find_cache_device(unsigned int cpu) +{ + struct device *cpu_dev =3D get_cpu_device(cpu); + struct device *cache_dev; + + cache_dev =3D device_find_child_by_name(cpu_dev, "cache"); + if (!cache_dev) + return -ENODEV; + per_cpu_cache_device(cpu) =3D cache_dev; + + return 0; +} + +static int _remove_pfctl_attr(struct device *dev, void *data) +{ + struct cacheinfo *leaf =3D dev_get_drvdata(dev); + struct device *pfctl_dev; + + if (!prefetcher_is_available(leaf->level, leaf->type, ANYPF)) + return 0; + + pfctl_dev =3D device_find_child_by_name(dev, "prefetch_control"); + if (!pfctl_dev) + return 0; + + device_unregister(pfctl_dev); + return 0; +} + +static void remove_pfctl_attr(unsigned int cpu) +{ + struct device *cache_dev =3D per_cpu_cache_device(cpu); + + if (!cache_dev) + return; + + device_for_each_child(cache_dev, NULL, _remove_pfctl_attr); +} + +static int _create_pfctl_attr(struct device *dev, void *data) +{ + struct cacheinfo *leaf =3D dev_get_drvdata(dev); + struct device *pfctl_dev; + + if (!prefetcher_is_available(leaf->level, leaf->type, ANYPF)) + return 0; + + pfctl_dev =3D cpu_device_create(dev, NULL, pfctl_groups, + "prefetch_control"); + if (IS_ERR(pfctl_dev)) + return PTR_ERR(pfctl_dev); + + return 0; +} + +static int create_pfctl_attr(unsigned int cpu) +{ + int ret; + struct device *cache_dev =3D per_cpu_cache_device(cpu); + + if (!cache_dev) + return -ENODEV; + + ret =3D device_for_each_child(cache_dev, NULL, _create_pfctl_attr); + if (ret < 0) + return ret; + + return 0; +} + +static int pfctl_online(unsigned int cpu) +{ + int ret; + + ret =3D find_cache_device(cpu); + if (ret < 0) + return ret; + + ret =3D create_pfctl_attr(cpu); + if (ret < 0) + return ret; + + return 0; +} + +static int pfctl_prepare_down(unsigned int cpu) +{ + remove_pfctl_attr(cpu); + + return 0; +} + +/** + * pfctl_register_driver - register a Hardware Prefetch Control driver + * @driver_data: struct pfctl_driver must contain the supported prefetcher= type + * and function pointer for reading and writing hardware pre= fetch + * register. If these are not defined this function return e= rror. + * + * Note: This function must be called after the cache device is initialized + * because it requires access to the cache device. + * (e.g. Call at the late_initcall) + * + * Context: Any context. + * Return: 0 on success, negative error code on failure. + */ +int pfctl_register_driver(struct pfctl_driver *driver_data) +{ + int ret; + + if (pdriver) + return -EEXIST; + + if ((driver_data->supported_l1d_prefetcher =3D=3D 0) && + (driver_data->supported_l2_prefetcher =3D=3D 0)) + return -EINVAL; + + if (!driver_data->read_pfreg || !driver_data->write_pfreg) + return -EINVAL; + + pdriver =3D driver_data; + + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "base/pfctl:online", + pfctl_online, pfctl_prepare_down); + if (ret < 0) { + pr_err("failed to register hotplug callbacks\n"); + pdriver =3D NULL; + return ret; + } + + hp_online =3D ret; + + return 0; +} +EXPORT_SYMBOL_GPL(pfctl_register_driver); + +/** + * pfctl_unregister_driver - unregister the Hardware Prefetch Control driv= er + * @driver_data: Used to verify that this function is called by the driver= that + * called pfctl_register_driver by determining if driver_dat= a is + * the same. + * + * Context: Any context. + * Return: nothing. + */ +void pfctl_unregister_driver(struct pfctl_driver *driver_data) +{ + if (!pdriver || (driver_data !=3D pdriver)) + return; + + cpuhp_remove_state(hp_online); + + pdriver =3D NULL; +} +EXPORT_SYMBOL_GPL(pfctl_unregister_driver); diff --git a/include/linux/pfctl.h b/include/linux/pfctl.h new file mode 100644 index 000000000000..607442606a95 --- /dev/null +++ b/include/linux/pfctl.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_PFCTL_H +#define _LINUX_PFCTL_H + +#define PFCTL_ENABLE_VAL 1 +#define PFCTL_DISABLE_VAL 0 +#define PFCTL_STRONG_VAL 1 +#define PFCTL_WEAK_VAL 0 +#define PFCTL_DIST_AUTO_VAL 0 + +enum pfctl_attr { + HWPF_ENABLE, + IPPF_ENABLE, + ACLPF_ENABLE, + SDPF_ENABLE, + SDPF_STRONG, + SDPF_DIST, +}; + +enum prefetcher { + HWPF =3D BIT(0), /* Hardware Prefetcher */ + IPPF =3D BIT(1), /* IP Prefetcher */ + ACLPF =3D BIT(2), /* Adjacent Cache Line Prefetcher */ + SDPF =3D BIT(3), /* Stream Detect Prefetcher */ + ANYPF =3D HWPF|IPPF|ACLPF|SDPF, +}; + +struct pfctl_driver { + unsigned int supported_l1d_prefetcher; + unsigned int supported_l2_prefetcher; + + int (*read_pfreg)(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 *val); + int (*write_pfreg)(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 val); +}; + +int pfctl_register_driver(struct pfctl_driver *driver_data); +void pfctl_unregister_driver(struct pfctl_driver *driver_data); + +#endif --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8429AC433EF for ; Fri, 11 Mar 2022 10:22:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347862AbiCKKXy (ORCPT ); Fri, 11 Mar 2022 05:23:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347826AbiCKKXm (ORCPT ); Fri, 11 Mar 2022 05:23:42 -0500 Received: from esa12.hc1455-7.c3s2.iphmx.com (esa12.hc1455-7.c3s2.iphmx.com [139.138.37.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F116F219E for ; Fri, 11 Mar 2022 02:22:37 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="45621054" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="45621054" Received: from unknown (HELO yto-r2.gw.nic.fujitsu.com) ([218.44.52.218]) by esa12.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:29 +0900 Received: from yto-m4.gw.nic.fujitsu.com (yto-nat-yto-m4.gw.nic.fujitsu.com [192.168.83.67]) by yto-r2.gw.nic.fujitsu.com (Postfix) with ESMTP id 92C2CC68AA for ; Fri, 11 Mar 2022 19:21:28 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by yto-m4.gw.nic.fujitsu.com (Postfix) with ESMTP id C2D69EA177 for ; Fri, 11 Mar 2022 19:21:27 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id 89708406139C9; Fri, 11 Mar 2022 19:21:27 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 2/8] drivers: base: Add Kconfig/Makefile to build hardware prefetch control core driver Date: Fri, 11 Mar 2022 19:19:34 +0900 Message-Id: <20220311101940.3403607-3-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds Kconfig/Makefile to build hardware prefetch control core driver. This also adds a MAINTAINERS entry. Signed-off-by: Kohei Tarumizu --- MAINTAINERS | 6 ++++++ drivers/base/Kconfig | 13 +++++++++++++ drivers/base/Makefile | 1 + 3 files changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 05fd080b82f3..213537cea2e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8452,6 +8452,12 @@ F: include/linux/hwmon*.h F: include/trace/events/hwmon*.h K: (devm_)?hwmon_device_(un)?register(|_with_groups|_with_info) =20 +HARDWARE PREFETCH CONTROL DRIVERS +M: Kohei Tarumizu +S: Maintained +F: drivers/base/pfctl.c +F: include/linux/pfctl.h + HARDWARE RANDOM NUMBER GENERATOR CORE M: Matt Mackall M: Herbert Xu diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index 6f04b831a5c0..d146604b5b3a 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -230,4 +230,17 @@ config GENERIC_ARCH_NUMA Enable support for generic NUMA implementation. Currently, RISC-V and ARM64 use it. =20 +config ARCH_HAS_HWPF_CONTROL + bool + +config HWPF_CONTROL + bool "Hardware Prefetch Control driver" + depends on ARCH_HAS_HWPF_CONTROL && SYSFS + help + This driver allows user to control CPU's Hardware Prefetch behavior. + If the machine supports this behavior, it provides a sysfs interface. + + See Documentation/ABI/testing/sysfs-devices-system-cpu for more + information. + endmenu diff --git a/drivers/base/Makefile b/drivers/base/Makefile index 02f7f1358e86..13f3a0ddf3d1 100644 --- a/drivers/base/Makefile +++ b/drivers/base/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_DEV_COREDUMP) +=3D devcoredump.o obj-$(CONFIG_GENERIC_MSI_IRQ_DOMAIN) +=3D platform-msi.o obj-$(CONFIG_GENERIC_ARCH_TOPOLOGY) +=3D arch_topology.o obj-$(CONFIG_GENERIC_ARCH_NUMA) +=3D arch_numa.o +obj-$(CONFIG_HWPF_CONTROL) +=3D pfctl.o =20 obj-y +=3D test/ =20 --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57631C433EF for ; Fri, 11 Mar 2022 10:22:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347878AbiCKKX5 (ORCPT ); Fri, 11 Mar 2022 05:23:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347830AbiCKKXm (ORCPT ); Fri, 11 Mar 2022 05:23:42 -0500 Received: from esa6.hc1455-7.c3s2.iphmx.com (esa6.hc1455-7.c3s2.iphmx.com [68.232.139.139]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 089CC2644 for ; Fri, 11 Mar 2022 02:22:37 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="66313567" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="66313567" Received: from unknown (HELO oym-r3.gw.nic.fujitsu.com) ([210.162.30.91]) by esa6.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:32 +0900 Received: from oym-m1.gw.nic.fujitsu.com (oym-nat-oym-m1.gw.nic.fujitsu.com [192.168.87.58]) by oym-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 0DA90CA240 for ; Fri, 11 Mar 2022 19:21:31 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by oym-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id 262F2AB5B2 for ; Fri, 11 Mar 2022 19:21:30 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id CDFCE406139C9; Fri, 11 Mar 2022 19:21:29 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 3/8] arm64: Add hardware prefetch control support for ARM64 Date: Fri, 11 Mar 2022 19:19:35 +0900 Message-Id: <20220311101940.3403607-4-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds module init/exit code, and creates sysfs attribute files for "stream_detect_prefetcher_enable", "stream_detect_prefetcher_strong" and "stream_detect_prefetcher_dist". This driver works only if part number is FUJITSU_CPU_PART_A64FX at this point. The details of the registers to be read and written in this patch are described below. "https://github.com/fujitsu/A64FX/tree/master/doc/" A64FX_Specification_HPC_Extension_v1_EN.pdf Signed-off-by: Kohei Tarumizu --- arch/arm64/kernel/pfctl.c | 368 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 368 insertions(+) create mode 100644 arch/arm64/kernel/pfctl.c diff --git a/arch/arm64/kernel/pfctl.c b/arch/arm64/kernel/pfctl.c new file mode 100644 index 000000000000..0487c763b206 --- /dev/null +++ b/arch/arm64/kernel/pfctl.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 FUJITSU LIMITED + * + * ARM64 Hardware Prefetch Control support + */ + +#include +#include +#include +#include +#include +#include + +struct pfctl_driver arm64_pfctl_driver; + +/************************************** + * FUJITSU A64FX support + **************************************/ + +/* + * Constants for these add the "A64FX_SDPF" prefix to the name described in + * section "1.3.4.2. IMP_PF_STREAM_DETECT_CTRL_EL0" of "A64FX specificatio= n". + * (https://github.com/fujitsu/A64FX/tree/master/doc/A64FX_Specification_H= PC_Extension_v1_EN.pdf") + * See this document for register specification details. + */ +#define A64FX_SDPF_IMP_PF_STREAM_DETECT_CTRL_EL0 sys_reg(3, 3, 11, 4, 0) +#define A64FX_SDPF_V BIT_ULL(63) +#define A64FX_SDPF_L1PF_DIS BIT_ULL(59) +#define A64FX_SDPF_L2PF_DIS BIT_ULL(58) +#define A64FX_SDPF_L1W BIT_ULL(55) +#define A64FX_SDPF_L2W BIT_ULL(54) +#define A64FX_SDPF_L1_DIST GENMASK_ULL(27, 24) +#define A64FX_SDPF_L2_DIST GENMASK_ULL(19, 16) + +#define A64FX_SDPF_MIN_DIST_L1 256 +#define A64FX_SDPF_MIN_DIST_L2 1024 + +struct a64fx_read_info { + enum pfctl_attr pattr; + u64 val; + unsigned int level; + int ret; +}; + +struct a64fx_write_info { + enum pfctl_attr pattr; + u64 val; + unsigned int level; + int ret; +}; + +static int a64fx_get_sdpf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val =3D FIELD_GET(A64FX_SDPF_L1PF_DIS, reg); + break; + case 2: + val =3D FIELD_GET(A64FX_SDPF_L2PF_DIS, reg); + break; + default: + return -EINVAL; + } + + if (val =3D=3D 0) + return PFCTL_ENABLE_VAL; + else if (val =3D=3D 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int a64fx_modify_sdpf_enable(u64 *reg, unsigned int level, u64 val) +{ + if (val =3D=3D PFCTL_ENABLE_VAL) + val =3D 0; + else + val =3D 1; + + switch (level) { + case 1: + *reg &=3D ~A64FX_SDPF_L1PF_DIS; + *reg |=3D FIELD_PREP(A64FX_SDPF_L1PF_DIS, val); + break; + case 2: + *reg &=3D ~A64FX_SDPF_L2PF_DIS; + *reg |=3D FIELD_PREP(A64FX_SDPF_L2PF_DIS, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int a64fx_get_sdpf_strong(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val =3D FIELD_GET(A64FX_SDPF_L1W, reg); + break; + case 2: + val =3D FIELD_GET(A64FX_SDPF_L2W, reg); + break; + default: + return -EINVAL; + } + + if (val =3D=3D 0) + return PFCTL_STRONG_VAL; + else if (val =3D=3D 1) + return PFCTL_WEAK_VAL; + else + return -EINVAL; +} + +static int a64fx_modify_sdpf_strong(u64 *reg, unsigned int level, u64 val) +{ + if (val =3D=3D PFCTL_STRONG_VAL) + val =3D 0; + else + val =3D 1; + + switch (level) { + case 1: + *reg &=3D ~A64FX_SDPF_L1W; + *reg |=3D FIELD_PREP(A64FX_SDPF_L1W, val); + break; + case 2: + *reg &=3D ~A64FX_SDPF_L2W; + *reg |=3D FIELD_PREP(A64FX_SDPF_L2W, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int a64fx_get_sdpf_dist(u64 reg, unsigned int level) +{ + switch (level) { + case 1: + return FIELD_GET(A64FX_SDPF_L1_DIST, reg) * + A64FX_SDPF_MIN_DIST_L1; + case 2: + return FIELD_GET(A64FX_SDPF_L2_DIST, reg) * + A64FX_SDPF_MIN_DIST_L2; + default: + return -EINVAL; + } +} + +static int a64fx_modify_sdpf_dist(u64 *reg, unsigned int level, u64 val) +{ + switch (level) { + case 1: + val =3D roundup(val, A64FX_SDPF_MIN_DIST_L1) / + A64FX_SDPF_MIN_DIST_L1; + if (!FIELD_FIT(A64FX_SDPF_L1_DIST, val)) + return -EINVAL; + *reg &=3D ~A64FX_SDPF_L1_DIST; + *reg |=3D FIELD_PREP(A64FX_SDPF_L1_DIST, val); + break; + case 2: + val =3D roundup(val, A64FX_SDPF_MIN_DIST_L2) / + A64FX_SDPF_MIN_DIST_L2; + if (!FIELD_FIT(A64FX_SDPF_L2_DIST, val)) + return -EINVAL; + *reg &=3D ~A64FX_SDPF_L2_DIST; + *reg |=3D FIELD_PREP(A64FX_SDPF_L2_DIST, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void a64fx_enable_sdpf_verify(u64 *reg) +{ + *reg &=3D ~A64FX_SDPF_V; + *reg |=3D FIELD_PREP(A64FX_SDPF_V, 1); +} + +static int a64fx_get_sdpf_params(enum pfctl_attr pattr, u64 reg, + unsigned int level, u64 *val) +{ + int ret; + + switch (pattr) { + case SDPF_ENABLE: + ret =3D a64fx_get_sdpf_enable(reg, level); + break; + case SDPF_STRONG: + ret =3D a64fx_get_sdpf_strong(reg, level); + break; + case SDPF_DIST: + ret =3D a64fx_get_sdpf_dist(reg, level); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + *val =3D ret; + + return 0; +} + +static int a64fx_modify_pfreg_val(enum pfctl_attr pattr, u64 *reg, + unsigned int level, u64 val) +{ + int ret; + + switch (pattr) { + case SDPF_ENABLE: + ret =3D a64fx_modify_sdpf_enable(reg, level, val); + break; + case SDPF_STRONG: + ret =3D a64fx_modify_sdpf_strong(reg, level, val); + break; + case SDPF_DIST: + ret =3D a64fx_modify_sdpf_dist(reg, level, val); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + + a64fx_enable_sdpf_verify(reg); + + return 0; +} + +static void _a64fx_read_pfreg(void *info) +{ + u64 reg; + struct a64fx_read_info *rinfo =3D info; + + reg =3D read_sysreg_s(A64FX_SDPF_IMP_PF_STREAM_DETECT_CTRL_EL0); + + rinfo->ret =3D a64fx_get_sdpf_params(rinfo->pattr, reg, rinfo->level, + &rinfo->val); +} + +static int a64fx_read_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 *val) +{ + struct a64fx_read_info info =3D { + .level =3D level, + .pattr =3D pattr, + }; + + smp_call_function_single(cpu, _a64fx_read_pfreg, &info, true); + + if (info.ret < 0) + return info.ret; + + *val =3D info.val; + return 0; +} + +static void _a64fx_write_pfreg(void *info) +{ + int ret; + u64 reg; + struct a64fx_write_info *winfo =3D info; + + reg =3D read_sysreg_s(A64FX_SDPF_IMP_PF_STREAM_DETECT_CTRL_EL0); + + ret =3D a64fx_modify_pfreg_val(winfo->pattr, ®, winfo->level, + winfo->val); + if (ret < 0) { + winfo->ret =3D ret; + return; + } + + write_sysreg_s(reg, A64FX_SDPF_IMP_PF_STREAM_DETECT_CTRL_EL0); + + winfo->ret =3D 0; +} + +static int a64fx_write_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 val) +{ + struct a64fx_write_info info =3D { + .level =3D level, + .pattr =3D pattr, + .val =3D val, + }; + + smp_call_function_single(cpu, _a64fx_write_pfreg, &info, true); + return info.ret; +} + +/***** end of FUJITSU A64FX support *****/ + +/* + * This driver returns a negative value if it does not support the Hardware + * Prefetch Control or if it is running on a VM guest. + */ +static int __init setup_pfctl_driver_params(void) +{ + unsigned long implementor =3D read_cpuid_implementor(); + unsigned long part_number =3D read_cpuid_part_number(); + + if (!is_kernel_in_hyp_mode()) + return -EINVAL; + + switch (implementor) { + case ARM_CPU_IMP_FUJITSU: + switch (part_number) { + case FUJITSU_CPU_PART_A64FX: + /* A64FX register requires EL2 access */ + if (!has_vhe()) + return -EINVAL; + + arm64_pfctl_driver.supported_l1d_prefetcher =3D SDPF; + arm64_pfctl_driver.supported_l2_prefetcher =3D SDPF; + arm64_pfctl_driver.read_pfreg =3D a64fx_read_pfreg; + arm64_pfctl_driver.write_pfreg =3D a64fx_write_pfreg; + break; + default: + return -ENODEV; + } + break; + default: + return -ENODEV; + } + + return 0; +} + +static int __init arm64_pfctl_init(void) +{ + int ret; + + ret =3D setup_pfctl_driver_params(); + if (ret < 0) + return ret; + + ret =3D pfctl_register_driver(&arm64_pfctl_driver); + if (ret < 0) + return ret; + + return 0; +} + +static void __exit arm64_pfctl_exit(void) +{ + pfctl_unregister_driver(&arm64_pfctl_driver); +} + +late_initcall(arm64_pfctl_init); +module_exit(arm64_pfctl_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("FUJITSU LIMITED"); +MODULE_DESCRIPTION("ARM64 Hardware Prefetch Control Driver"); --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68A0CC433F5 for ; Fri, 11 Mar 2022 10:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242417AbiCKKYB (ORCPT ); Fri, 11 Mar 2022 05:24:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347835AbiCKKXo (ORCPT ); Fri, 11 Mar 2022 05:23:44 -0500 X-Greylist: delayed 64 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 11 Mar 2022 02:22:40 PST Received: from esa11.hc1455-7.c3s2.iphmx.com (esa11.hc1455-7.c3s2.iphmx.com [207.54.90.137]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CC965F5B for ; Fri, 11 Mar 2022 02:22:38 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="45468770" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="45468770" Received: from unknown (HELO yto-r4.gw.nic.fujitsu.com) ([218.44.52.220]) by esa11.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:33 +0900 Received: from yto-m4.gw.nic.fujitsu.com (yto-nat-yto-m4.gw.nic.fujitsu.com [192.168.83.67]) by yto-r4.gw.nic.fujitsu.com (Postfix) with ESMTP id 99104E05CC for ; Fri, 11 Mar 2022 19:21:32 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by yto-m4.gw.nic.fujitsu.com (Postfix) with ESMTP id BFDBFEA177 for ; Fri, 11 Mar 2022 19:21:31 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id 7FA0F406139C9; Fri, 11 Mar 2022 19:21:31 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 4/8] arm64: Add Kconfig/Makefile to build hardware prefetch control driver Date: Fri, 11 Mar 2022 19:19:36 +0900 Message-Id: <20220311101940.3403607-5-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds Kconfig/Makefile to build hardware prefetch control driver for arm64 support. This also adds a MAINTAINERS entry. Signed-off-by: Kohei Tarumizu --- MAINTAINERS | 1 + arch/arm64/Kconfig | 7 +++++++ arch/arm64/kernel/Makefile | 1 + 3 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 213537cea2e2..7eb530f5b301 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8455,6 +8455,7 @@ K: (devm_)?hwmon_device_(un)?register(|_with_groups|_= with_info) HARDWARE PREFETCH CONTROL DRIVERS M: Kohei Tarumizu S: Maintained +F: arch/arm64/kernel/pfctl.c F: drivers/base/pfctl.c F: include/linux/pfctl.h =20 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 09b885cc4db5..da6bf7e75df6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -36,6 +36,7 @@ config ARM64 select ARCH_HAS_SET_DIRECT_MAP select ARCH_HAS_SET_MEMORY select ARCH_STACKWALK + select ARCH_HAS_HWPF_CONTROL select ARCH_HAS_STRICT_KERNEL_RWX select ARCH_HAS_STRICT_MODULE_RWX select ARCH_HAS_SYNC_DMA_FOR_DEVICE @@ -2027,6 +2028,12 @@ config STACKPROTECTOR_PER_TASK def_bool y depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG =20 +config ARM64_HWPF_CONTROL + tristate "ARM64 Hardware Prefetch Control support" + depends on HWPF_CONTROL + help + This adds Hardware Prefetch driver control support for ARM64. + endmenu =20 menu "Boot options" diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 88b3e2a21408..d5eb1dc6bfa6 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_ARM64_PTR_AUTH) +=3D pointer_auth.o obj-$(CONFIG_ARM64_MTE) +=3D mte.o obj-y +=3D vdso-wrap.o obj-$(CONFIG_COMPAT_VDSO) +=3D vdso32-wrap.o +obj-$(CONFIG_ARM64_HWPF_CONTROL) +=3D pfctl.o =20 obj-y +=3D probes/ head-y :=3D head.o --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 376B3C433F5 for ; Fri, 11 Mar 2022 10:23:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347882AbiCKKYF (ORCPT ); Fri, 11 Mar 2022 05:24:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347845AbiCKKXp (ORCPT ); Fri, 11 Mar 2022 05:23:45 -0500 Received: from esa12.hc1455-7.c3s2.iphmx.com (esa12.hc1455-7.c3s2.iphmx.com [139.138.37.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9D5C25E3 for ; Fri, 11 Mar 2022 02:22:40 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="45621061" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="45621061" Received: from unknown (HELO yto-r4.gw.nic.fujitsu.com) ([218.44.52.220]) by esa12.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:35 +0900 Received: from yto-m2.gw.nic.fujitsu.com (yto-nat-yto-m2.gw.nic.fujitsu.com [192.168.83.65]) by yto-r4.gw.nic.fujitsu.com (Postfix) with ESMTP id 0D870E05CA for ; Fri, 11 Mar 2022 19:21:35 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by yto-m2.gw.nic.fujitsu.com (Postfix) with ESMTP id E3BF8FD120 for ; Fri, 11 Mar 2022 19:21:33 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id AA667406139C9; Fri, 11 Mar 2022 19:21:33 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 5/8] arm64: Create cache sysfs directory without ACPI PPTT for hardware prefetch control Date: Fri, 11 Mar 2022 19:19:37 +0900 Message-Id: <20220311101940.3403607-6-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch create a cache sysfs directory without ACPI PPTT if the CONFIG_HWPF_CONTROL is true. Hardware prefetch control driver need cache sysfs directory and cache level/type information. In ARM processor, these information can be obtained from the register even without PPTT. Therefore, we set the cpu_map_populated to true to create cache sysfs directory if the machine doesn't have PPTT. Signed-off-by: Kohei Tarumizu --- arch/arm64/kernel/cacheinfo.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 587543c6c51c..039ec32d0b3d 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -43,6 +43,21 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type =3D type; } =20 +#if defined(CONFIG_HWPF_CONTROL) +static bool acpi_has_pptt(void) +{ + struct acpi_table_header *table; + acpi_status status; + + status =3D acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) + return false; + + acpi_put_table(table); + return true; +} +#endif + int init_cache_level(unsigned int cpu) { unsigned int ctype, level, leaves, fw_level; @@ -95,5 +110,19 @@ int populate_cache_leaves(unsigned int cpu) ci_leaf_init(this_leaf++, type, level); } } + +#if defined(CONFIG_HWPF_CONTROL) + /* + * Hardware prefetch functions need cache sysfs directory and cache + * level/type information. In ARM processor, these information can be + * obtained from registers even without PPTT. Therefore, we set the + * cpu_map_populated to true to create cache sysfs directory, if the + * machine doesn't have PPTT. + **/ + if (!acpi_disabled) + if (!acpi_has_pptt()) + this_cpu_ci->cpu_map_populated =3D true; +#endif + return 0; } --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B7DEC433F5 for ; Fri, 11 Mar 2022 10:23:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347922AbiCKKYN (ORCPT ); Fri, 11 Mar 2022 05:24:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347834AbiCKKXt (ORCPT ); Fri, 11 Mar 2022 05:23:49 -0500 Received: from esa11.hc1455-7.c3s2.iphmx.com (esa11.hc1455-7.c3s2.iphmx.com [207.54.90.137]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D93E4140B2 for ; Fri, 11 Mar 2022 02:22:41 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="45468777" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="45468777" Received: from unknown (HELO yto-r3.gw.nic.fujitsu.com) ([218.44.52.219]) by esa11.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:37 +0900 Received: from yto-m1.gw.nic.fujitsu.com (yto-nat-yto-m1.gw.nic.fujitsu.com [192.168.83.64]) by yto-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id B0B6AE3E10 for ; Fri, 11 Mar 2022 19:21:36 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by yto-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id D43DBD05E2 for ; Fri, 11 Mar 2022 19:21:35 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id 92C76406139C9; Fri, 11 Mar 2022 19:21:35 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 6/8] x86: Add hardware prefetch control support for x86 Date: Fri, 11 Mar 2022 19:19:38 +0900 Message-Id: <20220311101940.3403607-7-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds module init/exit code, and creates sysfs attribute file "hardware_prefetcher_enable", "ip_prefetcher_enable" and "adjacent_cache_line_prefetcher_enable" for x86. This driver works only if the model is INTEL_FAM6_BROADWELL_X at this point. If you would like to support a new model with the same register specifications as INTEL_FAM6_BROADWELL_X, it is possible to add the model settings to array of broadwell_cpu_ids[]. The details of the registers to be read and written in this patch are described below: "https://www.intel.com/content/www/us/en/developer/articles/technical/intel= -sdm.html" Volume 4 Signed-off-by: Kohei Tarumizu --- arch/x86/kernel/cpu/pfctl.c | 314 ++++++++++++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) create mode 100644 arch/x86/kernel/cpu/pfctl.c diff --git a/arch/x86/kernel/cpu/pfctl.c b/arch/x86/kernel/cpu/pfctl.c new file mode 100644 index 000000000000..be2dce644808 --- /dev/null +++ b/arch/x86/kernel/cpu/pfctl.c @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 FUJITSU LIMITED + * + * x86 Hardware Prefetch Control support + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct pfctl_driver x86_pfctl_driver; + +/************************************** + * Intle BROADWELL support + **************************************/ + +/* + * The register specification for each bits of Intel BROADWELL is as + * follow: + * + * [0] L2 Hardware Prefetcher Disable (R/W) + * [1] L2 Adjacent Cache Line Prefetcher Disable (R/W) + * [2] DCU Hardware Prefetcher Disable (R/W) + * [3] DCU IP Prefetcher Disable (R/W) + * [63:4] Reserved + * + * See "Intel 64 and IA-32 Architectures Software Developer's Manual" + * (https://www.intel.com/content/www/us/en/developer/articles/technical/i= ntel-sdm.html) + * for register specification details. + */ +#define BROADWELL_L2_HWPF_FIELD BIT_ULL(0) +#define BROADWELL_L2_ACLPF_FIELD BIT_ULL(1) +#define BROADWELL_DCU_HWPF_FIELD BIT_ULL(2) +#define BROADWELL_DCU_IPPF_FIELD BIT_ULL(3) + +static int broadwell_get_hwpf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val =3D FIELD_GET(BROADWELL_DCU_HWPF_FIELD, reg); + break; + case 2: + val =3D FIELD_GET(BROADWELL_L2_HWPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val =3D=3D 0) + return PFCTL_ENABLE_VAL; + else if (val =3D=3D 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_hwpf_enable(u64 *reg, unsigned int level, u64 = val) +{ + if (val =3D=3D PFCTL_ENABLE_VAL) + val =3D 0; + else + val =3D 1; + + switch (level) { + case 1: + *reg &=3D ~BROADWELL_DCU_HWPF_FIELD; + *reg |=3D FIELD_PREP(BROADWELL_DCU_HWPF_FIELD, val); + break; + case 2: + *reg &=3D ~BROADWELL_L2_HWPF_FIELD; + *reg |=3D FIELD_PREP(BROADWELL_L2_HWPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_ippf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 1: + val =3D FIELD_GET(BROADWELL_DCU_IPPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val =3D=3D 0) + return PFCTL_ENABLE_VAL; + else if (val =3D=3D 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_ippf_enable(u64 *reg, unsigned int level, u64 = val) +{ + if (val =3D=3D PFCTL_ENABLE_VAL) + val =3D 0; + else + val =3D 1; + + switch (level) { + case 1: + *reg &=3D ~BROADWELL_DCU_IPPF_FIELD; + *reg |=3D FIELD_PREP(BROADWELL_DCU_IPPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_aclpf_enable(u64 reg, unsigned int level) +{ + u64 val; + + switch (level) { + case 2: + val =3D FIELD_GET(BROADWELL_L2_ACLPF_FIELD, reg); + break; + default: + return -EINVAL; + } + + if (val =3D=3D 0) + return PFCTL_ENABLE_VAL; + else if (val =3D=3D 1) + return PFCTL_DISABLE_VAL; + else + return -EINVAL; +} + +static int broadwell_modify_aclpf_enable(u64 *reg, unsigned int level, u64= val) +{ + if (val =3D=3D PFCTL_ENABLE_VAL) + val =3D 0; + else + val =3D 1; + + switch (level) { + case 2: + *reg &=3D ~BROADWELL_L2_ACLPF_FIELD; + *reg |=3D FIELD_PREP(BROADWELL_L2_ACLPF_FIELD, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int broadwell_get_pfctl_params(enum pfctl_attr pattr, u64 reg, + unsigned int level, u64 *val) +{ + int ret; + + switch (pattr) { + case HWPF_ENABLE: + ret =3D broadwell_get_hwpf_enable(reg, level); + break; + case IPPF_ENABLE: + ret =3D broadwell_get_ippf_enable(reg, level); + break; + case ACLPF_ENABLE: + ret =3D broadwell_get_aclpf_enable(reg, level); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + *val =3D ret; + + return 0; +} + +static int broadwell_modify_pfreg(enum pfctl_attr pattr, u64 *reg, + unsigned int level, u64 val) +{ + int ret; + + switch (pattr) { + case HWPF_ENABLE: + ret =3D broadwell_modify_hwpf_enable(reg, level, val); + break; + case IPPF_ENABLE: + ret =3D broadwell_modify_ippf_enable(reg, level, val); + break; + case ACLPF_ENABLE: + ret =3D broadwell_modify_aclpf_enable(reg, level, val); + break; + default: + return -ENOENT; + } + + if (ret < 0) + return ret; + + return 0; +} + +static int broadwell_read_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 *val) +{ + int ret; + u64 reg; + + ret =3D rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®); + if (ret) + return ret; + + ret =3D broadwell_get_pfctl_params(pattr, reg, level, val); + if (ret) + return ret; + + return 0; +} + +static int broadwell_write_pfreg(enum pfctl_attr pattr, unsigned int cpu, + unsigned int level, u64 val) +{ + int ret; + u64 reg; + + ret =3D rdmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, ®); + if (ret) + return ret; + + ret =3D broadwell_modify_pfreg(pattr, ®, level, val); + if (ret < 0) + return ret; + + ret =3D wrmsrl_on_cpu(cpu, MSR_MISC_FEATURE_CONTROL, reg); + if (ret) + return ret; + + return 0; +} + +/* + * In addition to BROADWELL_X, NEHALEM and others have same register + * specifications as those represented by BROADWELL_XXX_FIELD. + * If you want to add support for these processor, add the new target model + * here. + */ +static const struct x86_cpu_id broadwell_cpu_ids[] =3D { + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL), + {} +}; + +/***** end of Intel BROADWELL support *****/ + +/* + * This driver returns a negative value if it does not support the Hardware + * Prefetch Control or if it is running on a VM guest. + */ +static int __init setup_pfctl_driver_params(void) +{ + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) + return -EINVAL; + + if (x86_match_cpu(broadwell_cpu_ids)) { + x86_pfctl_driver.supported_l1d_prefetcher =3D HWPF|IPPF; + x86_pfctl_driver.supported_l2_prefetcher =3D HWPF|ACLPF; + x86_pfctl_driver.read_pfreg =3D broadwell_read_pfreg; + x86_pfctl_driver.write_pfreg =3D broadwell_write_pfreg; + } else { + return -ENODEV; + } + + return 0; +} + +static int __init x86_pfctl_init(void) +{ + int ret; + + ret =3D setup_pfctl_driver_params(); + if (ret < 0) + return ret; + + ret =3D pfctl_register_driver(&x86_pfctl_driver); + if (ret < 0) + return ret; + + return 0; +} + +static void __exit x86_pfctl_exit(void) +{ + pfctl_unregister_driver(&x86_pfctl_driver); +} + +late_initcall(x86_pfctl_init); +module_exit(x86_pfctl_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("FUJITSU LIMITED"); +MODULE_DESCRIPTION("x86 Hardware Prefetch Control Driver"); --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D210C433F5 for ; Fri, 11 Mar 2022 10:23:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347933AbiCKKYT (ORCPT ); Fri, 11 Mar 2022 05:24:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347868AbiCKKXz (ORCPT ); Fri, 11 Mar 2022 05:23:55 -0500 X-Greylist: delayed 64 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 11 Mar 2022 02:22:46 PST Received: from esa8.hc1455-7.c3s2.iphmx.com (esa8.hc1455-7.c3s2.iphmx.com [139.138.61.253]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0AC727172 for ; Fri, 11 Mar 2022 02:22:45 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="53868029" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="53868029" Received: from unknown (HELO oym-r4.gw.nic.fujitsu.com) ([210.162.30.92]) by esa8.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:39 +0900 Received: from oym-m1.gw.nic.fujitsu.com (oym-nat-oym-m1.gw.nic.fujitsu.com [192.168.87.58]) by oym-r4.gw.nic.fujitsu.com (Postfix) with ESMTP id D2427E05DE for ; Fri, 11 Mar 2022 19:21:38 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by oym-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id E3457E14DF for ; Fri, 11 Mar 2022 19:21:37 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id 997B1406139D6; Fri, 11 Mar 2022 19:21:37 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 7/8] x86: Add Kconfig/Makefile to build hardware prefetch control driver Date: Fri, 11 Mar 2022 19:19:39 +0900 Message-Id: <20220311101940.3403607-8-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds Kconfig/Makefile to build hardware prefetch control driver for x86 support. This also adds a MAINTAINERS entry. Signed-off-by: Kohei Tarumizu --- MAINTAINERS | 1 + arch/x86/Kconfig | 7 +++++++ arch/x86/kernel/cpu/Makefile | 2 ++ 3 files changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7eb530f5b301..1d2b4ba82500 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8456,6 +8456,7 @@ HARDWARE PREFETCH CONTROL DRIVERS M: Kohei Tarumizu S: Maintained F: arch/arm64/kernel/pfctl.c +F: arch/x86/kernel/pfctl. F: drivers/base/pfctl.c F: include/linux/pfctl.h =20 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9f5bd41bf660..65235d25b6f1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -26,6 +26,7 @@ config X86_64 depends on 64BIT # Options that are inherently 64-bit kernel only: select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_HWPF_CONTROL select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 select ARCH_USE_CMPXCHG_LOCKREF select HAVE_ARCH_SOFT_DIRTY @@ -1378,6 +1379,12 @@ config X86_CPUID with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to /dev/cpu/31/cpuid. =20 +config X86_HWPF_CONTROL + tristate "x86 Hardware Prefetch Control support" + depends on HWPF_CONTROL + help + This adds Hardware Prefetch driver control support for X86. + choice prompt "High Memory Support" default HIGHMEM4G diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 9661e3e802be..aec62a6b37d2 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -56,6 +56,8 @@ obj-$(CONFIG_X86_LOCAL_APIC) +=3D perfctr-watchdog.o obj-$(CONFIG_HYPERVISOR_GUEST) +=3D vmware.o hypervisor.o mshyperv.o obj-$(CONFIG_ACRN_GUEST) +=3D acrn.o =20 +obj-$(CONFIG_X86_HWPF_CONTROL) +=3D pfctl.o + ifdef CONFIG_X86_FEATURE_NAMES quiet_cmd_mkcapflags =3D MKCAP $@ cmd_mkcapflags =3D $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $= @ $^ --=20 2.27.0 From nobody Tue Jun 23 03:14:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F4D2C433EF for ; Fri, 11 Mar 2022 10:23:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347883AbiCKKYZ (ORCPT ); Fri, 11 Mar 2022 05:24:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347898AbiCKKX7 (ORCPT ); Fri, 11 Mar 2022 05:23:59 -0500 Received: from esa5.hc1455-7.c3s2.iphmx.com (esa5.hc1455-7.c3s2.iphmx.com [68.232.139.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C80A333E09 for ; Fri, 11 Mar 2022 02:22:48 -0800 (PST) X-IronPort-AV: E=McAfee;i="6200,9189,10282"; a="65516904" X-IronPort-AV: E=Sophos;i="5.90,173,1643641200"; d="scan'208";a="65516904" Received: from unknown (HELO oym-r3.gw.nic.fujitsu.com) ([210.162.30.91]) by esa5.hc1455-7.c3s2.iphmx.com with ESMTP; 11 Mar 2022 19:21:43 +0900 Received: from oym-m1.gw.nic.fujitsu.com (oym-nat-oym-m1.gw.nic.fujitsu.com [192.168.87.58]) by oym-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 4CAC2CA240 for ; Fri, 11 Mar 2022 19:21:42 +0900 (JST) Received: from yto-om1.fujitsu.com (yto-om1.o.css.fujitsu.com [10.128.89.162]) by oym-m1.gw.nic.fujitsu.com (Postfix) with ESMTP id 3B89EE14DF for ; Fri, 11 Mar 2022 19:21:41 +0900 (JST) Received: from cn-r05-10.example.com (n3235113.np.ts.nmh.cs.fujitsu.co.jp [10.123.235.113]) by yto-om1.fujitsu.com (Postfix) with ESMTP id B8745406139BF; Fri, 11 Mar 2022 19:21:40 +0900 (JST) From: Kohei Tarumizu To: catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tarumizu.kohei@fujitsu.com Subject: [PATCH v2 8/8] docs: ABI: Add sysfs documentation interface of hardware prefetch control driver Date: Fri, 11 Mar 2022 19:19:40 +0900 Message-Id: <20220311101940.3403607-9-tarumizu.kohei@fujitsu.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> References: <20220311101940.3403607-1-tarumizu.kohei@fujitsu.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This describes the sysfs interface implemented on the hardware prefetch control driver. Signed-off-by: Kohei Tarumizu --- .../ABI/testing/sysfs-devices-system-cpu | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documenta= tion/ABI/testing/sysfs-devices-system-cpu index 61f5676a7429..c1f6aa1322da 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -681,3 +681,92 @@ Description: (RO) the list of CPUs that are isolated and don't participate in load balancing. These CPUs are set by boot parameter "isolcpus=3D". + +What: /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/hardware_= prefetcher_enable + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/ip_prefet= cher_enable + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/adjacent_= cache_line_prefetcher_enable + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/stream_de= tect_prefetcher_enable + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/stream_de= tect_prefetcher_strong + /sys/devices/system/cpu/cpu*/cache/index[0,2]/prefetch_control/stream_de= tect_prefetcher_dist +Date: March 2022 +Contact: Linux kernel mailing list +Description: Parameters for CPU's hardware prefetch control + + This sysfs interface provides Hardware Prefetch control + attribute file by using implementation defined registers. + These files exists in every CPU's cache/index[0,2] directory, + and these affect the cache level of the parent index directory. + Each attribute file exists depending on kind of processor and + cache level. + + *_prefetcher_enable: + (RW) control this prefetcher's enablement state. + Read returns current status: + 0: this prefetcher is disabled + 1: this prefetcher is enabled + + stream_detect_prefetcher_strong: + (RW) control prefetcher operation's strongness state. + Strong prefetch operation is surely executed, if there is + no corresponding data in cache. + Weak prefetch operation allows the hardware not to execute + operation depending on hardware state. + + Read returns current status: + 0: prefetch operation is weak + 1: prefetch operation is strong + + stream_detect_prefetcher_dist: + (RW) control the prefetcher distance value. + Read return current prefetcher distance value in bytes + or the string "auto". + + Write either a value in byte or the string "auto" to this + parameter. If you write a value less than multiples of a + specific value, it is rounded up. + + The value 0 and the string "auto" are the same and have + a special meaning. This means that instead of setting + dist to a user-specified value, it operates using + hardware-specific values. + + - Supported processors + + This sysfs interface is available on several processors, x86 + and ARM64. Currently, the following processors are supported: + + - x86 processor + - INTEL_FAM6_BROADWELL_X + + - ARM64 processor + - FUJITSU_CPU_PART_A64FX + + - Attribute mapping + + Some Intel processors have MSR 0x1a4. This register has several + specifications depending on the model. This interface provides + a one-to-one attribute file to control all the tunable + parameters the CPU provides of the following. + + - "* Hardware Prefetcher Disable (R/W)" + corresponds to the "hardware_prefetcher_enable" + + - "* Adjacent Cache Line Prefetcher Disable (R/W)" + corresponds to the "adjacent_cache_line_prefetcher_enable" + + - "* IP Prefetcher Disable (R/W)" + corresponds to the "ip_prefetcher_enable" + + The processor A64FX has register IMP_PF_STREAM_DETECT_CTRL_EL0 + for Hardware Prefetch Control. This attribute maps each + specification to the following. + + - "L*PF_DIS": enablement of hardware prefetcher + corresponds to the "stream_detect_prefetcher_enable" + + - "L*W": strongness of hardware prefetcher + corresponds to the "stream_detect_prefetcher_strong" + + - "L*_DIST": distance of hardware prefetcher + corresponds to the "stream_detect_prefetcher_dist" --=20 2.27.0