From nobody Tue Jun 23 03:07:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E31DC433F5 for ; Fri, 11 Mar 2022 09:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347605AbiCKJjT (ORCPT ); Fri, 11 Mar 2022 04:39:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239888AbiCKJjP (ORCPT ); Fri, 11 Mar 2022 04:39:15 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03471BBE25; Fri, 11 Mar 2022 01:38:10 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id b8so7678838pjb.4; Fri, 11 Mar 2022 01:38:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+sti7R5r7TlUzIhwq2afJWAsp4Iedj4R4baq+ryUh2g=; b=UPsLXqoS5RBH3+XHcocj3dT6VT/oGbCNu4zvXSVjMWOQiIW4Zv17pEQjwbEJSmuHKq nwt/rKa9jWswtdLbCpD7380vcsbGTynIJOI+EJOU1h24OKwK9TOjMpg9t2KCq89gkedX rrzz28GkgRUXbJ8yI9rda/V2EE7WzDjn74gJiwec3XUzXqWu84Tv355++8yxsjlK8OCr slB+drV0Yvrnt1rRSJOGrEFj/+gHKsH53kXryJxw9tB1AIbdUcpyjUv0Z9hkhy0DOKEd 5pv8Y9K17lZ4i1+xAmlhZruknJN1k+vaMTTA0LNYp6VuZm+Ut3GT05DuXjkEdPPJjUZu sMbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+sti7R5r7TlUzIhwq2afJWAsp4Iedj4R4baq+ryUh2g=; b=UEFdijlLkokXLInQ46BCqFR+xJBxU6Ul5Cbb7HAk72spTVTvt8xs+BVts4MMXVnDV+ r3ymBtYnGc7GbvjGyXTDNctG5/mefkqd27ZImVOON1w7xs+LBgKYhiH1zbszGztw181V /x4JyGwEKpXZ3dnTJ+Fgpl7b1PtUQELE/+LeRWRPIxzw7Zje2nyWoSP+2gntPsObNMJq rr1PijKSec6LRBW6BEizClWdGJ3ddDx26kMhwv8GX97ZzPJDnP2ysFpv8lEaGjhk5Wrq PH+tLCpMzrtGUpuEjLbeyoRMo2a2oIvK06esPAl1O3wu6gFjCy+N0L6K8dv0X0Ac0DbW 7m2A== X-Gm-Message-State: AOAM5313nmYAICDpf+NjZIAukC8XObmO/0dM2RiaaH9BI/B4dtPn6unp XMX7yw4D5omfXNvzn3j8uTY= X-Google-Smtp-Source: ABdhPJzYRJlhVYjsiUbgyuUOuHb8yYvjyX5Y3NPJ7anc1+dPGbWZPcJPM2mEEqB5bo8jjieTu90yqg== X-Received: by 2002:a17:90b:1c86:b0:1bf:2a7e:5c75 with SMTP id oo6-20020a17090b1c8600b001bf2a7e5c75mr9954721pjb.145.1646991489547; Fri, 11 Mar 2022 01:38:09 -0800 (PST) Received: from localhost.localdomain ([122.161.53.68]) by smtp.gmail.com with ESMTPSA id m11-20020a056a00080b00b004f75d5f9b5csm9011011pfk.26.2022.03.11.01.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Mar 2022 01:38:09 -0800 (PST) From: Kuldeep Singh To: Arnd Bergmann , Olof Johansson , soc@kernel.org, Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 1/3] arm64: dts: seattle: Update spi clock properties Date: Fri, 11 Mar 2022 15:07:58 +0530 Message-Id: <20220311093800.18778-2-singh.kuldeep87k@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> References: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PL022 binding require two clocks to be defined but AMD seattle platform does't comply with binding and define only one clock i.e apb_pclk. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Tom Lendacky Signed-off-by: Kuldeep Singh Acked-by: Rob Herring --- v2: - Resend to soc ML - Add Rob's acked-by tag arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot= /dts/amd/amd-seattle-soc.dtsi index b664e7af74eb..2aa21d98d560 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -113,8 +113,8 @@ spi0: spi@e1020000 { reg =3D <0 0xe1020000 0 0x1000>; spi-controller; interrupts =3D <0 330 4>; - clocks =3D <&uartspiclk_100mhz>; - clock-names =3D "apb_pclk"; + clocks =3D <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; + clock-names =3D "sspclk", "apb_pclk"; }; =20 spi1: spi@e1030000 { @@ -123,8 +123,8 @@ spi1: spi@e1030000 { reg =3D <0 0xe1030000 0 0x1000>; spi-controller; interrupts =3D <0 329 4>; - clocks =3D <&uartspiclk_100mhz>; - clock-names =3D "apb_pclk"; + clocks =3D <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; + clock-names =3D "sspclk", "apb_pclk"; num-cs =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.25.1 From nobody Tue Jun 23 03:07:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C20C433F5 for ; Fri, 11 Mar 2022 09:38:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347649AbiCKJjY (ORCPT ); Fri, 11 Mar 2022 04:39:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347602AbiCKJjT (ORCPT ); Fri, 11 Mar 2022 04:39:19 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47A6BE0A25; Fri, 11 Mar 2022 01:38:13 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id gj15-20020a17090b108f00b001bef86c67c1so7685441pjb.3; Fri, 11 Mar 2022 01:38:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iXKoOhJsegCgBWbpQZaKhqPFw+9/pc6YzaaD+yCqeLI=; b=NsC6TSNJe603PGQnszA9PJacCMKoaSa4T+QzSVMgCch1XLq/wM0zgoP5qL9XSpBxi4 AQQV+E8zoKJfPg9NTqIAV/TCByvxBF69OxWRZx4U03ja2g14truZBU26BxBemicDq9hb 8h8iLE6rXHd4UHx24a4c3q7QzfT+6wuX1eW7Jbh0ljsVBK0MRwuEEWwC1awFCJKMAfmQ nDbSx4ni2i7Xij5u5crvpcjpFUkg1QQJW4ceV6WuGs5xbsuqP6dJPnfAinU4VrjzbP+9 yivy2AzAliFv3qvnUdv01GAn4yIFek8TW3jyIJ6aTou9YlsguJy8hR3aeabSYOolieoY BNZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iXKoOhJsegCgBWbpQZaKhqPFw+9/pc6YzaaD+yCqeLI=; b=fsImKXXZF2lGkovoDOMvgUE2cuCSvbcClhPtHmYCNVg5QOTO1WbAW0wnV6GMTuWzeM EV+ywvMwmtvxelCdB962rBv55UZXQfrOXfHZOHigl70kiJtaqjP3Shvlus+MWPjTOvCa eyf1xT3pPriGjrrEyzOx0OTwkU65ZkgkZqN+itu+EJoW3HjKYqkMC9TBgz092B3sTxAp /q3vhNS8WMcU7FPmxzWhfRSV4jnlNesvzg8F0DApvM/ZfRGHlheU5O51bSED0k8xittN oOxf7arXUtv43KMkRJKRMKCNSR9VSTqkce0gd6qWo2x+H2NfpiEl7L15IrzfyIEzH4O9 MlRw== X-Gm-Message-State: AOAM533r3OxfAixXWJMtafN+EvUna5cchnL74ISPbsEtEEzgiQGb8vBv sxqNqaGdG+kc9IdrxFic0eqrys3dNiMsgw== X-Google-Smtp-Source: ABdhPJxOwlYZb3pZsNu37/YVDoq39syQkU+41qFjqS4cko1TODNhT00GBLVx5sFkgiyJynay7J/jBg== X-Received: by 2002:a17:90a:d3d3:b0:1bf:2e8d:3175 with SMTP id d19-20020a17090ad3d300b001bf2e8d3175mr10011200pjw.2.1646991493353; Fri, 11 Mar 2022 01:38:13 -0800 (PST) Received: from localhost.localdomain ([122.161.53.68]) by smtp.gmail.com with ESMTPSA id m11-20020a056a00080b00b004f75d5f9b5csm9011011pfk.26.2022.03.11.01.38.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Mar 2022 01:38:13 -0800 (PST) From: Kuldeep Singh To: Arnd Bergmann , Olof Johansson , soc@kernel.org, Chanho Min , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/3] arm64: dts: lg131x: Update spi clock properties Date: Fri, 11 Mar 2022 15:07:59 +0530 Message-Id: <20220311093800.18778-3-singh.kuldeep87k@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> References: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PL022 binding require two clocks to be defined but LG1312 and LG1313 platforms don't comply with bindings and define only one clock. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Chanho Min Signed-off-by: Kuldeep Singh Acked-by: Rob Herring --- v2: - Resend to soc ML - Add Rob's acked-by tag arch/arm64/boot/dts/lg/lg1312.dtsi | 8 ++++---- arch/arm64/boot/dts/lg/lg1313.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg= 1312.dtsi index bec97480a960..e4de0f98c685 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -172,15 +172,15 @@ spi0: spi@fe800000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x0 0xfe800000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; }; spi1: spi@fe900000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x0 0xfe900000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; }; dmac0: dma-controller@c1128000 { compatible =3D "arm,pl330", "arm,primecell"; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg= 1313.dtsi index ada3d4dc6305..873baae75035 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -172,15 +172,15 @@ spi0: spi@fe800000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x0 0xfe800000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; }; spi1: spi@fe900000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x0 0xfe900000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; }; dmac0: dma-controller@c1128000 { compatible =3D "arm,pl330", "arm,primecell"; --=20 2.25.1 From nobody Tue Jun 23 03:07:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6862BC433F5 for ; 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Fri, 11 Mar 2022 01:38:16 -0800 (PST) From: Kuldeep Singh To: Arnd Bergmann , Olof Johansson , soc@kernel.org, Rob Herring , Vladimir Zapolskiy Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] ARM: dts: lpc32xx: Update spi clock properties Date: Fri, 11 Mar 2022 15:08:00 +0530 Message-Id: <20220311093800.18778-4-singh.kuldeep87k@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> References: <20220311093800.18778-1-singh.kuldeep87k@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PL022 binding require two clocks to be defined but lpc platform doesn't comply with bindings and define only one clock i.e apb_pclk. Update spi clocks and clocks-names property by adding appropriate clock reference to make it compliant with bindings. CC: Vladimir Zapolskiy Signed-off-by: Kuldeep Singh --- v2: - New patch with similar changeset - Send to soc ML arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c87066d6c995..30958e02d5e2 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -178,8 +178,8 @@ ssp0: spi@20084000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x20084000 0x1000>; interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk LPC32XX_CLK_SSP0>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>; + clock-names =3D "sspclk", "apb_pclk"; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -202,8 +202,8 @@ ssp1: spi@2008c000 { compatible =3D "arm,pl022", "arm,primecell"; reg =3D <0x2008c000 0x1000>; interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk LPC32XX_CLK_SSP1>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>; + clock-names =3D "sspclk", "apb_pclk"; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; --=20 2.25.1