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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:15.8008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d7f5d4a-813c-45e2-1c33-08da028764b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0106 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Kirill A. Shutemov" The interface for enabling tagged addresses is very inflexible. It implies tag size and tag shift implemented by ARM TBI. Rework the interface to accommodate different shifts and tag sizes. PR_SET_TAGGED_ADDR_CTRL now accepts two new arguments: - nr_bits is pointer to int. The caller specifies the tag size it wants. Kernel updates the value of actual tag size that can be larger. - offset is pointer to int. Kernel returns there a shift of tag in the address. The change doesn't break existing users of the interface: if any of these pointers are NULL (as we had before the change), the user expects ARM TBI implementation: nr_bits =3D=3D 8 && offset =3D=3D 56 as it was impl= ied before. The initial implementation checked that these argument are NULL and the change wouldn't not break any legacy users. If tagging is enabled, GET_TAGGED_ADDR_CTRL would return size of tags and offset in the additional arguments. If tagging is disable, GET_TAGGED_ADDR_CTRL would return the maximum tag size in nr_bits. The selftest is updated accordingly and moved out of arm64-specific directory as we going to enable the interface on x86. As alternative to this approach we could introduce a totally new API and leave the legacy one as is. But it would slow down adoption: new prctl(2) flag wound need to propogate to the userspace headers. Signed-off-by: Kirill A. Shutemov [selftests/vm/tags/tags_test.c: Set ptr tag only when tagging is enabled and a couple of checkpatch warning fixes] Signed-off-by: Bharata B Rao --- arch/arm64/include/asm/processor.h | 12 ++-- arch/arm64/kernel/process.c | 45 +++++++++++--- arch/arm64/kernel/ptrace.c | 4 +- kernel/sys.c | 14 +++-- .../testing/selftests/arm64/tags/tags_test.c | 31 ---------- .../selftests/{arm64 =3D> vm}/tags/.gitignore | 0 .../selftests/{arm64 =3D> vm}/tags/Makefile | 0 .../{arm64 =3D> vm}/tags/run_tags_test.sh | 0 tools/testing/selftests/vm/tags/tags_test.c | 59 +++++++++++++++++++ 9 files changed, 115 insertions(+), 50 deletions(-) delete mode 100644 tools/testing/selftests/arm64/tags/tags_test.c rename tools/testing/selftests/{arm64 =3D> vm}/tags/.gitignore (100%) rename tools/testing/selftests/{arm64 =3D> vm}/tags/Makefile (100%) rename tools/testing/selftests/{arm64 =3D> vm}/tags/run_tags_test.sh (100%) create mode 100644 tools/testing/selftests/vm/tags/tags_test.c diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 6f41b65f9962..c3936bebf006 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -367,10 +367,14 @@ extern void __init minsigstksz_setup(void); =20 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ -long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); -long get_tagged_addr_ctrl(struct task_struct *task); -#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) -#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long flags, + int __user *nr_bits, int __user *offset); +long get_tagged_addr_ctrl(struct task_struct *task, + int __user *nr_bits, int __user *offset); +#define SET_TAGGED_ADDR_CTRL(flags, nr_bits, offset) \ + set_tagged_addr_ctrl(current, flags, nr_bits, offset) +#define GET_TAGGED_ADDR_CTRL(nr_bits, offset) \ + get_tagged_addr_ctrl(current, nr_bits, offset) #endif =20 /* diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 5369e649fa79..fc0240f5ead0 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -621,15 +621,21 @@ void arch_setup_new_exec(void) } =20 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI + +#define TBI_TAG_BITS 8 +#define TBI_TAG_SHIFT 56 + /* * Control the relaxed ABI allowing tagged user addresses into the kernel. */ static unsigned int tagged_addr_disabled; =20 -long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long flags, + int __user *nr_bits, int __user *offset) { unsigned long valid_mask =3D PR_TAGGED_ADDR_ENABLE; struct thread_info *ti =3D task_thread_info(task); + int val; =20 if (is_compat_thread(ti)) return -EINVAL; @@ -637,25 +643,41 @@ long set_tagged_addr_ctrl(struct task_struct *task, u= nsigned long arg) if (system_supports_mte()) valid_mask |=3D PR_MTE_TCF_MASK | PR_MTE_TAG_MASK; =20 - if (arg & ~valid_mask) + if (flags & ~valid_mask) return -EINVAL; =20 + if (nr_bits) { + if (get_user(val, nr_bits)) + return -EFAULT; + if (val > TBI_TAG_BITS || val < 1) + return -EINVAL; + } + /* * Do not allow the enabling of the tagged address ABI if globally * disabled via sysctl abi.tagged_addr_disabled. */ - if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled) + if (flags & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled) return -EINVAL; =20 - if (set_mte_ctrl(task, arg) !=3D 0) + if (set_mte_ctrl(task, flags) !=3D 0) return -EINVAL; =20 - update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE); + if (flags & PR_TAGGED_ADDR_ENABLE) { + if (nr_bits && put_user(TBI_TAG_BITS, nr_bits)) + return -EFAULT; + if (offset && put_user(TBI_TAG_SHIFT, offset)) + return -EFAULT; + } + + update_ti_thread_flag(ti, TIF_TAGGED_ADDR, + flags & PR_TAGGED_ADDR_ENABLE); =20 return 0; } =20 -long get_tagged_addr_ctrl(struct task_struct *task) +long get_tagged_addr_ctrl(struct task_struct *task, + int __user *nr_bits, int __user *offset) { long ret =3D 0; struct thread_info *ti =3D task_thread_info(task); @@ -663,8 +685,17 @@ long get_tagged_addr_ctrl(struct task_struct *task) if (is_compat_thread(ti)) return -EINVAL; =20 - if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR)) + if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR)) { ret =3D PR_TAGGED_ADDR_ENABLE; + if (nr_bits && put_user(TBI_TAG_BITS, nr_bits)) + return -EFAULT; + if (offset && put_user(TBI_TAG_SHIFT, offset)) + return -EFAULT; + } else { + /* Report maximum tag size */ + if (nr_bits && put_user(TBI_TAG_BITS, nr_bits)) + return -EFAULT; + } =20 ret |=3D get_mte_ctrl(task); =20 diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 39dbdfdc38d3..471fd40f7d4e 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -1073,7 +1073,7 @@ static int tagged_addr_ctrl_get(struct task_struct *t= arget, const struct user_regset *regset, struct membuf to) { - long ctrl =3D get_tagged_addr_ctrl(target); + long ctrl =3D get_tagged_addr_ctrl(target, NULL, NULL); =20 if (IS_ERR_VALUE(ctrl)) return ctrl; @@ -1093,7 +1093,7 @@ static int tagged_addr_ctrl_set(struct task_struct *t= arget, const struct if (ret) return ret; =20 - return set_tagged_addr_ctrl(target, ctrl); + return set_tagged_addr_ctrl(target, ctrl, NULL, NULL); } #endif =20 diff --git a/kernel/sys.c b/kernel/sys.c index 97dc9e5d6bf9..3af5c5098b3c 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -126,10 +126,10 @@ # define PAC_GET_ENABLED_KEYS(a) (-EINVAL) #endif #ifndef SET_TAGGED_ADDR_CTRL -# define SET_TAGGED_ADDR_CTRL(a) (-EINVAL) +# define SET_TAGGED_ADDR_CTRL(a, b, c) (-EINVAL) #endif #ifndef GET_TAGGED_ADDR_CTRL -# define GET_TAGGED_ADDR_CTRL() (-EINVAL) +# define GET_TAGGED_ADDR_CTRL(a, b) (-EINVAL) #endif =20 /* @@ -2557,14 +2557,16 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, = arg2, unsigned long, arg3, error =3D PAC_GET_ENABLED_KEYS(me); break; case PR_SET_TAGGED_ADDR_CTRL: - if (arg3 || arg4 || arg5) + if (arg5) return -EINVAL; - error =3D SET_TAGGED_ADDR_CTRL(arg2); + error =3D SET_TAGGED_ADDR_CTRL(arg2, (int __user *)arg3, + (int __user *)arg4); break; case PR_GET_TAGGED_ADDR_CTRL: - if (arg2 || arg3 || arg4 || arg5) + if (arg4 || arg5) return -EINVAL; - error =3D GET_TAGGED_ADDR_CTRL(); + error =3D GET_TAGGED_ADDR_CTRL((int __user *)arg2, + (int __user *)arg3); break; case PR_SET_IO_FLUSHER: if (!capable(CAP_SYS_RESOURCE)) diff --git a/tools/testing/selftests/arm64/tags/tags_test.c b/tools/testing= /selftests/arm64/tags/tags_test.c deleted file mode 100644 index 5701163460ef..000000000000 --- a/tools/testing/selftests/arm64/tags/tags_test.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include -#include -#include - -#define SHIFT_TAG(tag) ((uint64_t)(tag) << 56) -#define SET_TAG(ptr, tag) (((uint64_t)(ptr) & ~SHIFT_TAG(0xff)) | \ - SHIFT_TAG(tag)) - -int main(void) -{ - static int tbi_enabled =3D 0; - unsigned long tag =3D 0; - struct utsname *ptr; - int err; - - if (prctl(PR_SET_TAGGED_ADDR_CTRL, PR_TAGGED_ADDR_ENABLE, 0, 0, 0) =3D=3D= 0) - tbi_enabled =3D 1; - ptr =3D (struct utsname *)malloc(sizeof(*ptr)); - if (tbi_enabled) - tag =3D 0x42; - ptr =3D (struct utsname *)SET_TAG(ptr, tag); - err =3D uname(ptr); - free(ptr); - - return err; -} diff --git a/tools/testing/selftests/arm64/tags/.gitignore b/tools/testing/= selftests/vm/tags/.gitignore similarity index 100% rename from tools/testing/selftests/arm64/tags/.gitignore rename to tools/testing/selftests/vm/tags/.gitignore diff --git a/tools/testing/selftests/arm64/tags/Makefile b/tools/testing/se= lftests/vm/tags/Makefile similarity index 100% rename from tools/testing/selftests/arm64/tags/Makefile rename to tools/testing/selftests/vm/tags/Makefile diff --git a/tools/testing/selftests/arm64/tags/run_tags_test.sh b/tools/te= sting/selftests/vm/tags/run_tags_test.sh similarity index 100% rename from tools/testing/selftests/arm64/tags/run_tags_test.sh rename to tools/testing/selftests/vm/tags/run_tags_test.sh diff --git a/tools/testing/selftests/vm/tags/tags_test.c b/tools/testing/se= lftests/vm/tags/tags_test.c new file mode 100644 index 000000000000..c8486b6398b1 --- /dev/null +++ b/tools/testing/selftests/vm/tags/tags_test.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include + +static int tag_bits; +static int tag_offset; + +#define SHIFT_TAG(tag) ((uint64_t)(tag) << tag_offset) +#define SET_TAG(ptr, tag) (((uint64_t)(ptr) & ~SHIFT_TAG((1 << tag_bits) -= 1)) \ + | SHIFT_TAG(tag)) + +static int max_tag_bits(void) +{ + int nr; + + if (prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0) < 0) + return 0; + + if (prctl(PR_GET_TAGGED_ADDR_CTRL, &nr, 0, 0) < 0) + return 8; /* Assume ARM TBI */ + + return nr; +} + +int main(void) +{ + static int tags_enabled; + unsigned long tag =3D 0; + struct utsname *ptr; + int err; + + tag_bits =3D max_tag_bits(); + + if (tag_bits && !prctl(PR_SET_TAGGED_ADDR_CTRL, PR_TAGGED_ADDR_ENABLE, + &tag_bits, &tag_offset, 0)) { + tags_enabled =3D 1; + } else if (tag_bits =3D=3D 8 && !prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE, 0, 0)) { + /* ARM TBI with legacy interface*/ + tags_enabled =3D 1; + tag_offset =3D 56; + } + + ptr =3D (struct utsname *)malloc(sizeof(*ptr)); + if (tags_enabled) { + tag =3D (1UL << tag_bits) - 1; + ptr =3D (struct utsname *)SET_TAG(ptr, tag); + } + err =3D uname(ptr); + printf("Sysname: %s\n", ptr->sysname); + free(ptr); + + return err; +} --=20 2.25.1 From nobody Tue Jun 23 05:05:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF4BC433EF for ; Thu, 10 Mar 2022 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241537AbiCJLRc (ORCPT ); Thu, 10 Mar 2022 06:17:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241536AbiCJLR0 (ORCPT ); Thu, 10 Mar 2022 06:17:26 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2080.outbound.protection.outlook.com [40.107.236.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC3A1141454 for ; Thu, 10 Mar 2022 03:16:24 -0800 (PST) ARC-Seal: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:21.3917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ec121ed-844a-4d92-35a0-08da0287680e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2388 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently the maximum logical address size for AMD processors in 64 bit mode is 57 bits. This means that the remaining 7 upper bits [63:57] are available for software use. With UAI feature turned ON, the processor ignores these upper bits when performing canonical check on these addresses. Add UAI as a CPU feature. Signed-off-by: Bharata B Rao --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6db4e2932b3d..5f4e88e67feb 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -201,7 +201,7 @@ #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR= 4.PCIDE=3D1 */ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface = */ -/* FREE! ( 7*32+10) */ +#define X86_FEATURE_UAI ( 7*32+10) /* AMD Upper Address Ignore */ #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enable= d */ #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigati= on for Spectre variant 2 */ #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigatio= n for Spectre variant 2 */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 21d1f062895a..5c19f6f525cf 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_UAI, CPUID_EAX, 7, 0x80000021, 0 }, { 0, 0, 0, 0, 0 } }; =20 --=20 2.25.1 From nobody Tue Jun 23 05:05:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15164C433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:26.9955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f33297ab-f11a-4c4e-e3bf-08da02876b62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2820 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UAI feature is enabled by setting bit 20 in EFER MSR. Signed-off-by: Bharata B Rao --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/setup.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index a4a39c3e0f19..ce763952278f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -30,6 +30,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_UAI 20 /* Enable Upper Address Ignore */ =20 #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) @@ -38,6 +39,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_UAI (1<<_EFER_UAI) =20 /* Intel MSRs. Some also available on other CPUs */ =20 diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index f7a132eb794d..12615b1b4af5 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -740,6 +740,12 @@ dump_kernel_offset(struct notifier_block *self, unsign= ed long v, void *p) return 0; } =20 +static inline void __init uai_enable(void) +{ + if (boot_cpu_has(X86_FEATURE_UAI)) + msr_set_bit(MSR_EFER, _EFER_UAI); +} + /* * Determine if we were loaded by an EFI loader. If so, then we have also= been * passed the efi memmap, systab, etc., so we should use these data struct= ures @@ -1146,6 +1152,8 @@ void __init setup_arch(char **cmdline_p) =20 x86_init.paging.pagetable_init(); =20 + uai_enable(); + kasan_init(); =20 /* --=20 2.25.1 From nobody Tue Jun 23 05:05:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47E32C433F5 for ; Thu, 10 Mar 2022 11:16:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241554AbiCJLRl (ORCPT ); Thu, 10 Mar 2022 06:17:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241574AbiCJLRj (ORCPT ); Thu, 10 Mar 2022 06:17:39 -0500 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2072.outbound.protection.outlook.com [40.107.212.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCE20141FC5 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:34.0035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e35e95ad-af4b-429d-3d30-08da02876f90 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0157 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" untagged_addr() will be used by core mm routines to remove the tag bits and convert the address to canonical form. Limit the implementation to AMD CPUs as Intel's version of the same is likely to be different. Signed-off-by: Bharata B Rao --- arch/x86/include/asm/page_32.h | 3 +++ arch/x86/include/asm/page_64.h | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/page_32.h b/arch/x86/include/asm/page_32.h index df42f8aa99e4..8309aa987354 100644 --- a/arch/x86/include/asm/page_32.h +++ b/arch/x86/include/asm/page_32.h @@ -30,6 +30,9 @@ static inline void copy_page(void *to, void *from) { memcpy(to, from, PAGE_SIZE); } + +#define untagged_addr(addr) (addr) +#define untagged_ptr(ptr) (ptr) #endif /* !__ASSEMBLY__ */ =20 #endif /* _ASM_X86_PAGE_32_H */ diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h index e9c86299b835..41d4a729e783 100644 --- a/arch/x86/include/asm/page_64.h +++ b/arch/x86/include/asm/page_64.h @@ -90,6 +90,32 @@ static __always_inline unsigned long task_size_max(void) } #endif /* CONFIG_X86_5LEVEL */ =20 +#ifdef CONFIG_CPU_SUP_AMD +/* + * Tag bits are in same position [63:57] for both 4 and 5 level page + * tables. For both the cases we sign-extend from 56th bit since + * bits [56:48] are anyway expected to be canonical for 4 level page table= s. + */ +#define __untagged_addr(addr) \ + ((__force __typeof__(addr))sign_extend64((__force u64)(addr), 56)) + +#define untagged_addr(addr) ({ \ + u64 __addr =3D (__force u64)(addr); \ + __addr &=3D __untagged_addr(__addr); \ + (__force __typeof__(addr))__addr; \ +}) + +#define untagged_ptr(ptr) ({ \ + u64 __ptrval =3D (__force u64)(ptr); \ + __ptrval =3D untagged_addr(__ptrval); \ + (__force __typeof__(*(ptr)) *)__ptrval; \ +}) + +#else +#define untagged_addr(addr) (addr) +#define untagged_ptr(ptr) (ptr) +#endif + #endif /* !__ASSEMBLY__ */ =20 #ifdef CONFIG_X86_VSYSCALL_EMULATION --=20 2.25.1 From nobody Tue Jun 23 05:05:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C700C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5061.22 via Frontend Transport; Thu, 10 Mar 2022 11:16:39 +0000 Received: from BLR-5CG1133937.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 10 Mar 2022 05:16:32 -0600 From: Bharata B Rao To: CC: , , , , , , , , , , , , "Bharata B Rao" Subject: [RFC PATCH v0 5/6] x86: Untag user pointers in access_ok() Date: Thu, 10 Mar 2022 16:45:44 +0530 Message-ID: <20220310111545.10852-6-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310111545.10852-1-bharata@amd.com> References: <20220310111545.10852-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1f876cfd-bbff-4382-72cf-08da028772b4 X-MS-TrafficTypeDiagnostic: BL1PR12MB5947:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:39.2740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f876cfd-bbff-4382-72cf-08da028772b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5947 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a preparatory work to allow passing of tagged user pointers (with a top few bits other than zeroes) as syscall arguments. Since user can provide tagged pointer to syscalls they need to be untagged before validating them in access_ok(). Untagging is done only if flag TIF_TAGGED_ADDR is set for the thread. This is set via prctl() option which will be introduced in a subsequent patch. get_user() and put_user() don't use access_ok(), but check access against TASK_SIZE direcly in assembly. Strip tags, before calling into the assembly helper. [kirill.shutemov@linux.intel.com - get/put_user() changes] Signed-off-by: Bharata B Rao --- arch/x86/include/asm/thread_info.h | 2 ++ arch/x86/include/asm/uaccess.h | 28 +++++++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thre= ad_info.h index ebec69c35e95..c786103a5325 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -101,6 +101,7 @@ struct thread_info { #define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */ #define TIF_LAZY_MMU_UPDATES 27 /* task is updating the mmu lazily */ #define TIF_ADDR32 29 /* 32-bit address space on 64 bits */ +#define TIF_TAGGED_ADDR 30 /* Allow tagged user addresses */ =20 #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) @@ -124,6 +125,7 @@ struct thread_info { #define _TIF_BLOCKSTEP (1 << TIF_BLOCKSTEP) #define _TIF_LAZY_MMU_UPDATES (1 << TIF_LAZY_MMU_UPDATES) #define _TIF_ADDR32 (1 << TIF_ADDR32) +#define _TIF_TAGGED_ADDR (1 << TIF_TAGGED_ADDR) =20 /* flags to check in __switch_to() */ #define _TIF_WORK_CTXSW_BASE \ diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index ac96f9b2d64b..feb2e21c7e09 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -35,11 +35,15 @@ static inline bool __chk_range_not_ok(unsigned long add= r, unsigned long size, un return unlikely(addr > limit); } =20 -#define __range_not_ok(addr, size, limit) \ -({ \ - __chk_user_ptr(addr); \ - __chk_range_not_ok((unsigned long __force)(addr), size, limit); \ -}) +static inline bool __range_not_ok(const void __user *addr, unsigned long s= ize, + unsigned long limit) +{ + if (test_thread_flag(TIF_TAGGED_ADDR)) + addr =3D untagged_addr(addr); + + __chk_user_ptr(addr); + return __chk_range_not_ok((unsigned long __force)(addr), size, limit); +} =20 #ifdef CONFIG_DEBUG_ATOMIC_SLEEP static inline bool pagefault_disabled(void); @@ -152,7 +156,12 @@ extern int __get_user_bad(void); * Return: zero on success, or -EFAULT on error. * On error, the variable @x is set to zero. */ -#define get_user(x,ptr) ({ might_fault(); do_get_user_call(get_user,x,ptr)= ; }) +#define get_user(x,ptr) \ +({ \ + __typeof__(*(ptr)) *ptr_untagged =3D untagged_ptr(ptr); \ + might_fault(); \ + do_get_user_call(get_user,x,ptr_untagged); \ +}) =20 /** * __get_user - Get a simple variable from user space, with less checking. @@ -249,7 +258,12 @@ extern void __put_user_nocheck_8(void); * * Return: zero on success, or -EFAULT on error. */ -#define put_user(x, ptr) ({ might_fault(); do_put_user_call(put_user,x,ptr= ); }) +#define put_user(x, ptr) \ +({ \ + __typeof__(*(ptr)) *ptr_untagged =3D untagged_ptr(ptr); \ + might_fault(); \ + do_put_user_call(put_user,x,ptr_untagged); \ +}) =20 /** * __put_user - Write a simple value into user space, with less checking. --=20 2.25.1 From nobody Tue Jun 23 05:05:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D50FDC433F5 for ; Thu, 10 Mar 2022 11:17:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241586AbiCJLSX (ORCPT ); Thu, 10 Mar 2022 06:18:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241593AbiCJLRy (ORCPT ); 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Thu, 10 Mar 2022 05:16:38 -0600 From: Bharata B Rao To: CC: , , , , , , , , , , , , "Bharata B Rao" Subject: [RFC PATCH v0 6/6] x86: Add prctl() options to control tagged user addresses ABI Date: Thu, 10 Mar 2022 16:45:45 +0530 Message-ID: <20220310111545.10852-7-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310111545.10852-1-bharata@amd.com> References: <20220310111545.10852-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 54ad381d-831f-48d6-562f-08da028775d8 X-MS-TrafficTypeDiagnostic: DM6PR12MB3643:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kbcvRvV/lmgpXlu27R1XgpN84sc7HI3qrJYbNg30Ht35PJ8A7rf7i+OnKrVtoMxtV13gqtLpxeJGqrbzWg+ApeD+RwVKeplD4ypIFvVCa6Np1WRcgwUjbG0gLrWIGrADxq7KfSkKC60DLTlRVBqV1tujOjunRUlmc8ofbSRHAXzyU6TBUJYsfppexRwvQFgHztz6o7fjLLzmvZ0ixnaezRbY9yv8IMLdLKxUnvww7oZZioRerF80kuVV1xppLpCwDznAklKdA848s3MMBGt3XfAa0fz3UQgM7xF2uXofMEI4b/6mfbzoT2QpHb6g4F9Sn9HnrD/7sw0c1gkVuxK+2QZ+JXabYjQZjTxWnCBMzkbPb2scfG+2YFg/PrJotyjFNrHh75uXUWgkvnNP1fsp6JNKWuIP4yW9j5iqoVwg9YFErf0RAtcGfoicBSOfVW9gTDw/M8zi/D6OpmTKN3piWzgoTxhQda5gqYF1b0cOzcWJmpOWP2KbGUXwsM/DvFL0kZeDWp4U6YcU5KHNdKhvgWSgcsKCDXRdu28GA/huuURULJwNhDyhYASPqhQ4+tonoTnpIt4n83bar+XvCNR8uguDVpLae1BR1lxcv8nG198imbURcCSbD0BjC7ToZnrqHx8GH4+zpQX/WF3VuljEZzCJXD8J/V8Rvszv0jy3iRkb0kTHiljSsNBhNOIcjmIrfy7ZB/wOCpYMmIstDk3Cdg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(6916009)(81166007)(426003)(54906003)(1076003)(70206006)(8676002)(5660300002)(70586007)(356005)(2906002)(40460700003)(83380400001)(316002)(47076005)(36756003)(2616005)(336012)(7416002)(86362001)(16526019)(26005)(82310400004)(8936002)(186003)(4326008)(7696005)(6666004)(508600001)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2022 11:16:44.5424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54ad381d-831f-48d6-562f-08da028775d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3643 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Provide an option for applications to opt-in for a relaxed tagged ABI via prtcl(). This allows them to pass tagged addresses to syscalls as pointer arguments. The implementation is kept separate for AMD UAI as the equivalent implementation for Intel LAM is likely to be different. Signed-off-by: Bharata B Rao --- arch/x86/Kconfig | 9 +++ arch/x86/include/asm/processor.h | 12 +++ arch/x86/include/asm/uaccess.h | 3 +- arch/x86/kernel/process.c | 134 +++++++++++++++++++++++++++++++ 4 files changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9f5bd41bf660..b73414eb1c01 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2436,6 +2436,15 @@ config STRICT_SIGALTSTACK_SIZE =20 source "kernel/livepatch/Kconfig" =20 +config X86_TAGGED_ADDR_ABI + bool "Enable the tagged user addresses syscall ABI" + depends on X86_64 && CPU_SUP_AMD + default y + help + When this option is enabled, user applications can opt-in to a + relaxed ABI via prctl() allowing tagged addresses to be passed + to system calls as pointer arguments. + endmenu =20 config ARCH_HAS_ADD_PAGES diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 2c5f12ae7d04..414e2c039c34 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -863,4 +863,16 @@ bool arch_is_platform_page(u64 paddr); #define arch_is_platform_page arch_is_platform_page #endif =20 +#ifdef CONFIG_X86_TAGGED_ADDR_ABI +/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long flags, + int __user *nr_bits, int __user *offset); +long get_tagged_addr_ctrl(struct task_struct *task, + int __user *nr_bits, int __user *offset); +#define SET_TAGGED_ADDR_CTRL(flags, nr_bits, offset) \ + set_tagged_addr_ctrl(current, flags, nr_bits, offset) +#define GET_TAGGED_ADDR_CTRL(nr_bits, offset) \ + get_tagged_addr_ctrl(current, nr_bits, offset) +#endif + #endif /* _ASM_X86_PROCESSOR_H */ diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index feb2e21c7e09..e415523dc425 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -38,7 +38,8 @@ static inline bool __chk_range_not_ok(unsigned long addr,= unsigned long size, un static inline bool __range_not_ok(const void __user *addr, unsigned long s= ize, unsigned long limit) { - if (test_thread_flag(TIF_TAGGED_ADDR)) + if (IS_ENABLED(CONFIG_X86_TAGGED_ADDR_ABI) && + (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR))) addr =3D untagged_addr(addr); =20 __chk_user_ptr(addr); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 81d8ef036637..2bc44efdd994 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,12 @@ static void pkru_flush_thread(void) pkru_write_default(); } =20 +static void flush_tagged_addr_state(void) +{ + if (IS_ENABLED(CONFIG_X86_TAGGED_ADDR_ABI)) + clear_thread_flag(TIF_TAGGED_ADDR); +} + void flush_thread(void) { struct task_struct *tsk =3D current; @@ -240,6 +247,7 @@ void flush_thread(void) =20 fpu_flush_thread(); pkru_flush_thread(); + flush_tagged_addr_state(); } =20 void disable_TSC(void) @@ -1000,3 +1008,129 @@ long do_arch_prctl_common(struct task_struct *task,= int option, =20 return -EINVAL; } + +#ifdef CONFIG_X86_TAGGED_ADDR_ABI +/* + * Control the relaxed ABI allowing tagged user addresses into the kernel. + */ +static unsigned int tagged_addr_disabled; + +#ifdef CONFIG_CPU_SUP_AMD +#define UAI_TAG_BITS 7 + +static long amd_set_tagged_addr_ctrl(unsigned long flags, int __user *nr_b= its, + int __user *offset) +{ + int val; + + if (!boot_cpu_has(X86_FEATURE_UAI)) + return -EINVAL; + + /* Disable tagging */ + if (!(flags & PR_TAGGED_ADDR_ENABLE)) { + clear_thread_flag(TIF_TAGGED_ADDR); + return 0; + } + + if (!nr_bits || !offset) + return -EINVAL; + + /* + * Do not allow the enabling of the tagged address ABI if globally + * disabled via sysctl abi.tagged_addr_disabled. + */ + if (tagged_addr_disabled) + return -EINVAL; + + if (get_user(val, nr_bits)) + return -EFAULT; + + if (val !=3D UAI_TAG_BITS) + return -EINVAL; + + if (put_user(val, nr_bits) || put_user(64 - val, offset)) + return -EFAULT; + + set_thread_flag(TIF_TAGGED_ADDR); + return 0; +} + +static long amd_get_tagged_addr_ctrl(int __user *nr_bits, int __user *offs= et) +{ + long ret =3D 0; + + if (!boot_cpu_has(X86_FEATURE_UAI)) + return -EINVAL; + + if (test_thread_flag(TIF_TAGGED_ADDR)) { + if (nr_bits && put_user(UAI_TAG_BITS, nr_bits)) + return -EFAULT; + if (offset && put_user(64 - UAI_TAG_BITS, offset)) + return -EFAULT; + ret =3D PR_TAGGED_ADDR_ENABLE; + } else { + /* Report max tag size */ + if (nr_bits && put_user(UAI_TAG_BITS, nr_bits)) + return -EFAULT; + } + return ret; +} +#endif + +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long flags, + int __user *nr_bits, int __user *offset) +{ + unsigned long valid_mask =3D PR_TAGGED_ADDR_ENABLE; + + if (in_32bit_syscall()) + return -EINVAL; + + if (flags & ~valid_mask) + return -EINVAL; + + if (IS_ENABLED(CONFIG_CPU_SUP_AMD)) + return amd_set_tagged_addr_ctrl(flags, nr_bits, offset); + else + return -EINVAL; +} + +long get_tagged_addr_ctrl(struct task_struct *task, + int __user *nr_bits, int __user *offset) +{ + + if (in_32bit_syscall()) + return -EINVAL; + + if (IS_ENABLED(CONFIG_CPU_SUP_AMD)) + return amd_get_tagged_addr_ctrl(nr_bits, offset); + else + return -EINVAL; +} + +/* + * Global sysctl to disable the tagged user addresses support. This control + * only prevents the tagged address ABI enabling via prctl() and does not + * disable it for tasks that already opted in to the relaxed ABI. + */ +static struct ctl_table tagged_addr_sysctl_table[] =3D { + { + .procname =3D "tagged_addr_disabled", + .mode =3D 0644, + .data =3D &tagged_addr_disabled, + .maxlen =3D sizeof(int), + .proc_handler =3D proc_dointvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, + { } +}; + +static int __init tagged_addr_init(void) +{ + if (!register_sysctl("abi", tagged_addr_sysctl_table)) + return -EINVAL; + return 0; +} + +core_initcall(tagged_addr_init); +#endif /* CONFIG_X86_TAGGED_ADDR_ABI */ --=20 2.25.1