From nobody Tue Jun 23 06:12:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DFF2C433F5 for ; Wed, 9 Mar 2022 22:34:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238729AbiCIWfn (ORCPT ); Wed, 9 Mar 2022 17:35:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238700AbiCIWfi (ORCPT ); Wed, 9 Mar 2022 17:35:38 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7ED212168A for ; Wed, 9 Mar 2022 14:34:37 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id 9so3220985pll.6 for ; Wed, 09 Mar 2022 14:34:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U6O5sm7q1F6xFSlPrH17/2jiVY2VUS9QtitvGJZRQyk=; b=KnvZ8YiLrEK4Afru/3Tu2SukfgKgYEj7Mscax/ctTPtDn3sgCDBvnrJ70J+xa24cBa E731vxG0Tx9xpg8m9XXBa6BmBHY8a0xvS3QDbt3Yz65V+ryUquGW0jIdLDoXcB8YBWjj i+guqHsauDBQ2/t3YTa/V1oAxigBON9I6ahgHNu1NUzYYfr/AyEOSjyumHkQzVWqvJ5J tCuIsAjNyyNV5ccPwGCg7loHtofGHn0qlaOyUWe9hIHACsJ/sNyOXAaM9OEm4fB0i0GX tX48vNBVJAtot1W3o1r7bpSlu92V/cVK0EScVABDSvYNlg5BToDHUxD/mVRDgPvg+SJ4 vZPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U6O5sm7q1F6xFSlPrH17/2jiVY2VUS9QtitvGJZRQyk=; b=KbEEo+e1efTDJxfUgh4JyhkDATcCLBVezjXKyH/jYA/YzscP0GToZNx8HlQMLqsjUv psMOOxmvz58bFXi73UwomU4WXvrFn4jyrKBICsNfwHRnWScnQ2/p1rL1la6PQGEGgSMe 4I9F6kr5Cviwi1XvY1azwJK2ZORrR4S4z1NLmGW+BAB+j/lQ609aNZlV9hOfsChcwI3j EfxmDbBSG5FoLEnA97dE6CeHilQrbY6WQgd7yacx9Q7kTKKzM6paeZKuOhYs+saWXTTJ Jv4zWxXps+CUPC0S4hzSsQcQAkobtLofny1vOs4UvHjhPBEimn4EiZZm3C7hE9UOJj9k 1HoA== X-Gm-Message-State: AOAM533e0Jzo1YUCf+SxA2NJ05ia3mFCgaLhNlBl4UQB2CpBdBeZE5vi X5v3XTHNISw7C80yAVprQk744OepBTclyg== X-Google-Smtp-Source: ABdhPJzGl1Z1Rc5KiPXNcDUYVz/ayHeqedpwp76qEbtb2lt066z6xSeqFPyFPtT63u/ONkgLZz80Eg== X-Received: by 2002:a17:902:ec82:b0:151:cd00:99d with SMTP id x2-20020a170902ec8200b00151cd00099dmr1887580plg.96.1646865277093; Wed, 09 Mar 2022 14:34:37 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:6f34:be93:349a:f478]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm3476477pfv.206.2022.03.09.14.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 14:34:36 -0800 (PST) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 1/2] xtensa: add helpers for division, remainder and shifts Date: Wed, 9 Mar 2022 14:34:17 -0800 Message-Id: <20220309223418.1253242-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220309223418.1253242-1-jcmvbkbc@gmail.com> References: <20220309223418.1253242-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Don't rely on libgcc presence, build own versions of the helpers with correct ABI. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/asmmacro.h | 34 ++++++++ arch/xtensa/lib/Makefile | 2 + arch/xtensa/lib/ashldi3.S | 28 ++++++ arch/xtensa/lib/ashrdi3.S | 28 ++++++ arch/xtensa/lib/divsi3.S | 74 ++++++++++++++++ arch/xtensa/lib/lshrdi3.S | 28 ++++++ arch/xtensa/lib/modsi3.S | 87 +++++++++++++++++++ arch/xtensa/lib/mulsi3.S | 133 +++++++++++++++++++++++++++++ arch/xtensa/lib/udivsi3.S | 68 +++++++++++++++ arch/xtensa/lib/umodsi3.S | 57 +++++++++++++ 10 files changed, 539 insertions(+) create mode 100644 arch/xtensa/lib/ashldi3.S create mode 100644 arch/xtensa/lib/ashrdi3.S create mode 100644 arch/xtensa/lib/divsi3.S create mode 100644 arch/xtensa/lib/lshrdi3.S create mode 100644 arch/xtensa/lib/modsi3.S create mode 100644 arch/xtensa/lib/mulsi3.S create mode 100644 arch/xtensa/lib/udivsi3.S create mode 100644 arch/xtensa/lib/umodsi3.S diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/a= smmacro.h index 809c507d1825..3190157950fa 100644 --- a/arch/xtensa/include/asm/asmmacro.h +++ b/arch/xtensa/include/asm/asmmacro.h @@ -191,6 +191,40 @@ #endif .endm =20 + .macro do_nsau cnt, val, tmp, a +#if XCHAL_HAVE_NSA + nsau \cnt, \val +#else + mov \a, \val + movi \cnt, 0 + extui \tmp, \a, 16, 16 + bnez \tmp, 0f + movi \cnt, 16 + slli \a, \a, 16 +0: + extui \tmp, \a, 24, 8 + bnez \tmp, 1f + addi \cnt, \cnt, 8 + slli \a, \a, 8 +1: + movi \tmp, __nsau_data + extui \a, \a, 24, 8 + add \tmp, \tmp, \a + l8ui \tmp, \tmp, 0 + add \cnt, \cnt, \tmp +#endif /* !XCHAL_HAVE_NSA */ + .endm + + .macro do_abs dst, src, tmp +#if XCHAL_HAVE_ABS + abs \dst, \src +#else + neg \tmp, \src + movgez \tmp, \src, \src + mov \dst, \tmp +#endif + .endm + #define XTENSA_STACK_ALIGNMENT 16 =20 #if defined(__XTENSA_WINDOWED_ABI__) diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile index 9437ca51f18a..5848c133f7ea 100644 --- a/arch/xtensa/lib/Makefile +++ b/arch/xtensa/lib/Makefile @@ -4,5 +4,7 @@ # =20 lib-y +=3D memcopy.o memset.o checksum.o \ + ashldi3.o ashrdi3.o lshrdi3.o \ + divsi3.o udivsi3.o modsi3.o umodsi3.o mulsi3.o \ usercopy.o strncpy_user.o strnlen_user.o lib-$(CONFIG_PCI) +=3D pci-auto.o diff --git a/arch/xtensa/lib/ashldi3.S b/arch/xtensa/lib/ashldi3.S new file mode 100644 index 000000000000..67fb0da9e432 --- /dev/null +++ b/arch/xtensa/lib/ashldi3.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +#ifdef __XTENSA_EB__ +#define uh a2 +#define ul a3 +#else +#define uh a3 +#define ul a2 +#endif /* __XTENSA_EB__ */ + +ENTRY(__ashldi3) + + abi_entry_default + ssl a4 + bgei a4, 32, .Llow_only + src uh, uh, ul + sll ul, ul + abi_ret_default + +.Llow_only: + sll uh, ul + movi ul, 0 + abi_ret_default + +ENDPROC(__ashldi3) diff --git a/arch/xtensa/lib/ashrdi3.S b/arch/xtensa/lib/ashrdi3.S new file mode 100644 index 000000000000..cbf052c512cc --- /dev/null +++ b/arch/xtensa/lib/ashrdi3.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +#ifdef __XTENSA_EB__ +#define uh a2 +#define ul a3 +#else +#define uh a3 +#define ul a2 +#endif /* __XTENSA_EB__ */ + +ENTRY(__ashrdi3) + + abi_entry_default + ssr a4 + bgei a4, 32, .Lhigh_only + src ul, uh, ul + sra uh, uh + abi_ret_default + +.Lhigh_only: + sra ul, uh + srai uh, uh, 31 + abi_ret_default + +ENDPROC(__ashrdi3) diff --git a/arch/xtensa/lib/divsi3.S b/arch/xtensa/lib/divsi3.S new file mode 100644 index 000000000000..b044b4744a8b --- /dev/null +++ b/arch/xtensa/lib/divsi3.S @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +ENTRY(__divsi3) + + abi_entry_default +#if XCHAL_HAVE_DIV32 + quos a2, a2, a3 +#else + xor a7, a2, a3 /* sign =3D dividend ^ divisor */ + do_abs a6, a2, a4 /* udividend =3D abs (dividend) */ + do_abs a3, a3, a4 /* udivisor =3D abs (divisor) */ + bltui a3, 2, .Lle_one /* check if udivisor <=3D 1 */ + do_nsau a5, a6, a2, a8 /* udividend_shift =3D nsau (udividend) */ + do_nsau a4, a3, a2, a8 /* udivisor_shift =3D nsau (udivisor) */ + bgeu a5, a4, .Lspecial + + sub a4, a4, a5 /* count =3D udivisor_shift - udividend_shift */ + ssl a4 + sll a3, a3 /* udivisor <<=3D count */ + movi a2, 0 /* quotient =3D 0 */ + + /* test-subtract-and-shift loop; one quotient bit on each iteration */ +#if XCHAL_HAVE_LOOPS + loopnez a4, .Lloopend +#endif /* XCHAL_HAVE_LOOPS */ +.Lloop: + bltu a6, a3, .Lzerobit + sub a6, a6, a3 + addi a2, a2, 1 +.Lzerobit: + slli a2, a2, 1 + srli a3, a3, 1 +#if !XCHAL_HAVE_LOOPS + addi a4, a4, -1 + bnez a4, .Lloop +#endif /* !XCHAL_HAVE_LOOPS */ +.Lloopend: + + bltu a6, a3, .Lreturn + addi a2, a2, 1 /* increment if udividend >=3D udivisor */ +.Lreturn: + neg a5, a2 + movltz a2, a5, a7 /* return (sign < 0) ? -quotient : quotient */ + abi_ret_default + +.Lle_one: + beqz a3, .Lerror + neg a2, a6 /* if udivisor =3D=3D 1, then return... */ + movgez a2, a6, a7 /* (sign < 0) ? -udividend : udividend */ + abi_ret_default + +.Lspecial: + bltu a6, a3, .Lreturn0 /* if dividend < divisor, return 0 */ + movi a2, 1 + movi a4, -1 + movltz a2, a4, a7 /* else return (sign < 0) ? -1 : 1 */ + abi_ret_default + +.Lerror: + /* Divide by zero: Use an illegal instruction to force an exception. + The subsequent "DIV0" string can be recognized by the exception + handler to identify the real cause of the exception. */ + ill + .ascii "DIV0" + +.Lreturn0: + movi a2, 0 +#endif /* XCHAL_HAVE_DIV32 */ + abi_ret_default + +ENDPROC(__divsi3) diff --git a/arch/xtensa/lib/lshrdi3.S b/arch/xtensa/lib/lshrdi3.S new file mode 100644 index 000000000000..129ef8d1725b --- /dev/null +++ b/arch/xtensa/lib/lshrdi3.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +#ifdef __XTENSA_EB__ +#define uh a2 +#define ul a3 +#else +#define uh a3 +#define ul a2 +#endif /* __XTENSA_EB__ */ + +ENTRY(__lshrdi3) + + abi_entry_default + ssr a4 + bgei a4, 32, .Lhigh_only + src ul, uh, ul + srl uh, uh + abi_ret_default + +.Lhigh_only: + srl ul, uh + movi uh, 0 + abi_ret_default + +ENDPROC(__lshrdi3) diff --git a/arch/xtensa/lib/modsi3.S b/arch/xtensa/lib/modsi3.S new file mode 100644 index 000000000000..d00e77181e20 --- /dev/null +++ b/arch/xtensa/lib/modsi3.S @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +ENTRY(__modsi3) + + abi_entry_default +#if XCHAL_HAVE_DIV32 + rems a2, a2, a3 +#else + mov a7, a2 /* save original (signed) dividend */ + do_abs a2, a2, a4 /* udividend =3D abs (dividend) */ + do_abs a3, a3, a4 /* udivisor =3D abs (divisor) */ + bltui a3, 2, .Lle_one /* check if udivisor <=3D 1 */ + do_nsau a5, a2, a6, a8 /* udividend_shift =3D nsau (udividend) */ + do_nsau a4, a3, a6, a8 /* udivisor_shift =3D nsau (udivisor) */ + bgeu a5, a4, .Lspecial + + sub a4, a4, a5 /* count =3D udivisor_shift - udividend_shift */ + ssl a4 + sll a3, a3 /* udivisor <<=3D count */ + + /* test-subtract-and-shift loop */ +#if XCHAL_HAVE_LOOPS + loopnez a4, .Lloopend +#endif /* XCHAL_HAVE_LOOPS */ +.Lloop: + bltu a2, a3, .Lzerobit + sub a2, a2, a3 +.Lzerobit: + srli a3, a3, 1 +#if !XCHAL_HAVE_LOOPS + addi a4, a4, -1 + bnez a4, .Lloop +#endif /* !XCHAL_HAVE_LOOPS */ +.Lloopend: + +.Lspecial: + bltu a2, a3, .Lreturn + sub a2, a2, a3 /* subtract again if udividend >=3D udivisor */ +.Lreturn: + bgez a7, .Lpositive + neg a2, a2 /* if (dividend < 0), return -udividend */ +.Lpositive: + abi_ret_default + +.Lle_one: + bnez a3, .Lreturn0 + + /* Divide by zero: Use an illegal instruction to force an exception. + The subsequent "DIV0" string can be recognized by the exception + handler to identify the real cause of the exception. */ + ill + .ascii "DIV0" + +.Lreturn0: + movi a2, 0 +#endif /* XCHAL_HAVE_DIV32 */ + abi_ret_default + +ENDPROC(__modsi3) + +#if !XCHAL_HAVE_NSA + .section .rodata + .align 4 + .global __nsau_data + .type __nsau_data, @object +__nsau_data: + .byte 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4 + .byte 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 + .byte 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 + .byte 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + .size __nsau_data, . - __nsau_data +#endif /* !XCHAL_HAVE_NSA */ diff --git a/arch/xtensa/lib/mulsi3.S b/arch/xtensa/lib/mulsi3.S new file mode 100644 index 000000000000..91a9d7c62f96 --- /dev/null +++ b/arch/xtensa/lib/mulsi3.S @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + + .macro do_addx2 dst, as, at, tmp +#if XCHAL_HAVE_ADDX + addx2 \dst, \as, \at +#else + slli \tmp, \as, 1 + add \dst, \tmp, \at +#endif + .endm + + .macro do_addx4 dst, as, at, tmp +#if XCHAL_HAVE_ADDX + addx4 \dst, \as, \at +#else + slli \tmp, \as, 2 + add \dst, \tmp, \at +#endif + .endm + + .macro do_addx8 dst, as, at, tmp +#if XCHAL_HAVE_ADDX + addx8 \dst, \as, \at +#else + slli \tmp, \as, 3 + add \dst, \tmp, \at +#endif + .endm + +ENTRY(__mulsi3) + + abi_entry_default + +#if XCHAL_HAVE_MUL32 + mull a2, a2, a3 + +#elif XCHAL_HAVE_MUL16 + or a4, a2, a3 + srai a4, a4, 16 + bnez a4, .LMUL16 + mul16u a2, a2, a3 + abi_ret_default +.LMUL16: + srai a4, a2, 16 + srai a5, a3, 16 + mul16u a7, a4, a3 + mul16u a6, a5, a2 + mul16u a4, a2, a3 + add a7, a7, a6 + slli a7, a7, 16 + add a2, a7, a4 + +#elif XCHAL_HAVE_MAC16 + mul.aa.hl a2, a3 + mula.aa.lh a2, a3 + rsr a5, ACCLO + umul.aa.ll a2, a3 + rsr a4, ACCLO + slli a5, a5, 16 + add a2, a4, a5 + +#else /* !MUL32 && !MUL16 && !MAC16 */ + + /* Multiply one bit at a time, but unroll the loop 4x to better + exploit the addx instructions and avoid overhead. + Peel the first iteration to save a cycle on init. */ + + /* Avoid negative numbers. */ + xor a5, a2, a3 /* Top bit is 1 if one input is negative. */ + do_abs a3, a3, a6 + do_abs a2, a2, a6 + + /* Swap so the second argument is smaller. */ + sub a7, a2, a3 + mov a4, a3 + movgez a4, a2, a7 /* a4 =3D max (a2, a3) */ + movltz a3, a2, a7 /* a3 =3D min (a2, a3) */ + + movi a2, 0 + extui a6, a3, 0, 1 + movnez a2, a4, a6 + + do_addx2 a7, a4, a2, a7 + extui a6, a3, 1, 1 + movnez a2, a7, a6 + + do_addx4 a7, a4, a2, a7 + extui a6, a3, 2, 1 + movnez a2, a7, a6 + + do_addx8 a7, a4, a2, a7 + extui a6, a3, 3, 1 + movnez a2, a7, a6 + + bgeui a3, 16, .Lmult_main_loop + neg a3, a2 + movltz a2, a3, a5 + abi_ret_default + + .align 4 +.Lmult_main_loop: + srli a3, a3, 4 + slli a4, a4, 4 + + add a7, a4, a2 + extui a6, a3, 0, 1 + movnez a2, a7, a6 + + do_addx2 a7, a4, a2, a7 + extui a6, a3, 1, 1 + movnez a2, a7, a6 + + do_addx4 a7, a4, a2, a7 + extui a6, a3, 2, 1 + movnez a2, a7, a6 + + do_addx8 a7, a4, a2, a7 + extui a6, a3, 3, 1 + movnez a2, a7, a6 + + bgeui a3, 16, .Lmult_main_loop + + neg a3, a2 + movltz a2, a3, a5 + +#endif /* !MUL32 && !MUL16 && !MAC16 */ + + abi_ret_default + +ENDPROC(__mulsi3) diff --git a/arch/xtensa/lib/udivsi3.S b/arch/xtensa/lib/udivsi3.S new file mode 100644 index 000000000000..d2477e0786cf --- /dev/null +++ b/arch/xtensa/lib/udivsi3.S @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +ENTRY(__udivsi3) + + abi_entry_default +#if XCHAL_HAVE_DIV32 + quou a2, a2, a3 +#else + bltui a3, 2, .Lle_one /* check if the divisor <=3D 1 */ + + mov a6, a2 /* keep dividend in a6 */ + do_nsau a5, a6, a2, a7 /* dividend_shift =3D nsau (dividend) */ + do_nsau a4, a3, a2, a7 /* divisor_shift =3D nsau (divisor) */ + bgeu a5, a4, .Lspecial + + sub a4, a4, a5 /* count =3D divisor_shift - dividend_shift */ + ssl a4 + sll a3, a3 /* divisor <<=3D count */ + movi a2, 0 /* quotient =3D 0 */ + + /* test-subtract-and-shift loop; one quotient bit on each iteration */ +#if XCHAL_HAVE_LOOPS + loopnez a4, .Lloopend +#endif /* XCHAL_HAVE_LOOPS */ +.Lloop: + bltu a6, a3, .Lzerobit + sub a6, a6, a3 + addi a2, a2, 1 +.Lzerobit: + slli a2, a2, 1 + srli a3, a3, 1 +#if !XCHAL_HAVE_LOOPS + addi a4, a4, -1 + bnez a4, .Lloop +#endif /* !XCHAL_HAVE_LOOPS */ +.Lloopend: + + bltu a6, a3, .Lreturn + addi a2, a2, 1 /* increment quotient if dividend >=3D divisor */ +.Lreturn: + abi_ret_default + +.Lle_one: + beqz a3, .Lerror /* if divisor =3D=3D 1, return the dividend */ + abi_ret_default + +.Lspecial: + /* return dividend >=3D divisor */ + bltu a6, a3, .Lreturn0 + movi a2, 1 + abi_ret_default + +.Lerror: + /* Divide by zero: Use an illegal instruction to force an exception. + The subsequent "DIV0" string can be recognized by the exception + handler to identify the real cause of the exception. */ + ill + .ascii "DIV0" + +.Lreturn0: + movi a2, 0 +#endif /* XCHAL_HAVE_DIV32 */ + abi_ret_default + +ENDPROC(__udivsi3) diff --git a/arch/xtensa/lib/umodsi3.S b/arch/xtensa/lib/umodsi3.S new file mode 100644 index 000000000000..5f031bfa0354 --- /dev/null +++ b/arch/xtensa/lib/umodsi3.S @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH GCC-exception-2.0 */ +#include +#include +#include + +ENTRY(__umodsi3) + + abi_entry_default +#if XCHAL_HAVE_DIV32 + remu a2, a2, a3 +#else + bltui a3, 2, .Lle_one /* check if the divisor is <=3D 1 */ + + do_nsau a5, a2, a6, a7 /* dividend_shift =3D nsau (dividend) */ + do_nsau a4, a3, a6, a7 /* divisor_shift =3D nsau (divisor) */ + bgeu a5, a4, .Lspecial + + sub a4, a4, a5 /* count =3D divisor_shift - dividend_shift */ + ssl a4 + sll a3, a3 /* divisor <<=3D count */ + + /* test-subtract-and-shift loop */ +#if XCHAL_HAVE_LOOPS + loopnez a4, .Lloopend +#endif /* XCHAL_HAVE_LOOPS */ +.Lloop: + bltu a2, a3, .Lzerobit + sub a2, a2, a3 +.Lzerobit: + srli a3, a3, 1 +#if !XCHAL_HAVE_LOOPS + addi a4, a4, -1 + bnez a4, .Lloop +#endif /* !XCHAL_HAVE_LOOPS */ +.Lloopend: + +.Lspecial: + bltu a2, a3, .Lreturn + sub a2, a2, a3 /* subtract once more if dividend >=3D divisor */ +.Lreturn: + abi_ret_default + +.Lle_one: + bnez a3, .Lreturn0 + + /* Divide by zero: Use an illegal instruction to force an exception. + The subsequent "DIV0" string can be recognized by the exception + handler to identify the real cause of the exception. */ + ill + .ascii "DIV0" + +.Lreturn0: + movi a2, 0 +#endif /* XCHAL_HAVE_DIV32 */ + abi_ret_default + +ENDPROC(__umodsi3) --=20 2.30.2 From nobody Tue Jun 23 06:12:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D5ACC433F5 for ; Wed, 9 Mar 2022 22:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238735AbiCIWfo (ORCPT ); Wed, 9 Mar 2022 17:35:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238702AbiCIWfi (ORCPT ); Wed, 9 Mar 2022 17:35:38 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04617121689 for ; Wed, 9 Mar 2022 14:34:39 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id h5so1853692plf.7 for ; Wed, 09 Mar 2022 14:34:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iqofDGyvLh9ucnd9K2IvJDYKRmWqauAqViHarwufpQo=; b=OADP5Tdq8IEmMkpS6qsuttrrRqtzkyntAjIyx9m7gOS2j73vT942qZA4DhUwWkRXhw NiVem8FWxIyiRa7hnClnEVdWuw6NzdkRx19K4RmelBn7IKON5TyNUic5QEh4Y0SXKAM8 1D5VYGceoTDZDgTAfPE1r1/K2I6Iv2z4pWbyNbYiJNaEQnKWf1lWuRhJNmJ2V2ABJvJK Bj1NZCdE4MUDbs/FvYrBGvuwtHlZe+lh7QWatODVqHobR7N2eeBa6dEp2DYmntp91EpL tqgDpTzraqoUlc+VKxfdr08ueP506O/m52NUAQGHy2CLYAN4fMKL2k2QCrbrrMt1/AKr Cprg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iqofDGyvLh9ucnd9K2IvJDYKRmWqauAqViHarwufpQo=; b=XMsEVjvtJM1Q2Cug6BZK0X2tT7mJUyW0ujhd3f+yikIBO+TXmYFpPP/YJsqm6WATps gcwlWh6pPkg2Bd4EzwxeENu4QyXEkym+Na0//yl+k1nFJq28YSAoERmJNPruU/vxB1K6 ejodi7AVgtFIhme7TFsdHXjdwwrBi9+nzp6UB8l5zR3hnwem7ogmyq6+6Ye6rX1fYgal 0ozM4gC/B82498mGA8jQ+g3ghn3ivsbTdrdA9IeZm0rkYIICm+SMVCmXEP2SXopM8rli gbjkX3L3BgIEASKS2zGLCXqchl2vVP5jyRZqWHrhL3+Wojhbs0ocRDVOLKu3BKPJq6CT SQ6A== X-Gm-Message-State: AOAM530VTgGHQcMsMywj4C3R0k9svjl+vlwpSGVuk/RGq0h8gOQjWi3f nhVOksQFdYFOrcPNjBPw87M= X-Google-Smtp-Source: ABdhPJw3GGik8ofqP7XbwJF1EfgkYIqYSlkZZCNl+r7SAtuLMEY/vW7U1uW85L91ejc+GIbmZyXIxg== X-Received: by 2002:a17:90b:4c43:b0:1bf:8585:9baa with SMTP id np3-20020a17090b4c4300b001bf85859baamr1808359pjb.60.1646865278466; Wed, 09 Mar 2022 14:34:38 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:6f34:be93:349a:f478]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm3476477pfv.206.2022.03.09.14.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 14:34:37 -0800 (PST) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 2/2] xtensa: don't link with libgcc Date: Wed, 9 Mar 2022 14:34:18 -0800 Message-Id: <20220309223418.1253242-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220309223418.1253242-1-jcmvbkbc@gmail.com> References: <20220309223418.1253242-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" libgcc may be absent or may have different ABI than the kernel. Don't link with it. Drop declarations and export for helpers that are not implemented. Use generic versions of DI mode multiplication and comparisons. Drop register window spilling helper as it should never be used by the compiler-generated code. Signed-off-by: Max Filippov --- arch/xtensa/Kconfig | 3 +++ arch/xtensa/Makefile | 6 +----- arch/xtensa/kernel/xtensa_ksyms.c | 14 -------------- 3 files changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 8ac599aa6d99..b324f6743073 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -20,6 +20,9 @@ config XTENSA select DMA_REMAP if MMU select GENERIC_ATOMIC64 select GENERIC_IRQ_SHOW + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_UCMPDI2 select GENERIC_PCI_IOMAP select GENERIC_SCHED_CLOCK select HAVE_ARCH_AUDITSYSCALL diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile index ee2769519eaf..725cd4cd8b30 100644 --- a/arch/xtensa/Makefile +++ b/arch/xtensa/Makefile @@ -51,13 +51,9 @@ KBUILD_CPPFLAGS +=3D $(patsubst %,-I$(srctree)/%include,= $(vardirs) $(plfdirs)) =20 KBUILD_DEFCONFIG :=3D iss_defconfig =20 -# Find libgcc.a - -LIBGCC :=3D $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) - head-y :=3D arch/xtensa/kernel/head.o =20 -libs-y +=3D arch/xtensa/lib/ $(LIBGCC) +libs-y +=3D arch/xtensa/lib/ =20 boot :=3D arch/xtensa/boot =20 diff --git a/arch/xtensa/kernel/xtensa_ksyms.c b/arch/xtensa/kernel/xtensa_= ksyms.c index d79edbb98d2a..b0bc8897c924 100644 --- a/arch/xtensa/kernel/xtensa_ksyms.c +++ b/arch/xtensa/kernel/xtensa_ksyms.c @@ -59,32 +59,18 @@ extern long long __ashldi3(long long, int); extern long long __lshrdi3(long long, int); extern int __divsi3(int, int); extern int __modsi3(int, int); -extern long long __muldi3(long long, long long); extern int __mulsi3(int, int); extern unsigned int __udivsi3(unsigned int, unsigned int); extern unsigned int __umodsi3(unsigned int, unsigned int); -extern unsigned long long __umoddi3(unsigned long long, unsigned long long= ); -extern unsigned long long __udivdi3(unsigned long long, unsigned long long= ); -extern int __ucmpdi2(int, int); =20 EXPORT_SYMBOL(__ashldi3); EXPORT_SYMBOL(__ashrdi3); EXPORT_SYMBOL(__lshrdi3); EXPORT_SYMBOL(__divsi3); EXPORT_SYMBOL(__modsi3); -EXPORT_SYMBOL(__muldi3); EXPORT_SYMBOL(__mulsi3); EXPORT_SYMBOL(__udivsi3); EXPORT_SYMBOL(__umodsi3); -EXPORT_SYMBOL(__udivdi3); -EXPORT_SYMBOL(__umoddi3); -EXPORT_SYMBOL(__ucmpdi2); - -void __xtensa_libgcc_window_spill(void) -{ - BUG(); -} -EXPORT_SYMBOL(__xtensa_libgcc_window_spill); =20 unsigned int __sync_fetch_and_and_4(volatile void *p, unsigned int v) { --=20 2.30.2