From nobody Tue Jun 23 06:19:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3378AC4332F for ; Wed, 9 Mar 2022 15:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233787AbiCIPQ4 (ORCPT ); Wed, 9 Mar 2022 10:16:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233778AbiCIPQy (ORCPT ); Wed, 9 Mar 2022 10:16:54 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 428DE17BC6E for ; Wed, 9 Mar 2022 07:15:55 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id v4so2619376pjh.2 for ; Wed, 09 Mar 2022 07:15:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B/IcWlT+PDOAuKFhHBO22sb+SfpqtrQ61LlKL6Ry12Q=; b=t7sc/C5jUWt89kTrhEtmyKtFqcGc5bNY8RrjGzLXl4wr1SmRJfVT0gI4LIKyn8QLDW 91TbWh95XTGlepNVumZwd+GfBoe27+cmIBINILwepPfBjuuh8bHclLORplrQRXcmJQd5 mWcPaMBP8ZvmTo4VMVn1Hg7UtP6U6Umx3yEIZHeznMJBZT/WDG3s+eOXFY2q25Vvrzlp HDIlFxSWWWTnYtkwHIEK+l1prXbJ3ajK16V317xMfXoHehaY4+utvsIoECK1Bauz8mjd moaTLvtlKCQq7ekft3iWrGnG8gD0H+lb28Yxo6CrIL+c7RTxqFM+UDUxqBw5NGKjq5cE dpOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B/IcWlT+PDOAuKFhHBO22sb+SfpqtrQ61LlKL6Ry12Q=; b=xmgNErUVAmMl0YccfrIGlwcmdvOb/laI9VzKn6o0q2EIL972GQ1jB3GoEAyidm5OlJ bBf5ilXmHbMWDpiLOY7Iovc8xA0ZD04tARPvdIKibCDgCS1qhjDYxyCQZX4nunqv1PJ3 4p1Iti452BZ5tAb/DoQRq9dh47xBsIk6yYrZHUe9/t6nMDH/k9Rj4rygLV7PzGDEWIjt uwZuYCdVFvf3+wmwr6/t0KJT05mzk37MAAg1w64yHiwf4F6huFo3zKee8ODflBcOBuwn 92X9LFo0ROqJI6N9sCr1UTFFoah8SxmpWvw4a5qEYfGXcGn71JVBf9o5HWpH0wkXDEsf tiiQ== X-Gm-Message-State: AOAM531k6g7OIO/aK+35gpdPIbKqq4Q8AIfkWjTRmv41u7dz5zhExnR5 x0rXkK0EkY8HvyrGTWMWEmRw X-Google-Smtp-Source: ABdhPJwAOG34hjqTjNfdA7pWvCnPSiGY4m4NrhjpikXMG87mhNgOOsYgr4P3RiYYkBNP6WPqd0LBjQ== X-Received: by 2002:a17:902:dacc:b0:151:c216:2772 with SMTP id q12-20020a170902dacc00b00151c2162772mr23086584plx.107.1646838954708; Wed, 09 Mar 2022 07:15:54 -0800 (PST) Received: from localhost.localdomain ([117.193.208.22]) by smtp.gmail.com with ESMTPSA id p25-20020a637419000000b0037fa57520adsm2727425pgc.27.2022.03.09.07.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 07:15:54 -0800 (PST) From: Manivannan Sadhasivam To: rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, angelogioacchino.delregno@somainline.org, Manivannan Sadhasivam , Hector Yuan , Sudeep Holla Subject: [PATCH v2 1/2] dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example Date: Wed, 9 Mar 2022 20:45:40 +0530 Message-Id: <20220309151541.139511-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220309151541.139511-1-manivannan.sadhasivam@linaro.org> References: <20220309151541.139511-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom CPUFREQ HW don't have the support for generic performance domains yet. So use MediaTek CPUFREQ HW that has the support available in mainline. This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: reg: [[305397760, 4096]] is too short From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: 'clocks' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: 'clock-names' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: '#freq-domain-cells' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: '#performance-domain-cells' does not match= any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Cc: Hector Yuan Cc: Sudeep Holla Signed-off-by: Manivannan Sadhasivam Acked-by: Sudeep Holla Reviewed-by: Rob Herring --- .../bindings/dvfs/performance-domain.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml= b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml index c8b91207f34d..9e0bcf1a89fe 100644 --- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -52,10 +52,16 @@ additionalProperties: true =20 examples: - | - performance: performance-controller@12340000 { - compatible =3D "qcom,cpufreq-hw"; - reg =3D <0x12340000 0x1000>; - #performance-domain-cells =3D <1>; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + performance: performance-controller@11bc00 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + + #performance-domain-cells =3D <1>; + }; }; =20 // The node above defines a performance controller that is a performan= ce --=20 2.25.1 From nobody Tue Jun 23 06:19:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8843C433EF for ; Wed, 9 Mar 2022 15:16:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231829AbiCIPRC (ORCPT ); Wed, 9 Mar 2022 10:17:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233788AbiCIPQ7 (ORCPT ); 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Wed, 09 Mar 2022 07:15:59 -0800 (PST) From: Manivannan Sadhasivam To: rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, angelogioacchino.delregno@somainline.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v2 2/2] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings Date: Wed, 9 Mar 2022 20:45:41 +0530 Message-Id: <20220309151541.139511-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220309151541.139511-1-manivannan.sadhasivam@linaro.org> References: <20220309151541.139511-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert Qualcomm cpufreq devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 201 ++++++++++++++++++ 2 files changed, 201 insertions(+), 172 deletions(-) delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-= hw.txt create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-= hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt = b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index 9299028ee712..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,172 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (= QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequen= cy -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". - -- clocks - Usage: required - Value type: From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: From common clock binding. - Definition: must be "xo", "alternate". - -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -- #freq-domain-cells: - Usage: required. - Definition: Number of cells in a freqency domain specifier. - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property = with -phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster swit= ch -DCVS state together. - -/ { - cpus { - #address-cells =3D <2>; - #size-cells =3D <0>; - - CPU0: cpu@0 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x0>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { - compatible =3D "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x100>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x200>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x300>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x400>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x500>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x600>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x700>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: cpufreq@17d43000 { - compatible =3D "qcom,cpufreq-hw"; - reg =3D <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names =3D "freq-domain0", "freq-domain1"; - - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - - #freq-domain-cells =3D <1>; - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml new file mode 100644 index 000000000000..2f1b8b6852a0 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Manivannan Sadhasivam + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc.= (QTI) + SoCs to manage frequency in hardware. It is capable of controlling frequ= ency + for multiple clusters. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw + + - description: v2 of CPUFREQ HW (EPSS) + items: + - enum: + - qcom,sm8250-cpufreq-epss + - const: qcom,cpufreq-epss + + reg: + minItems: 2 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + + reg-names: + minItems: 2 + items: + - const: freq-domain0 + - const: freq-domain1 + - const: freq-domain2 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + '#freq-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a clust= er + // switch DCVS state together. + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_100>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_200>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_300>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_400>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_500>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_600>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_700>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpufreq@17d43000 { + compatible =3D "qcom,cpufreq-hw"; + reg =3D <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + }; + }; +... --=20 2.25.1