From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B458BC43219 for ; Tue, 8 Mar 2022 19:09:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241589AbiCHTKP (ORCPT ); Tue, 8 Mar 2022 14:10:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236771AbiCHTKK (ORCPT ); Tue, 8 Mar 2022 14:10:10 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E7103BBC8 for ; Tue, 8 Mar 2022 11:09:12 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id z4so17261998pgh.12 for ; Tue, 08 Mar 2022 11:09:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rMJkwmlB3bZLriNMyZ8DsEqjAAJ48EVoT2JT0CYAPOI=; b=mFv8IBEzTTgFYmOv2AjE+XulYFfLNCNLTODKhgvOeLdxUff238mHz2Gw8Fs0lYl0ci VTam7LL2nPiV1HzWpZFavC1ztRY9JiJB2fg61y8mZkqGkIi0fr/Io6+IF1aLIAFEWJwU tUIF3XMafY5M3rcyVRxw3AwA7dOU/S4H8ZURg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rMJkwmlB3bZLriNMyZ8DsEqjAAJ48EVoT2JT0CYAPOI=; b=id2FxzXclqqOqjWhzBSvZI9Ci3S5LlFZoTw8puQOnn8cc6v/AmSyh3/K2IETp1khKt RVrIlVGT6ucXxogG9hP7hcK9jFPVkI24JqHkKBXL7eQhSsSM3PHgfRwrdAoGkJp2jlWy mnSqwHPnqRaHQzzXxIdeiooLp0WXck0Wn+belEzQtU/mH/shMl0iaX19sliARfRJfm/f 7XuPsVBF61Rqe+z+H58fedEEyoIhdhBA96eToA2cDIr39aBt7pIc0Y0lg5eLkEG4nBSM Bm7i7OG6tq/D5jVUktcHzTfa9rrztCA8KeCmMzlRdVkMMEBRRNXr0lmqvcYpdoircxzb UjCg== X-Gm-Message-State: AOAM532xUXB3B0km6GSWA+5WPafCfHx3bmPBQcaY1/NQI9CpyA4FxP4s sc/0Hw+XstpDjYEFBORzRhMdLg== X-Google-Smtp-Source: ABdhPJyTeiljTXCBL5iqIKZD8ijrU6tja6kun6B78QjGlQLnEGaZINsOakRgSTrCt66UtHE71E5O6w== X-Received: by 2002:a05:6a00:2296:b0:4e1:905f:46b6 with SMTP id f22-20020a056a00229600b004e1905f46b6mr19879888pfe.16.1646766551838; Tue, 08 Mar 2022 11:09:11 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id b13-20020a056a00114d00b004c122b90703sm20059044pfm.27.2022.03.08.11.09.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:11 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 01/15] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Date: Tue, 8 Mar 2022 11:08:47 -0800 Message-Id: <20220308110825.v4.1.I875ab8f28c5155a7d2f103316191954d4b07ac13@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" I want to add, deprecate, and bugfix some properties, as well as add the first users. This is easier with a proper schema. The transformation is mostly straightforward, plus a few notable tweaks: * Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The driver code and the example matched, but the description was different. I went with the implementation. Note that this property is also slated for deprecation/deletion in the subsequent patches. * Drop upthreshold and downdifferential properties from the example. These were undocumented (so, wouldn't pass validation), but were representing software properties (governor tweaks). I drop them from the driver in subsequent patches. * Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example, and all downstream users matched -- the binding definition was the exception. Anyway, "dmc_clk" is a more appropriately generic name. * Choose a better filename and location (this is a memory controller). Signed-off-by: Brian Norris Reviewed-by: Krzysztof Kozlowski --- Changes in v4: * Update .yaml to use more "default" entries, instead of free-form text * s/phandle-array/phandle/ * Move to .../memory-controllers, update filename Changes in v3: * Add |maxItems| for devfreq-events * Improve deprecation notes Changes in v2: * rename to 'memory-controller' in example * place 'required' after properties * drop superluous free-form references and repetitions of other bindings * fix for yamllint .../bindings/devfreq/rk3399_dmc.txt | 212 ------------ .../rockchip,rk3399-dmc.yaml | 306 ++++++++++++++++++ 2 files changed, 306 insertions(+), 212 deletions(-) delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/ro= ckchip,rk3399-dmc.yaml diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Doc= umentation/devicetree/bindings/devfreq/rk3399_dmc.txt deleted file mode 100644 index 58fc8a6cebc7..000000000000 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ /dev/null @@ -1,212 +0,0 @@ -* Rockchip rk3399 DMC (Dynamic Memory Controller) device - -Required properties: -- compatible: Must be "rockchip,rk3399-dmc". -- devfreq-events: Node to get DDR loading, Refer to - Documentation/devicetree/bindings/devfreq/event/ - rockchip-dfi.txt -- clocks: Phandles for clock specified in "clock-names" property -- clock-names : The name of clock used by the DFI, must be - "pclk_ddr_mon"; -- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp= -v2.yaml - for details. -- center-supply: DMC supply node. -- status: Marks the node enabled/disabled. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Optional properties: -- interrupts: The CPU interrupt number. The interrupt specifier - format depends on the interrupt controller. - It should be a DCF interrupt. When DDR DVFS finishes - a DCF interrupt is triggered. -- rockchip,pmu: Phandle to the syscon managing the "PMU general register - files". - -Following properties relate to DDR timing: - -- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk= 3399-ddr.h, - it selects the DDR3 cl-trp-trcd type. It must be - set according to "Speed Bin" in DDR3 datasheet, - DO NOT use a smaller "Speed Bin" than specified - for the DDR3 being used. - -- rockchip,pd_idle : Configure the PD_IDLE value. Defines the - power-down idle period in which memories are - placed into power-down mode if bus is idle - for PD_IDLE DFI clock cycles. - -- rockchip,sr_idle : Configure the SR_IDLE value. Defines the - self-refresh idle period in which memories are - placed into self-refresh mode if bus is idle - for SR_IDLE * 1024 DFI clock cycles (DFI - clocks freq is half of DRAM clock), default - value is "0". - -- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and control= ler - clock gating idle period. Memories are placed - into self-refresh mode and memory controller - clock arg gating started if bus is idle for - sr_mc_gate_idle*1024 DFI clock cycles. - -- rockchip,srpd_lite_idle : Defines the self-refresh power down idle - period in which memories are placed into - self-refresh power down mode if bus is idle - for srpd_lite_idle * 1024 DFI clock cycles. - This parameter is for LPDDR4 only. - -- rockchip,standby_idle : Defines the standby idle period in which - memories are placed into self-refresh mode. - The controller, pi, PHY and DRAM clock will - be gated if bus is idle for standby_idle * DFI - clock cycles. - -- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in = MHz. - When DDR frequency is less than DRAM_DLL_DISB_FREQ, - DDR3 DLL will be bypassed. Note: if DLL was bypassed, - the odt will also stop working. - -- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in - MHz (Mega Hz). When DDR frequency is less than - DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. - Note: PHY DLL and PHY ODT are independent. - -- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this paramete= r defines - the ODT disable frequency in MHz (Mega Hz). - when the DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines - the DRAM side driver strength in ohms. Default - value is 40. - -- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines - the DRAM side ODT strength in ohms. Default value - is 120. - -- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter = defines - the phy side CA line (incluing command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter = defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter de= fines - the PHY side ODT strength. Default value is 240. - -- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parame= ter defines - then ODT disable frequency in MHz (Mega Hz). - When DDR frequency is less then ddr3_odt_dis_freq, - the ODT on the DRAM side and controller side are - both disabled. - -- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter de= fines - the DRAM side driver strength in ohms. Default - value is 34. - -- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter de= fines - the DRAM side ODT strength in ohms. Default value - is 240. - -- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parame= ter defines - the PHY side CA line (including command line, - address line and clock line) driver strength. - Default value is 40. - -- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parame= ter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 40. - -- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter de= fine - the phy side odt strength, default value is 240. - -- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parame= ter - defines the ODT disable frequency in - MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and - controller side are both disabled. - -- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter de= fines - the DRAM side driver strength in ohms. Default - value is 60. - -- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter= defines - the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is 40. - -- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter = defines - the DRAM side ODT on CA line strength in ohms. - Default value is 40. - -- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parame= ter defines - the PHY side CA line (including command address - line) driver strength. Default value is 40. - -- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this param= eter defines - the PHY side clock line and CS line driver - strength. Default value is 80. - -- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parame= ter defines - the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is 80. - -- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter= defines - the PHY side ODT strength. Default value is 60. - -Example: - dmc_opp_table: dmc_opp_table { - compatible =3D "operating-points-v2"; - - opp00 { - opp-hz =3D /bits/ 64 <300000000>; - opp-microvolt =3D <900000>; - }; - opp01 { - opp-hz =3D /bits/ 64 <666000000>; - opp-microvolt =3D <900000>; - }; - }; - - dmc: dmc { - compatible =3D "rockchip,rk3399-dmc"; - devfreq-events =3D <&dfi>; - interrupts =3D ; - clocks =3D <&cru SCLK_DDRC>; - clock-names =3D "dmc_clk"; - operating-points-v2 =3D <&dmc_opp_table>; - center-supply =3D <&ppvar_centerlogic>; - upthreshold =3D <15>; - downdifferential =3D <10>; - rockchip,ddr3_speed_bin =3D <21>; - rockchip,pd_idle =3D <0x40>; - rockchip,sr_idle =3D <0x2>; - rockchip,sr_mc_gate_idle =3D <0x3>; - rockchip,srpd_lite_idle =3D <0x4>; - rockchip,standby_idle =3D <0x2000>; - rockchip,dram_dll_dis_freq =3D <300>; - rockchip,phy_dll_dis_freq =3D <125>; - rockchip,auto_pd_dis_freq =3D <666>; - rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,ddr3_drv =3D <40>; - rockchip,ddr3_odt =3D <120>; - rockchip,phy_ddr3_ca_drv =3D <40>; - rockchip,phy_ddr3_dq_drv =3D <40>; - rockchip,phy_ddr3_odt =3D <240>; - rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_drv =3D <34>; - rockchip,lpddr3_odt =3D <240>; - rockchip,phy_lpddr3_ca_drv =3D <40>; - rockchip,phy_lpddr3_dq_drv =3D <40>; - rockchip,phy_lpddr3_odt =3D <240>; - rockchip,lpddr4_odt_dis_freq =3D <333>; - rockchip,lpddr4_drv =3D <60>; - rockchip,lpddr4_dq_odt =3D <40>; - rockchip,lpddr4_ca_odt =3D <40>; - rockchip,phy_lpddr4_ca_drv =3D <40>; - rockchip,phy_lpddr4_ck_cs_drv =3D <80>; - rockchip,phy_lpddr4_dq_drv =3D <80>; - rockchip,phy_lpddr4_odt =3D <60>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,= rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rock= chip,rk3399-dmc.yaml new file mode 100644 index 000000000000..b32c03cb0c68 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml @@ -0,0 +1,306 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# %YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3399 DMC (Dynamic Memory Controller) device + +maintainers: + - Brian Norris + +properties: + compatible: + enum: + - rockchip,rk3399-dmc + + devfreq-events: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Node to get DDR loading. Refer to + Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dmc_clk + + operating-points-v2: true + + center-supply: + description: + DMC regulator supply. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "PMU general register files". + + interrupts: + maxItems: 1 + description: + The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS + finishes, a DCF interrupt is triggered. + + rockchip,ddr3_speed_bin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + For values, reference include/dt-bindings/clock/rk3399-ddr.h. Select= s the + DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DD= R3 + datasheet; DO NOT use a smaller "Speed Bin" than specified for the D= DR3 + being used. + + rockchip,pd_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the PD_IDLE value. Defines the power-down idle period in w= hich + memories are placed into power-down mode if bus is idle for PD_IDLE = DFI + clock cycles. + + rockchip,sr_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Configure the SR_IDLE value. Defines the self-refresh idle period in + which memories are placed into self-refresh mode if bus is idle for + SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clo= ck). + default: 0 + + rockchip,sr_mc_gate_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the memory self-refresh and controller clock gating idle per= iod. + Memories are placed into self-refresh mode and memory controller clo= ck + arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock + cycles. + + rockchip,srpd_lite_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the self-refresh power down idle period in which memories are + placed into self-refresh power down mode if bus is idle for + srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 + only. + + rockchip,standby_idle: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the standby idle period in which memories are placed into + self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted + if bus is idle for standby_idle * DFI clock cycles. + + rockchip,dram_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is = less + than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed. + Note: if DLL was bypassed, the odt will also stop working. + + rockchip,phy_dll_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR freq= uency + is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. + Note: PHY DLL and PHY ODT are independent. + + rockchip,auto_pd_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the auto PD disable frequency in MHz. + + rockchip,ddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,ddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side dri= ve + strength in ohms. + default: 40 + + rockchip,ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the DRAM side ODT + strength in ohms. + default: 120 + + rockchip,phy_ddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the phy side CA l= ine + (incluing command line, address line and clock line) drive strength. + default: 40 + + rockchip,phy_ddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side DQ l= ine + (including DQS/DQ/DM line) drive strength. + default: 40 + + rockchip,phy_ddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is DDR3, this parameter defines the PHY side ODT + strength. + default: 240 + + rockchip,lpddr3_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines then ODT disable + frequency in MHz (Mega Hz). When DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,lpddr3_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side d= rive + strength in ohms. + default: 34 + + rockchip,lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the DRAM side O= DT + strength in ohms. + default: 240 + + rockchip,phy_lpddr3_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side CA= line + (including command line, address line and clock line) drive strength. + default: 40 + + rockchip,phy_lpddr3_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR3, this parameter defines the PHY side DQ= line + (including DQS/DQ/DM line) drive strength. + default: 40 + + rockchip,phy_lpddr3_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When dram type is LPDDR3, this parameter define the phy side odt + strength, default value is 240. + + rockchip,lpddr4_odt_dis_freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the ODT disable + frequency in MHz (Mega Hz). When the DDR frequency is less then + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both + disabled. + + rockchip,lpddr4_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side d= rive + strength in ohms. + default: 60 + + rockchip,lpddr4_dq_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on + DQS/DQ line strength in ohms. + default: 40 + + rockchip,lpddr4_ca_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on + CA line strength in ohms. + default: 40 + + rockchip,phy_lpddr4_ca_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side CA= line + (including command address line) drive strength. + default: 40 + + rockchip,phy_lpddr4_ck_cs_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side cl= ock + line and CS line drive strength. + default: 80 + + rockchip,phy_lpddr4_dq_drv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side DQ= line + (including DQS/DQ/DM line) drive strength. + default: 80 + + rockchip,phy_lpddr4_odt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When the DRAM type is LPDDR4, this parameter defines the PHY side ODT + strength. + default: 60 + +required: + - compatible + - devfreq-events + - clocks + - clock-names + - operating-points-v2 + - center-supply + +additionalProperties: false + +examples: + - | + #include + #include + memory-controller { + compatible =3D "rockchip,rk3399-dmc"; + devfreq-events =3D <&dfi>; + rockchip,pmu =3D <&pmu>; + interrupts =3D ; + clocks =3D <&cru SCLK_DDRC>; + clock-names =3D "dmc_clk"; + operating-points-v2 =3D <&dmc_opp_table>; + center-supply =3D <&ppvar_centerlogic>; + rockchip,ddr3_speed_bin =3D <21>; + rockchip,pd_idle =3D <0x40>; + rockchip,sr_idle =3D <0x2>; + rockchip,sr_mc_gate_idle =3D <0x3>; + rockchip,srpd_lite_idle =3D <0x4>; + rockchip,standby_idle =3D <0x2000>; + rockchip,dram_dll_dis_freq =3D <300>; + rockchip,phy_dll_dis_freq =3D <125>; + rockchip,auto_pd_dis_freq =3D <666>; + rockchip,ddr3_odt_dis_freq =3D <333>; + rockchip,ddr3_drv =3D <40>; + rockchip,ddr3_odt =3D <120>; + rockchip,phy_ddr3_ca_drv =3D <40>; + rockchip,phy_ddr3_dq_drv =3D <40>; + rockchip,phy_ddr3_odt =3D <240>; + rockchip,lpddr3_odt_dis_freq =3D <333>; + rockchip,lpddr3_drv =3D <34>; + rockchip,lpddr3_odt =3D <240>; + rockchip,phy_lpddr3_ca_drv =3D <40>; + rockchip,phy_lpddr3_dq_drv =3D <40>; + rockchip,phy_lpddr3_odt =3D <240>; + rockchip,lpddr4_odt_dis_freq =3D <333>; + rockchip,lpddr4_drv =3D <60>; + rockchip,lpddr4_dq_odt =3D <40>; + rockchip,lpddr4_ca_odt =3D <40>; + rockchip,phy_lpddr4_ca_drv =3D <40>; + rockchip,phy_lpddr4_ck_cs_drv =3D <80>; + rockchip,phy_lpddr4_dq_drv =3D <80>; + rockchip,phy_lpddr4_odt =3D <60>; + }; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 358EBC433FE for ; Tue, 8 Mar 2022 19:09:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349888AbiCHTKU (ORCPT ); Tue, 8 Mar 2022 14:10:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349867AbiCHTKN (ORCPT ); Tue, 8 Mar 2022 14:10:13 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9CBC3ED00 for ; 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Tue, 08 Mar 2022 11:09:14 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id p16-20020a056a000b5000b004f669806cd9sm21407488pfo.87.2022.03.08.11.09.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:13 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 02/15] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Tue, 8 Mar 2022 11:08:48 -0800 Message-Id: <20220308110825.v4.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- Changes in v4: * Add Reviewed-by Changes in v3: * Add Reviewed-by .../rockchip,rk3399-dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,= rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rock= chip,rk3399-dmc.yaml index b32c03cb0c68..356bbe5db383 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml @@ -45,6 +45,7 @@ properties: finishes, a DCF interrupt is triggered. =20 rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Select= s the @@ -91,6 +92,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. =20 rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is = less @@ -98,6 +100,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. =20 rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR freq= uency @@ -105,6 +108,7 @@ properties: Note: PHY DLL and PHY ODT are independent. =20 rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -118,6 +122,7 @@ properties: disabled. =20 rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side dri= ve @@ -125,6 +130,7 @@ properties: default: 40 =20 rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT @@ -132,6 +138,7 @@ properties: default: 120 =20 rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA l= ine @@ -139,6 +146,7 @@ properties: default: 40 =20 rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ l= ine @@ -146,6 +154,7 @@ properties: default: 40 =20 rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -161,6 +170,7 @@ properties: disabled. =20 rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side d= rive @@ -168,6 +178,7 @@ properties: default: 34 =20 rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side O= DT @@ -175,6 +186,7 @@ properties: default: 240 =20 rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA= line @@ -182,6 +194,7 @@ properties: default: 40 =20 rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ= line @@ -189,6 +202,7 @@ properties: default: 40 =20 rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -203,6 +217,7 @@ properties: disabled. =20 rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side d= rive @@ -210,6 +225,7 @@ properties: default: 60 =20 rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on @@ -217,6 +233,7 @@ properties: default: 40 =20 rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side O= DT on @@ -224,6 +241,7 @@ properties: default: 40 =20 rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA= line @@ -231,6 +249,7 @@ properties: default: 40 =20 rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side cl= ock @@ -238,6 +257,7 @@ properties: default: 80 =20 rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ= line @@ -245,6 +265,7 @@ properties: default: 80 =20 rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -274,33 +295,12 @@ examples: clock-names =3D "dmc_clk"; operating-points-v2 =3D <&dmc_opp_table>; center-supply =3D <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin =3D <21>; rockchip,pd_idle =3D <0x40>; rockchip,sr_idle =3D <0x2>; rockchip,sr_mc_gate_idle =3D <0x3>; rockchip,srpd_lite_idle =3D <0x4>; rockchip,standby_idle =3D <0x2000>; - rockchip,dram_dll_dis_freq =3D <300>; - rockchip,phy_dll_dis_freq =3D <125>; - rockchip,auto_pd_dis_freq =3D <666>; rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,ddr3_drv =3D <40>; - rockchip,ddr3_odt =3D <120>; - rockchip,phy_ddr3_ca_drv =3D <40>; - rockchip,phy_ddr3_dq_drv =3D <40>; - rockchip,phy_ddr3_odt =3D <240>; rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_drv =3D <34>; - rockchip,lpddr3_odt =3D <240>; - rockchip,phy_lpddr3_ca_drv =3D <40>; - rockchip,phy_lpddr3_dq_drv =3D <40>; - rockchip,phy_lpddr3_odt =3D <240>; rockchip,lpddr4_odt_dis_freq =3D <333>; - rockchip,lpddr4_drv =3D <60>; - rockchip,lpddr4_dq_odt =3D <40>; - rockchip,lpddr4_ca_odt =3D <40>; - rockchip,phy_lpddr4_ca_drv =3D <40>; - rockchip,phy_lpddr4_ck_cs_drv =3D <80>; - rockchip,phy_lpddr4_dq_drv =3D <80>; - rockchip,phy_lpddr4_odt =3D <60>; }; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8A9BC433EF for ; Tue, 8 Mar 2022 19:09:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349891AbiCHTKX (ORCPT ); Tue, 8 Mar 2022 14:10:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349875AbiCHTKO (ORCPT ); Tue, 8 Mar 2022 14:10:14 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F45248E43 for ; Tue, 8 Mar 2022 11:09:16 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id gj15-20020a17090b108f00b001bef86c67c1so193888pjb.3 for ; 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Tue, 08 Mar 2022 11:09:16 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id d7-20020a056a00244700b004e1300a2f7csm20703284pfj.212.2022.03.08.11.09.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:16 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 03/15] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Date: Tue, 8 Mar 2022 11:08:49 -0800 Message-Id: <20220308110825.v4.3.I9341269171c114d0e04e41d48037fd32816e2d8c@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The driver and all downstream device trees [1] are using Hz units, but the document claims MHz. DRAM frequency for these systems can't possibly exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much. Rather than add unnecessary risk in getting the units wrong, let's just go with the unofficial convention and make the docs match reality. A sub-1MHz frequency is extremely unlikely, so include a minimum in the schema, to help catch anybody who might have believed this was MHz. [1] And notably, also those trying to upstream them: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.o= rg/ Signed-off-by: Brian Norris Reviewed-by: Rob Herring Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- (no changes since v3) Changes in v3: * Add Reviewed-by, Acked-by .../rockchip,rk3399-dmc.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,= rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rock= chip,rk3399-dmc.yaml index 356bbe5db383..96efb23cfc0f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml @@ -115,11 +115,11 @@ properties: =20 rockchip,ddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is DDR3, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_fr= eq, + the ODT on the DRAM side and controller side are both disabled. =20 rockchip,ddr3_drv: deprecated: true @@ -163,11 +163,11 @@ properties: =20 rockchip,lpddr3_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR3, this parameter defines then ODT disable - frequency in MHz (Mega Hz). When DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, = the + ODT on the DRAM side and controller side are both disabled. =20 rockchip,lpddr3_drv: deprecated: true @@ -210,11 +210,11 @@ properties: =20 rockchip,lpddr4_odt_dis_freq: $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1000000 # In case anyone thought this was MHz. description: When the DRAM type is LPDDR4, this parameter defines the ODT disable - frequency in MHz (Mega Hz). When the DDR frequency is less then - ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are = both - disabled. + frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_fr= eq, + the ODT on the DRAM side and controller side are both disabled. =20 rockchip,lpddr4_drv: deprecated: true @@ -300,7 +300,7 @@ examples: rockchip,sr_mc_gate_idle =3D <0x3>; rockchip,srpd_lite_idle =3D <0x4>; rockchip,standby_idle =3D <0x2000>; - rockchip,ddr3_odt_dis_freq =3D <333>; - rockchip,lpddr3_odt_dis_freq =3D <333>; - rockchip,lpddr4_odt_dis_freq =3D <333>; + rockchip,ddr3_odt_dis_freq =3D <333000000>; + rockchip,lpddr3_odt_dis_freq =3D <333000000>; + rockchip,lpddr4_odt_dis_freq =3D <333000000>; }; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72669C433EF for ; Tue, 8 Mar 2022 19:09:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349915AbiCHTKZ (ORCPT ); Tue, 8 Mar 2022 14:10:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236771AbiCHTKQ (ORCPT ); Tue, 8 Mar 2022 14:10:16 -0500 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D1CB4927C for ; Tue, 8 Mar 2022 11:09:19 -0800 (PST) Received: by mail-pf1-x42d.google.com with SMTP id g19so180942pfc.9 for ; Tue, 08 Mar 2022 11:09:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aQBXnYV77u8nGKn/MzXkBt16/3DAVGbxcTfsybprNzY=; b=mCBxWxx6dpCtH8y2eYwy4bA86huPX44nffjFiMfYcPzNPGzEFjY5/isggSYFRHymfA SuD4SuNPjNsJ0gkJYzcGgdErOmEBtQK42eAtTXzl0CzUbbb3DU6mP7Wjcl3SNwJ+5LLY wSdrD/ZIqmJZP1nklPmE9Wmp+ikm+Mt4f1pKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aQBXnYV77u8nGKn/MzXkBt16/3DAVGbxcTfsybprNzY=; b=u74E2ieEddWHT5mfNi8YZGr8rZ67jDXQtgSYhBj1Zr/5lhraGl7fEXHouPbANBYfd2 Qm9YS3vFR+PqInwMBl5Di/9RqhcDzkXzY/e1l84w3I2P7ig/WzWdYIO4FR7uZKPjRhBq PbIRy2AdjjvrwEs26/8BCtuCYIR2T3OXrZeZ0mGS+RyAnFY8HqzRKh5QxM3CSjfH1K9Z vacJrXSItmQ/KcTukoinSEi5GbM+Ijpxnuujj9A/JhrntpCpAX6TqHu9NCtyp2pFLsgd 2SmnACsTXwtrl9kGlA0PcaJtueYJtv3eYS8VxU8x/sxCLxg7Nph3Inv2psef39pu/Ats Od4Q== X-Gm-Message-State: AOAM533RSQ7G5D1T9wdhALdMuXt+E+1LXQIF9qSTlZH+4JquUXArW1Vz +WB9/rnTernoEr61azCreZGBfA== X-Google-Smtp-Source: ABdhPJy2G8NKjzBfMuq+zr/kLWgKLJwymWEQdXwGWRkQT7dOHPkeLllLbPtznYqzy9tlAdivDeqCgA== X-Received: by 2002:a05:6a00:1490:b0:4f6:f2bd:1dd3 with SMTP id v16-20020a056a00149000b004f6f2bd1dd3mr13949465pfu.58.1646766558818; Tue, 08 Mar 2022 11:09:18 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id p186-20020a62d0c3000000b004f6fa49c4b9sm9110384pfg.218.2022.03.08.11.09.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:18 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 04/15] dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds Date: Tue, 8 Mar 2022 11:08:50 -0800 Message-Id: <20220308110825.v4.4.I01c6a2b2db578136686b42d463af985cfdff2fd9@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's inefficient to use the same number of cycles for all OPPs, since lower frequencies make for longer idle times. Let's specify the idle time instead, so software can pick the optimal number of cycles on its own. NB: these bindings aren't used anywhere yet. Signed-off-by: Brian Norris Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- Changes in v4: * Use 'default:' Changes in v3: * Add Reviewed-by Changes in v2: * New patch .../rockchip,rk3399-dmc.yaml | 51 +++++++++++++++++-- 1 file changed, 46 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,= rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rock= chip,rk3399-dmc.yaml index 96efb23cfc0f..5228a32b5962 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml @@ -54,42 +54,52 @@ properties: being used. =20 rockchip,pd_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Configure the PD_IDLE value. Defines the power-down idle period in w= hich memories are placed into power-down mode if bus is idle for PD_IDLE = DFI clock cycles. + See also rockchip,pd-idle-ns. =20 rockchip,sr_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Configure the SR_IDLE value. Defines the self-refresh idle period in which memories are placed into self-refresh mode if bus is idle for SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clo= ck). + See also rockchip,sr-idle-ns. default: 0 =20 rockchip,sr_mc_gate_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the memory self-refresh and controller clock gating idle per= iod. Memories are placed into self-refresh mode and memory controller clo= ck arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock cycles. + See also rockchip,sr-mc-gate-idle-ns. =20 rockchip,srpd_lite_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the self-refresh power down idle period in which memories are placed into self-refresh power down mode if bus is idle for srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4 only. + See also rockchip,srpd-lite-idle-ns. =20 rockchip,standby_idle: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the standby idle period in which memories are placed into self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted if bus is idle for standby_idle * DFI clock cycles. + See also rockchip,standby-idle-ns. =20 rockchip,dram_dll_dis_freq: deprecated: true @@ -272,6 +282,37 @@ properties: strength. default: 60 =20 + rockchip,pd-idle-ns: + description: + Configure the PD_IDLE value in nanoseconds. Defines the power-down i= dle + period in which memories are placed into power-down mode if bus is i= dle + for PD_IDLE nanoseconds. + + rockchip,sr-idle-ns: + description: + Configure the SR_IDLE value in nanoseconds. Defines the self-refresh= idle + period in which memories are placed into self-refresh mode if bus is= idle + for SR_IDLE nanoseconds. + default: 0 + + rockchip,sr-mc-gate-idle-ns: + description: + Defines the memory self-refresh and controller clock gating idle per= iod in nanoseconds. + Memories are placed into self-refresh mode and memory controller clo= ck + arg gating started if bus is idle for sr_mc_gate_idle nanoseconds. + + rockchip,srpd-lite-idle-ns: + description: + Defines the self-refresh power down idle period in which memories are + placed into self-refresh power down mode if bus is idle for + srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only. + + rockchip,standby-idle-ns: + description: + Defines the standby idle period in which memories are placed into + self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted + if bus is idle for standby_idle nanoseconds. + required: - compatible - devfreq-events @@ -295,11 +336,11 @@ examples: clock-names =3D "dmc_clk"; operating-points-v2 =3D <&dmc_opp_table>; center-supply =3D <&ppvar_centerlogic>; - rockchip,pd_idle =3D <0x40>; - rockchip,sr_idle =3D <0x2>; - rockchip,sr_mc_gate_idle =3D <0x3>; - rockchip,srpd_lite_idle =3D <0x4>; - rockchip,standby_idle =3D <0x2000>; + rockchip,pd-idle-ns =3D <160>; + rockchip,sr-idle-ns =3D <10240>; + rockchip,sr-mc-gate-idle-ns =3D <40960>; + rockchip,srpd-lite-idle-ns =3D <61440>; + rockchip,standby-idle-ns =3D <81920>; rockchip,ddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr4_odt_dis_freq =3D <333000000>; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3576FC433EF for ; Tue, 8 Mar 2022 19:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242699AbiCHTKc (ORCPT ); Tue, 8 Mar 2022 14:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349890AbiCHTKV (ORCPT ); Tue, 8 Mar 2022 14:10:21 -0500 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8783649683 for ; Tue, 8 Mar 2022 11:09:22 -0800 (PST) Received: by mail-pf1-x42a.google.com with SMTP id z16so209828pfh.3 for ; Tue, 08 Mar 2022 11:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xCLmej3ASMhCzoCjalBeE7MlVyXBTYUNm6WHWDyRzJ4=; b=XDxUtkkfguKIpXdJtQdm6/VFWj2zLR4nvCC+0mQOD1nG8UWWuJtvxLFJSelx48So8/ 66H2OCtsTdV6g29lwJmEt5CJMSshQHOS1qfTmOKQD3b3ZYUko5of7V74eu/cJVQgASvs rmxjzOezqwaAQM7J+RErQlYt4E0WjG1SXP94E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xCLmej3ASMhCzoCjalBeE7MlVyXBTYUNm6WHWDyRzJ4=; b=bGLPWh3YMOeSC0H5wKsf2qOu9lXVuT9YYUiZpL8SZQtAmqVkIfP9CfMCU6DM3eQaPu 8D/2AQSiBMTCQhQdAz2uL9EYTUidm0C8nun9HAwKuYvE8RdmFVSI/b3WxZ15qswMP3GF h+JAaKeXCMYpcu/09L9wCdRoFy7WpgUJPKQrB687Ok+Eb48WlLCmqNP0ykqA3FooW8C9 M/KTS5x9TX5gwZG30P8yFSPUMgI9O8lRWvAvUbkop6VNYFCwjo0Of8x3sxn0moxnZZZl zwobzE19MX6ckyTCSNRwu9NhrjqXZiy1S0+3RxtrB/f5jMSXfUDfsur1zQVuLuPU1Nlx 9Kjg== X-Gm-Message-State: AOAM530BKxldGIchB5pGUPtGCv0CFrlFKiwjc96Aw96HSMnVM//wx5UK hjfWLBIMHU/tRHbqL8bsjXwyAQ== X-Google-Smtp-Source: ABdhPJxUPpHD0D1g6CmnuNEbS2Y2kpd0VWcLBfHdpnesyIyVAd6VCoGpyggUrB52V0mZ5oxLHPWk3w== X-Received: by 2002:a62:bd05:0:b0:4f7:aec:dd7e with SMTP id a5-20020a62bd05000000b004f70aecdd7emr9923561pff.9.1646766561672; Tue, 08 Mar 2022 11:09:21 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id l2-20020a637c42000000b003644cfa0dd1sm15180460pgn.79.2022.03.08.11.09.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:21 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 05/15] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Date: Tue, 8 Mar 2022 11:08:51 -0800 Message-Id: <20220308110825.v4.5.I382d4de737198ea52deb118c9bdc4d93d76e009e@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DDR DVFS tuning has found that several power-saving features don't have good tradeoffs at higher frequencies -- at higher frequencies, we'll see glitches or other errors. Provide tuning controls so these can be disabled at higher OPPs, and left active only at the lower ones. Signed-off-by: Brian Norris Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- (no changes since v3) Changes in v3: * Add Reviewed-by Changes in v2: * hyphens, not underscores * *-hz units, and drop the types definition .../rockchip,rk3399-dmc.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,= rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rock= chip,rk3399-dmc.yaml index 5228a32b5962..fb4920397d08 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-= dmc.yaml @@ -313,6 +313,38 @@ properties: self-refresh mode. The controller, pi, PHY and DRAM clock will be ga= ted if bus is idle for standby_idle nanoseconds. =20 + rockchip,pd-idle-dis-freq-hz: + description: + Defines the power-down idle disable frequency in Hz. When the DDR + frequency is greater than pd-idle-dis-freq, power-down idle is disab= led. + See also rockchip,pd-idle-ns. + + rockchip,sr-idle-dis-freq-hz: + description: + Defines the self-refresh idle disable frequency in Hz. When the DDR + frequency is greater than sr-idle-dis-freq, self-refresh idle is + disabled. See also rockchip,sr-idle-ns. + + rockchip,sr-mc-gate-idle-dis-freq-hz: + description: + Defines the self-refresh and memory-controller clock gating disable + frequency in Hz. When the DDR frequency is greater than + sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See= also + rockchip,sr-mc-gate-idle-ns. + + rockchip,srpd-lite-idle-dis-freq-hz: + description: + Defines the self-refresh power down idle disable frequency in Hz. Wh= en + the DDR frequency is greater than srpd-lite-idle-dis-freq, memory wi= ll + not be placed into self-refresh power down mode when idle. See also + rockchip,srpd-lite-idle-ns. + + rockchip,standby-idle-dis-freq-hz: + description: + Defines the standby idle disable frequency in Hz. When the DDR frequ= ency + is greater than standby-idle-dis-freq, standby idle is disabled. See= also + rockchip,standby-idle-ns. + required: - compatible - devfreq-events @@ -344,4 +376,9 @@ examples: rockchip,ddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr3_odt_dis_freq =3D <333000000>; rockchip,lpddr4_odt_dis_freq =3D <333000000>; + rockchip,pd-idle-dis-freq-hz =3D <1000000000>; + rockchip,sr-idle-dis-freq-hz =3D <1000000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz =3D <0>; + rockchip,standby-idle-dis-freq-hz =3D <928000000>; }; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0059C433F5 for ; Tue, 8 Mar 2022 19:09:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230134AbiCHTKf (ORCPT ); Tue, 8 Mar 2022 14:10:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349873AbiCHTKW (ORCPT ); Tue, 8 Mar 2022 14:10:22 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9437F4A914 for ; Tue, 8 Mar 2022 11:09:24 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id m11-20020a17090a7f8b00b001beef6143a8so189513pjl.4 for ; Tue, 08 Mar 2022 11:09:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NhX5SlYl7BXLmMZAasTyx4ByzRymbQLodzBvBVJqn84=; b=ia6LpA7WceZ4f03km26fJVpfZ4ixhMsuxFoCfP9TgIF8ypocAYjFCdR+s8YnhP9Zy4 jCokCj4KV0dQ+s1mkZorQ2Os1jPQWNUQXHIDTUeYkJ0atBuLmIRbSOWR+ArgHYQGuOun QFhYo1L4C86o/w+h6WiPFMaRdpqNiP0+L5PqM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NhX5SlYl7BXLmMZAasTyx4ByzRymbQLodzBvBVJqn84=; b=OB1y2IoZqHOU6Zz3UIWTC9B7Scf44s/cdVzUIYBCQtSdOaMaQI/nlo2gZ6qnn7xdhm DSPr7J6v0uaL643qIaiqCdb3jPuuJbXTfedi1NXpq48XgSDLQcnPcr8ranERlGumPV86 06/XuYxHAdme+LNxkfI9jYArfZgIrzU4EvLJHJHw5ZOcRkX4slLNFoulNtPhP6YLhSTn VgufarN9AMYqbAa2T6Y5puiQl6R1XbYmnSUO1Z1t3PzkTH8NCUwN8KZ1ee3Sy74GiTx9 Xc0bDWHPDbRTeWVxS6aP3fIRogSmIfPnJwHazAc6MTQ8tEg0PgN2a9uyNMXOZFpq0QcE RxpQ== X-Gm-Message-State: AOAM533FQA6xN+DgfTAeivnZAdKHe04QQGlmD0MrQEng9iDrWIj3Pw18 35q0vI19ZxjLMVpk4jOMyKy2wmZPNh1QFg== X-Google-Smtp-Source: ABdhPJwHFfOX969K7axpRvKBZTipkQuA9fBVIEHWS27NildAkKpn5ETWs6/B2N5QI1yzAw3MwfofWw== X-Received: by 2002:a17:902:7e4d:b0:14f:e295:5a41 with SMTP id a13-20020a1709027e4d00b0014fe2955a41mr18835755pln.27.1646766564094; Tue, 08 Mar 2022 11:09:24 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id w23-20020a627b17000000b004f6cf170070sm13970753pfc.186.2022.03.08.11.09.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:23 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 06/15] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props Date: Tue, 8 Mar 2022 11:08:52 -0800 Message-Id: <20220308110825.v4.6.I4bd77eb751d5bfce8346bfed576bcacb28e4550f@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These properties are: * undocumented * directly representing software properties, not hardware properties * unused (no in-tree users, yet; this IP block has so far only been used in downstream kernels) Let's just stick the values that downstream users have been using directly in the driver and call it a day. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 293857ebfd75..e982862f6ac2 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -430,10 +430,8 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) goto err_edev; } =20 - of_property_read_u32(np, "upthreshold", - &data->ondemand_data.upthreshold); - of_property_read_u32(np, "downdifferential", - &data->ondemand_data.downdifferential); + data->ondemand_data.upthreshold =3D 25; + data->ondemand_data.downdifferential =3D 15; =20 data->rate =3D clk_get_rate(data->dmc_clk); =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E60BC433EF for ; Tue, 8 Mar 2022 19:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349460AbiCHTKo (ORCPT ); Tue, 8 Mar 2022 14:10:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349911AbiCHTKZ (ORCPT ); Tue, 8 Mar 2022 14:10:25 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04BBD4A3CE for ; Tue, 8 Mar 2022 11:09:26 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id d17so197593pfv.6 for ; Tue, 08 Mar 2022 11:09:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MGvJc+Ve3oy0Yq0K3bpgSkrQ5JxGu0c98z8DVJNiX8g=; b=NOrGr4vMwXpdp5J0k2X41Gy+WSY8DEp7MQcwRe2e3Dx3IMs3z4xNrxyR+7wx2wGxNB d7VtVskm1B4sNzZoz2CBQ+GPTaIPpU2iG2EQ78RYY43K659GFbd3uwIbhK/LB7FH6Y2h e8CKd2TsZ6BW9wRAAqH+xrnTt+g5dK3qDls/Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MGvJc+Ve3oy0Yq0K3bpgSkrQ5JxGu0c98z8DVJNiX8g=; b=wY6rpat3VuXr9XFAAKhTwYZ21Zf5JpbhvDR8H74SkCKUVHrG8Cj0fwaKv0/U+sg2Zu M3mKFxCoJtQbiLhytgMrxBypmgNqqUj6X8yRhBonuR45wc02TeMBb8Y1g2kc9Nr2k4pC p2P43U9nrUgMjknuFKbYp+3EJYOB71HMNQeYB+3GMTxTK2/tjXwzCzmo6aFKoypD8ctx JJ+qPzg0h+GgRyuMTKDZKDewhpA88ix9uxftccHiivKyiL6PF0IIgGSfdAI8pA2AaJQs 0ePB8DU3K3ofF5kIzJSFSq882K0uk2SYXCJCmga3wio1qTPWjXyJEZxiEEUwu633jnGJ ttog== X-Gm-Message-State: AOAM531laa27iQ3z8KQS5pVKTyfObgWnCtqZi3sy7S1V/ZKxSAE4Xme6 Jp4q/c+kb1BRxHiSk5dQAn+vNA== X-Google-Smtp-Source: ABdhPJxxzJ/Hw8tQQls00LevA33RIKViziiy3kGxSNaj5N/yoBMPP2JAvI9Q6tzRCqvYRxHuZcX4hQ== X-Received: by 2002:a63:f04f:0:b0:373:bd70:af2 with SMTP id s15-20020a63f04f000000b00373bd700af2mr15219130pgj.497.1646766566341; Tue, 08 Mar 2022 11:09:26 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id k1-20020a056a00168100b004e0e45a39c6sm21486873pfc.181.2022.03.08.11.09.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:25 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 07/15] PM / devfreq: rk3399_dmc: Drop excess timing properties Date: Tue, 8 Mar 2022 11:08:53 -0800 Message-Id: <20220308110825.v4.7.Ia0f7d6168a71ba4a4fd0519972a8dfd4c681fc25@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of these properties are initialized by ARM Trusted Firmware, and have been since the early days of this chip. It's redundant (and possibly wrong) to do this here now. What's more, there seems to be some confusion about the units and some of the definitions of this timing struct: the DT docs say MHz for many of these, but downstream users were in Hz (and therefore, the ATF interface was Hz). Also, the in-driver usage for some of these (e.g., for comparing to target frequency) were in Hz too. So doubly wrong. We can avoid thinking about who got the right units by dropping the unnecessary code and properties. They are marked deprecated in the binding schema. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 144 +++++++---------------------------- 1 file changed, 29 insertions(+), 115 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index e982862f6ac2..8f447217303f 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -23,38 +23,6 @@ #include #include =20 -struct dram_timing { - unsigned int ddr3_speed_bin; - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; - unsigned int auto_pd_dis_freq; - unsigned int dram_dll_dis_freq; - unsigned int phy_dll_dis_freq; - unsigned int ddr3_odt_dis_freq; - unsigned int ddr3_drv; - unsigned int ddr3_odt; - unsigned int phy_ddr3_ca_drv; - unsigned int phy_ddr3_dq_drv; - unsigned int phy_ddr3_odt; - unsigned int lpddr3_odt_dis_freq; - unsigned int lpddr3_drv; - unsigned int lpddr3_odt; - unsigned int phy_lpddr3_ca_drv; - unsigned int phy_lpddr3_dq_drv; - unsigned int phy_lpddr3_odt; - unsigned int lpddr4_odt_dis_freq; - unsigned int lpddr4_drv; - unsigned int lpddr4_dq_odt; - unsigned int lpddr4_ca_odt; - unsigned int phy_lpddr4_ca_drv; - unsigned int phy_lpddr4_ck_cs_drv; - unsigned int phy_lpddr4_dq_drv; - unsigned int phy_lpddr4_odt; -}; - struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -62,13 +30,21 @@ struct rk3399_dmcfreq { struct clk *dmc_clk; struct devfreq_event_dev *edev; struct mutex lock; - struct dram_timing timing; struct regulator *vdd_center; struct regmap *regmap_pmu; unsigned long rate, target_rate; unsigned long volt, target_volt; unsigned int odt_dis_freq; int odt_pd_arg0, odt_pd_arg1; + + unsigned int pd_idle; + unsigned int sr_idle; + unsigned int sr_mc_gate_idle; + unsigned int srpd_lite_idle; + unsigned int standby_idle; + unsigned int ddr3_odt_dis_freq; + unsigned int lpddr3_odt_dis_freq; + unsigned int lpddr4_odt_dis_freq; }; =20 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -238,69 +214,27 @@ static __maybe_unused int rk3399_dmcfreq_resume(struc= t device *dev) static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, rk3399_dmcfreq_resume); =20 -static int of_get_ddr_timings(struct dram_timing *timing, - struct device_node *np) +static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, + struct device_node *np) { int ret =3D 0; =20 - ret =3D of_property_read_u32(np, "rockchip,ddr3_speed_bin", - &timing->ddr3_speed_bin); ret |=3D of_property_read_u32(np, "rockchip,pd_idle", - &timing->pd_idle); + &data->pd_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_idle", - &timing->sr_idle); + &data->sr_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_mc_gate_idle", - &timing->sr_mc_gate_idle); + &data->sr_mc_gate_idle); ret |=3D of_property_read_u32(np, "rockchip,srpd_lite_idle", - &timing->srpd_lite_idle); + &data->srpd_lite_idle); ret |=3D of_property_read_u32(np, "rockchip,standby_idle", - &timing->standby_idle); - ret |=3D of_property_read_u32(np, "rockchip,auto_pd_dis_freq", - &timing->auto_pd_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,dram_dll_dis_freq", - &timing->dram_dll_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,phy_dll_dis_freq", - &timing->phy_dll_dis_freq); + &data->standby_idle); ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", - &timing->ddr3_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,ddr3_drv", - &timing->ddr3_drv); - ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt", - &timing->ddr3_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", - &timing->phy_ddr3_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", - &timing->phy_ddr3_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_ddr3_odt", - &timing->phy_ddr3_odt); + &data->ddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", - &timing->lpddr3_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,lpddr3_drv", - &timing->lpddr3_drv); - ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt", - &timing->lpddr3_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", - &timing->phy_lpddr3_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", - &timing->phy_lpddr3_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr3_odt", - &timing->phy_lpddr3_odt); + &data->lpddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", - &timing->lpddr4_odt_dis_freq); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_drv", - &timing->lpddr4_drv); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_dq_odt", - &timing->lpddr4_dq_odt); - ret |=3D of_property_read_u32(np, "rockchip,lpddr4_ca_odt", - &timing->lpddr4_ca_odt); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", - &timing->phy_lpddr4_ca_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", - &timing->phy_lpddr4_ck_cs_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", - &timing->phy_lpddr4_dq_drv); - ret |=3D of_property_read_u32(np, "rockchip,phy_lpddr4_odt", - &timing->phy_lpddr4_odt); + &data->lpddr4_odt_dis_freq); =20 return ret; } @@ -311,8 +245,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D pdev->dev.of_node, *node; struct rk3399_dmcfreq *data; - int ret, index, size; - uint32_t *timing; + int ret; struct dev_pm_opp *opp; u32 ddr_type; u32 val; @@ -343,26 +276,7 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) return ret; } =20 - /* - * Get dram timing and pass it to arm trust firmware, - * the dram driver in arm trust firmware will get these - * timing and to do dram initial. - */ - if (!of_get_ddr_timings(&data->timing, np)) { - timing =3D &data->timing.ddr3_speed_bin; - size =3D sizeof(struct dram_timing) / 4; - for (index =3D 0; index < size; index++) { - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, - ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, - 0, 0, 0, 0, &res); - if (res.a0) { - dev_err(dev, "Failed to set dram param: %ld\n", - res.a0); - ret =3D -EINVAL; - goto err_edev; - } - } - } + rk3399_dmcfreq_of_props(data, np); =20 node =3D of_parse_phandle(np, "rockchip,pmu", 0); if (!node) @@ -381,13 +295,13 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) =20 switch (ddr_type) { case RK3399_PMUGRF_DDRTYPE_DDR3: - data->odt_dis_freq =3D data->timing.ddr3_odt_dis_freq; + data->odt_dis_freq =3D data->ddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR3: - data->odt_dis_freq =3D data->timing.lpddr3_odt_dis_freq; + data->odt_dis_freq =3D data->lpddr3_odt_dis_freq; break; case RK3399_PMUGRF_DDRTYPE_LPDDR4: - data->odt_dis_freq =3D data->timing.lpddr4_odt_dis_freq; + data->odt_dis_freq =3D data->lpddr4_odt_dis_freq; break; default: ret =3D -EINVAL; @@ -414,11 +328,11 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) * arg2: * bit[0] : odt enable */ - data->odt_pd_arg0 =3D (data->timing.sr_idle & 0xff) | - ((data->timing.sr_mc_gate_idle & 0xff) << 8) | - ((data->timing.standby_idle & 0xffff) << 16); - data->odt_pd_arg1 =3D (data->timing.pd_idle & 0xfff) | - ((data->timing.srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 =3D (data->sr_idle & 0xff) | + ((data->sr_mc_gate_idle & 0xff) << 8) | + ((data->standby_idle & 0xffff) << 16); + data->odt_pd_arg1 =3D (data->pd_idle & 0xfff) | + ((data->srpd_lite_idle & 0xfff) << 16); =20 /* * We add a devfreq driver to our parent since it has a device tree node --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD193C433EF for ; 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Tue, 08 Mar 2022 11:09:28 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 08/15] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD Date: Tue, 8 Mar 2022 11:08:54 -0800 Message-Id: <20220308110825.v4.8.I0f36da588afd01d0dc9ce5866240efa34bd91e21@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We're going to add new usages, and it's cleaner to work with macros instead of comments and magic numbers. Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 43 ++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 8f447217303f..c4efbc15cbb1 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -23,6 +24,15 @@ #include #include =20 +#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) +#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) +#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) + +#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0) +#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16) + +#define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0) + struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; @@ -55,7 +65,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsi= gned long *freq, unsigned long old_clk_rate =3D dmcfreq->rate; unsigned long target_volt, target_rate; struct arm_smccc_res res; - bool odt_enable =3D false; int err; =20 opp =3D devfreq_recommended_opp(dev, freq, flags); @@ -72,8 +81,10 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, mutex_lock(&dmcfreq->lock); =20 if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg2 =3D 0; + if (target_rate >=3D dmcfreq->odt_dis_freq) - odt_enable =3D true; + odt_pd_arg2 |=3D RK3399_SET_ODT_PD_2_ODT_ENABLE; =20 /* * This makes a SMC call to the TF-A to set the DDR PD @@ -83,7 +94,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsi= gned long *freq, arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, dmcfreq->odt_pd_arg1, ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_enable, 0, 0, 0, &res); + odt_pd_arg2, 0, 0, 0, &res); } =20 /* @@ -316,23 +327,17 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) /* * In TF-A there is a platform SIP call to set the PD (power-down) * timings and to enable or disable the ODT (on-die termination). - * This call needs three arguments as follows: - * - * arg0: - * bit[0-7] : sr_idle - * bit[8-15] : sr_mc_gate_idle - * bit[16-31] : standby idle - * arg1: - * bit[0-11] : pd_idle - * bit[16-27] : srpd_lite_idle - * arg2: - * bit[0] : odt enable */ - data->odt_pd_arg0 =3D (data->sr_idle & 0xff) | - ((data->sr_mc_gate_idle & 0xff) << 8) | - ((data->standby_idle & 0xffff) << 16); - data->odt_pd_arg1 =3D (data->pd_idle & 0xfff) | - ((data->srpd_lite_idle & 0xfff) << 16); + data->odt_pd_arg0 =3D + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE, + data->sr_mc_gate_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE, + data->standby_idle); + data->odt_pd_arg1 =3D + FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) | + FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE, + data->srpd_lite_idle); =20 /* * We add a devfreq driver to our parent since it has a device tree node --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FF3AC433EF for ; Tue, 8 Mar 2022 19:10:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349075AbiCHTK4 (ORCPT ); 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Tue, 08 Mar 2022 11:09:30 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 09/15] PM / devfreq: rk3399_dmc: Support new disable-freq properties Date: Tue, 8 Mar 2022 11:08:55 -0800 Message-Id: <20220308110825.v4.9.I08d654522b8a1ae92ecb8d2e2a74511f778f61e5@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the newly-defined properties to allow disabling certain power-saving-at-idle features at higher frequencies. This is a rewritten version of work by Lin Huang . Signed-off-by: Brian Norris --- (no changes since v1) drivers/devfreq/rk3399_dmc.c | 51 +++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index c4efbc15cbb1..fc740c1f6747 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -55,6 +55,12 @@ struct rk3399_dmcfreq { unsigned int ddr3_odt_dis_freq; unsigned int lpddr3_odt_dis_freq; unsigned int lpddr4_odt_dis_freq; + + unsigned int pd_idle_dis_freq; + unsigned int sr_idle_dis_freq; + unsigned int sr_mc_gate_idle_dis_freq; + unsigned int srpd_lite_idle_dis_freq; + unsigned int standby_idle_dis_freq; }; =20 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, @@ -81,8 +87,25 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, mutex_lock(&dmcfreq->lock); =20 if (dmcfreq->regmap_pmu) { + unsigned int odt_pd_arg0 =3D dmcfreq->odt_pd_arg0; + unsigned int odt_pd_arg1 =3D dmcfreq->odt_pd_arg1; unsigned int odt_pd_arg2 =3D 0; =20 + if (target_rate >=3D dmcfreq->sr_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_IDLE; + + if (target_rate >=3D dmcfreq->sr_mc_gate_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE; + + if (target_rate >=3D dmcfreq->standby_idle_dis_freq) + odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_STANDBY_IDLE; + + if (target_rate >=3D dmcfreq->pd_idle_dis_freq) + odt_pd_arg1 &=3D ~RK3399_SET_ODT_PD_1_PD_IDLE; + + if (target_rate >=3D dmcfreq->srpd_lite_idle_dis_freq) + odt_pd_arg1 &=3D ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE; + if (target_rate >=3D dmcfreq->odt_dis_freq) odt_pd_arg2 |=3D RK3399_SET_ODT_PD_2_ODT_ENABLE; =20 @@ -91,10 +114,9 @@ static int rk3399_dmcfreq_target(struct device *dev, un= signed long *freq, * (power-down) timings and to enable or disable the * ODT (on-die termination) resistors. */ - arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, - dmcfreq->odt_pd_arg1, - ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, - odt_pd_arg2, 0, 0, 0, &res); + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1, + ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2, + 0, 0, 0, &res); } =20 /* @@ -230,6 +252,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfr= eq *data, { int ret =3D 0; =20 + /* + * These are all optional, and serve as minimum bounds. Give them large + * (i.e., never "disabled") values if the DT doesn't specify one. + */ + data->pd_idle_dis_freq =3D + data->sr_idle_dis_freq =3D + data->sr_mc_gate_idle_dis_freq =3D + data->srpd_lite_idle_dis_freq =3D + data->standby_idle_dis_freq =3D UINT_MAX; + ret |=3D of_property_read_u32(np, "rockchip,pd_idle", &data->pd_idle); ret |=3D of_property_read_u32(np, "rockchip,sr_idle", @@ -247,6 +279,17 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfr= eq *data, ret |=3D of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", &data->lpddr4_odt_dis_freq); =20 + ret |=3D of_property_read_u32(np, "rockchip,pd-idle-dis-freq-hz", + &data->pd_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,sr-idle-dis-freq-hz", + &data->sr_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,sr-mc-gate-idle-dis-freq-hz", + &data->sr_mc_gate_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,srpd-lite-idle-dis-freq-hz", + &data->srpd_lite_idle_dis_freq); + ret |=3D of_property_read_u32(np, "rockchip,standby-idle-dis-freq-hz", + &data->standby_idle_dis_freq); + return ret; } =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1098CC4332F for ; Tue, 8 Mar 2022 19:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350023AbiCHTLC (ORCPT ); Tue, 8 Mar 2022 14:11:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349965AbiCHTKp (ORCPT ); Tue, 8 Mar 2022 14:10:45 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BB794EA0E for ; Tue, 8 Mar 2022 11:09:34 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id q19so4662950pgm.6 for ; Tue, 08 Mar 2022 11:09:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XdkuXzvsU8Qmmgk1oFXQM7A/zqUKyIIaZpyPEVdNOeA=; b=JwRh6BtiqbuT4qCPUSLvGr9eHRAxIPrezqeJENfy+kjTR4kU0Rlm0pGwZFmWl/Uj9A uyaUeaO7hoZaj/lAbwawuRyCY0iYJyGPpRY2KeE+/OSfDXsAWuPf2OWVh9NxtRqdCzF2 rIdrqmDQqhqHwHcdn1cmAtDZb7SYig3gAhZJQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XdkuXzvsU8Qmmgk1oFXQM7A/zqUKyIIaZpyPEVdNOeA=; b=L4jWTOeu17hTAfotaYoeurDiaq30wpy8Lxpa+DvWIta9Ff3EosZLZX0bVwHZVEETLs 4PvT7BzXhdRWkIiaIebT41OYI3TtfkiFFLRXkeopXr7aUzr1lUEJp9v+0ScNUXJ5BHnZ vS3UY+YBxN/+lOPK2V3Rkkdu2D0En/SCPQjZg/TeBVYfmm09dt/x2tlC3QpCNi5+9B46 cdjNsuaTAx7qNON6eiXjo/HSDgseHi2ywCe18iqgC01YOqHv1cb5dlfhRFMwj66RZORf uFbitMoIEyTaV58lOrIk+xCeBD8mmcmNa4o/eZSDImRGcUr+0VT/35YE7Od13GhHtZQO zgkA== X-Gm-Message-State: AOAM530XR4IFOpYzTsEhdy2wQHMPH/ve496hsxUzGas1Wk22+V/cTz4h 3NyvBw5mGw4fUfRimNlJb690Tw== X-Google-Smtp-Source: ABdhPJxRtrM2/49Je72bpHM2q09u+9Kclg+1x8oKck8ftlFcUfomI5ADI2wTOiWXIUoJ/CAsnmmgsA== X-Received: by 2002:a63:7e43:0:b0:374:75ce:4d80 with SMTP id o3-20020a637e43000000b0037475ce4d80mr15356157pgn.589.1646766573686; Tue, 08 Mar 2022 11:09:33 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id q11-20020a63f94b000000b00373c5319642sm15865829pgk.93.2022.03.08.11.09.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:32 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 10/15] PM / devfreq: rk3399_dmc: Support new *-ns properties Date: Tue, 8 Mar 2022 11:08:56 -0800 Message-Id: <20220308110825.v4.10.I4e01e243ea11e9f95295b40b44a9eaa3a883a0dd@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We want to keep the idle time fixed, so compute based on the current DDR frequency. The old properties were deprecated and never used, so we can safely drop them from the driver. This is a rewritten version of work by Lin Huang . Signed-off-by: Brian Norris --- (no changes since v2) Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 85 +++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 35 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index fc740c1f6747..f778564cab49 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -24,6 +24,8 @@ #include #include =20 +#define NS_TO_CYCLE(NS, MHz) (((NS) * (MHz)) / NSEC_PER_USEC) + #define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) #define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) #define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) @@ -45,13 +47,12 @@ struct rk3399_dmcfreq { unsigned long rate, target_rate; unsigned long volt, target_volt; unsigned int odt_dis_freq; - int odt_pd_arg0, odt_pd_arg1; =20 - unsigned int pd_idle; - unsigned int sr_idle; - unsigned int sr_mc_gate_idle; - unsigned int srpd_lite_idle; - unsigned int standby_idle; + unsigned int pd_idle_ns; + unsigned int sr_idle_ns; + unsigned int sr_mc_gate_idle_ns; + unsigned int srpd_lite_idle_ns; + unsigned int standby_idle_ns; unsigned int ddr3_odt_dis_freq; unsigned int lpddr3_odt_dis_freq; unsigned int lpddr4_odt_dis_freq; @@ -70,9 +71,14 @@ static int rk3399_dmcfreq_target(struct device *dev, uns= igned long *freq, struct dev_pm_opp *opp; unsigned long old_clk_rate =3D dmcfreq->rate; unsigned long target_volt, target_rate; + unsigned int ddrcon_mhz; struct arm_smccc_res res; int err; =20 + u32 odt_pd_arg0 =3D 0; + u32 odt_pd_arg1 =3D 0; + u32 odt_pd_arg2 =3D 0; + opp =3D devfreq_recommended_opp(dev, freq, flags); if (IS_ERR(opp)) return PTR_ERR(opp); @@ -86,11 +92,35 @@ static int rk3399_dmcfreq_target(struct device *dev, un= signed long *freq, =20 mutex_lock(&dmcfreq->lock); =20 - if (dmcfreq->regmap_pmu) { - unsigned int odt_pd_arg0 =3D dmcfreq->odt_pd_arg0; - unsigned int odt_pd_arg1 =3D dmcfreq->odt_pd_arg1; - unsigned int odt_pd_arg2 =3D 0; + /* + * Some idle parameters may be based on the DDR controller clock, which + * is half of the DDR frequency. + * pd_idle and standby_idle are based on the controller clock cycle. + * sr_idle_cycle, sr_mc_gate_idle_cycle, and srpd_lite_idle_cycle + * are based on the 1024 controller clock cycle + */ + ddrcon_mhz =3D target_rate / USEC_PER_SEC / 2; + + u32p_replace_bits(&odt_pd_arg1, + NS_TO_CYCLE(dmcfreq->pd_idle_ns, ddrcon_mhz), + RK3399_SET_ODT_PD_1_PD_IDLE); + u32p_replace_bits(&odt_pd_arg0, + NS_TO_CYCLE(dmcfreq->standby_idle_ns, ddrcon_mhz), + RK3399_SET_ODT_PD_0_STANDBY_IDLE); + u32p_replace_bits(&odt_pd_arg0, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_0_SR_IDLE); + u32p_replace_bits(&odt_pd_arg0, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_mc_gate_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE); + u32p_replace_bits(&odt_pd_arg1, + DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->srpd_lite_idle_ns, + ddrcon_mhz), 1024), + RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE); =20 + if (dmcfreq->regmap_pmu) { if (target_rate >=3D dmcfreq->sr_idle_dis_freq) odt_pd_arg0 &=3D ~RK3399_SET_ODT_PD_0_SR_IDLE; =20 @@ -262,16 +292,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcf= req *data, data->srpd_lite_idle_dis_freq =3D data->standby_idle_dis_freq =3D UINT_MAX; =20 - ret |=3D of_property_read_u32(np, "rockchip,pd_idle", - &data->pd_idle); - ret |=3D of_property_read_u32(np, "rockchip,sr_idle", - &data->sr_idle); - ret |=3D of_property_read_u32(np, "rockchip,sr_mc_gate_idle", - &data->sr_mc_gate_idle); - ret |=3D of_property_read_u32(np, "rockchip,srpd_lite_idle", - &data->srpd_lite_idle); - ret |=3D of_property_read_u32(np, "rockchip,standby_idle", - &data->standby_idle); + ret |=3D of_property_read_u32(np, "rockchip,pd-idle-ns", + &data->pd_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,sr-idle-ns", + &data->sr_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,sr-mc-gate-idle-ns", + &data->sr_mc_gate_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,srpd-lite-idle-ns", + &data->srpd_lite_idle_ns); + ret |=3D of_property_read_u32(np, "rockchip,standby-idle-ns", + &data->standby_idle_ns); ret |=3D of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", &data->ddr3_odt_dis_freq); ret |=3D of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", @@ -367,21 +397,6 @@ static int rk3399_dmcfreq_probe(struct platform_device= *pdev) ROCKCHIP_SIP_CONFIG_DRAM_INIT, 0, 0, 0, 0, &res); =20 - /* - * In TF-A there is a platform SIP call to set the PD (power-down) - * timings and to enable or disable the ODT (on-die termination). - */ - data->odt_pd_arg0 =3D - FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE, - data->sr_mc_gate_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE, - data->standby_idle); - data->odt_pd_arg1 =3D - FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) | - FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE, - data->srpd_lite_idle); - /* * We add a devfreq driver to our parent since it has a device tree node * with operating points. --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B86A5C433F5 for ; Tue, 8 Mar 2022 19:10:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349991AbiCHTLH (ORCPT ); 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Tue, 08 Mar 2022 11:09:35 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Enric Balletbo i Serra , =?UTF-8?q?Ga=C3=ABl=20PORTAY?= , Daniel Lezcano , Brian Norris Subject: [PATCH v4 11/15] arm64: dts: rk3399: Add dfi and dmc nodes Date: Tue, 8 Mar 2022 11:08:57 -0800 Message-Id: <20220308110825.v4.11.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lin Huang These are required to support DDR DVFS on RK3399 platforms. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Ga=C3=ABl PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Change since Daniel's posting: reordered by unit address, per existing style --- (no changes since v2) Changes in v2: - rename dmc to memory-controller Changes in v1: This is based on a v5 posting from various authors: https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.o= rg/ Much of that series was already merged, so I start over with the numbering. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts= /rockchip/rk3399.dtsi index 080457a68e3c..9065bb55ee7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1295,6 +1295,25 @@ pwm3: pwm@ff420030 { status =3D "disabled"; }; =20 + dfi: dfi@ff630000 { + reg =3D <0x00 0xff630000 0x00 0x4000>; + compatible =3D "rockchip,rk3399-dfi"; + rockchip,pmu =3D <&pmugrf>; + interrupts =3D ; + clocks =3D <&cru PCLK_DDR_MON>; + clock-names =3D "pclk_ddr_mon"; + status =3D "disabled"; + }; + + dmc: memory-controller { + compatible =3D "rockchip,rk3399-dmc"; + rockchip,pmu =3D <&pmugrf>; + devfreq-events =3D <&dfi>; + clocks =3D <&cru SCLK_DDRC>; + clock-names =3D "dmc_clk"; + status =3D "disabled"; + }; + vpu: video-codec@ff650000 { compatible =3D "rockchip,rk3399-vpu"; reg =3D <0x0 0xff650000 0x0 0x800>; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BBDDC433EF for ; Tue, 8 Mar 2022 19:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350001AbiCHTLL (ORCPT ); Tue, 8 Mar 2022 14:11:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350008AbiCHTLB (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lin Huang Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Ga=C3=ABl PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris --- (no changes since v2) Changes in v2: - Adapt to new properties Changes in v1: This was part of a previous series, at: https://lore.kernel.org/r/20210308233858.24741-3-daniel.lezcano@linaro.org I've picked up a bunch of changes and fixes, so I've restarted the patch series numbering. Updates since the old series: - reordered alphabetically by phandle name, per style - drop a ton of deprecated/unused properties - add required center-supply for scarlet - add new *_idle_dis_freq properties - drop the lowest (200 MHz) OPP; this was never stabilized for production - bump the voltage (0.9V -> 0.925V) for the highest OPP on Chromebook models; later (tablet) models were more stable, with a fixed DDR regulator - bump odt_dis_freq to 666 MHz; early versions used 333 MHz, but stabilization efforts landed on 666 MHz for production .../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch= /arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..50d459ee4831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -234,6 +234,13 @@ &cdn_dp { extcon =3D <&usbc_extcon0>, <&usbc_extcon1>; }; =20 +&dmc { + center-supply =3D <&ppvar_centerlogic>; + rockchip,pd-idle-dis-freq-hz =3D <800000000>; + rockchip,sr-idle-dis-freq-hz =3D <800000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <800000000>; +}; + &edp { status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/ar= m64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index a9817b3d7edc..913d845eb51a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -391,6 +391,18 @@ &cru { <400000000>; }; =20 +/* The center supply is fixed to .9V on scarlet */ +&dmc { + center-supply =3D <&pp900_s0>; +}; + +/* We don't need .925 V for 928 MHz on scarlet */ +&dmc_opp_table { + opp03 { + opp-microvolt =3D <900000>; + }; +}; + &gpio0 { gpio-line-names =3D /* GPIO0 A 0-7 */ "CLK_32K_AP", diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..23bfba86daab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -373,6 +373,34 @@ &cru { <200000000>; }; =20 +&dfi { + status =3D "okay"; +}; + +&dmc { + status =3D "okay"; + + rockchip,pd-idle-ns =3D <160>; + rockchip,sr-idle-ns =3D <10240>; + rockchip,sr-mc-gate-idle-ns =3D <40960>; + rockchip,srpd-lite-idle-ns =3D <61440>; + rockchip,standby-idle-ns =3D <81920>; + + rockchip,ddr3_odt_dis_freq =3D <666000000>; + rockchip,lpddr3_odt_dis_freq =3D <666000000>; + rockchip,lpddr4_odt_dis_freq =3D <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz =3D <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz =3D <0>; + rockchip,standby-idle-dis-freq-hz =3D <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/= boot/dts/rockchip/rk3399-op1-opp.dtsi index 2180e0f75003..6e29e74f6fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,27 @@ opp05 { opp-microvolt =3D <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible =3D "operating-points-v2"; + + opp00 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <900000>; + }; + opp01 { + opp-hz =3D /bits/ 64 <666000000>; + opp-microvolt =3D <900000>; + }; + opp02 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <900000>; + }; + opp03 { + opp-hz =3D /bits/ 64 <928000000>; + opp-microvolt =3D <925000>; + }; + }; }; =20 &cpu_l0 { @@ -136,6 +157,10 @@ &cpu_b1 { operating-points-v2 =3D <&cluster1_opp>; }; =20 +&dmc { + operating-points-v2 =3D <&dmc_opp_table>; +}; + &gpu { operating-points-v2 =3D <&gpu_opp_table>; }; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EFD2C433FE for ; Tue, 8 Mar 2022 19:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241931AbiCHTL1 (ORCPT ); Tue, 8 Mar 2022 14:11:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350027AbiCHTLC (ORCPT ); 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charset="utf-8" Otherwise we hit an unablanced enable-count when unbinding the DFI device: [ 1279.659119] ------------[ cut here ]------------ [ 1279.659179] WARNING: CPU: 2 PID: 5638 at drivers/devfreq/devfreq-event.c= :360 devfreq_event_remove_edev+0x84/0x8c ... [ 1279.659352] Hardware name: Google Kevin (DT) [ 1279.659363] pstate: 80400005 (Nzcv daif +PAN -UAO -TCO BTYPE=3D--) [ 1279.659371] pc : devfreq_event_remove_edev+0x84/0x8c [ 1279.659380] lr : devm_devfreq_event_release+0x1c/0x28 ... [ 1279.659571] Call trace: [ 1279.659582] devfreq_event_remove_edev+0x84/0x8c [ 1279.659590] devm_devfreq_event_release+0x1c/0x28 [ 1279.659602] release_nodes+0x1cc/0x244 [ 1279.659611] devres_release_all+0x44/0x60 [ 1279.659621] device_release_driver_internal+0x11c/0x1ac [ 1279.659629] device_driver_detach+0x20/0x2c [ 1279.659641] unbind_store+0x7c/0xb0 [ 1279.659650] drv_attr_store+0x2c/0x40 [ 1279.659663] sysfs_kf_write+0x44/0x58 [ 1279.659672] kernfs_fop_write_iter+0xf4/0x190 [ 1279.659684] vfs_write+0x2b0/0x2e4 [ 1279.659693] ksys_write+0x80/0xec [ 1279.659701] __arm64_sys_write+0x24/0x30 [ 1279.659714] el0_svc_common+0xf0/0x1d8 [ 1279.659724] do_el0_svc_compat+0x28/0x3c [ 1279.659738] el0_svc_compat+0x10/0x1c [ 1279.659746] el0_sync_compat_handler+0xa8/0xcc [ 1279.659758] el0_sync_compat+0x188/0x1c0 [ 1279.659768] ---[ end trace cec200e5094155b4 ]--- Signed-off-by: Brian Norris --- (no changes since v2) Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index f778564cab49..fca9fcbd4249 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -452,6 +452,8 @@ static int rk3399_dmcfreq_remove(struct platform_device= *pdev) { struct rk3399_dmcfreq *dmcfreq =3D dev_get_drvdata(&pdev->dev); =20 + devfreq_event_disable_edev(dmcfreq->edev); + /* * Before remove the opp table we need to unregister the opp notifier. */ --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA919C433F5 for ; Tue, 8 Mar 2022 19:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348174AbiCHTLk (ORCPT ); Tue, 8 Mar 2022 14:11:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350036AbiCHTLG (ORCPT ); Tue, 8 Mar 2022 14:11:06 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F4F34B409 for ; Tue, 8 Mar 2022 11:09:49 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id b8so199169pjb.4 for ; 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Tue, 08 Mar 2022 11:09:48 -0800 (PST) Received: from localhost ([2620:15c:202:201:b3e3:a188:cbfc:3a0e]) by smtp.gmail.com with UTF8SMTPSA id f18-20020a056a001ad200b004bf321765dfsm21125042pfv.95.2022.03.08.11.09.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Mar 2022 11:09:48 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 14/15] PM / devfreq: rk3399_dmc: Use devm_pm_opp_of_add_table() Date: Tue, 8 Mar 2022 11:09:00 -0800 Message-Id: <20220308110825.v4.14.I3df48ceacbf299549501a44433039d46e0a275ea@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This simplifies error-cleanup and remove(). Signed-off-by: Brian Norris --- (no changes since v2) Changes in v2: - New patch drivers/devfreq/rk3399_dmc.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index fca9fcbd4249..9615658d04ae 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -401,7 +401,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) * We add a devfreq driver to our parent since it has a device tree node * with operating points. */ - if (dev_pm_opp_of_add_table(dev)) { + if (devm_pm_opp_of_add_table(dev)) { dev_err(dev, "Invalid operating-points in device tree.\n"); ret =3D -EINVAL; goto err_edev; @@ -415,7 +415,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) opp =3D devfreq_recommended_opp(dev, &data->rate, 0); if (IS_ERR(opp)) { ret =3D PTR_ERR(opp); - goto err_free_opp; + goto err_edev; } =20 data->rate =3D dev_pm_opp_get_freq(opp); @@ -430,7 +430,7 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) &data->ondemand_data); if (IS_ERR(data->devfreq)) { ret =3D PTR_ERR(data->devfreq); - goto err_free_opp; + goto err_edev; } =20 devm_devfreq_register_opp_notifier(dev, data->devfreq); @@ -440,8 +440,6 @@ static int rk3399_dmcfreq_probe(struct platform_device = *pdev) =20 return 0; =20 -err_free_opp: - dev_pm_opp_of_remove_table(&pdev->dev); err_edev: devfreq_event_disable_edev(data->edev); =20 @@ -454,12 +452,6 @@ static int rk3399_dmcfreq_remove(struct platform_devic= e *pdev) =20 devfreq_event_disable_edev(dmcfreq->edev); =20 - /* - * Before remove the opp table we need to unregister the opp notifier. - */ - devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); - dev_pm_opp_of_remove_table(dmcfreq->dev); - return 0; } =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Tue Jun 23 08:15:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D320AC433EF for ; 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Tue, 08 Mar 2022 11:09:50 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Heiko Stuebner Cc: Derek Basehore , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Lin Huang , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Brian Norris Subject: [PATCH v4 15/15] PM / devfreq: rk3399_dmc: Avoid static (reused) profile Date: Tue, 8 Mar 2022 11:09:01 -0800 Message-Id: <20220308110825.v4.15.I8d71e9555aca1fa7e532d22dd1ef27976f21799d@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308190901.3144566-1-briannorris@chromium.org> References: <20220308190901.3144566-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This static struct can get reused if the device gets removed/reprobed, and that causes use-after-free in its ->freq_table. Let's just move the struct to our dynamic allocation. Signed-off-by: Brian Norris --- (no changes since v2) Changes in v2: * New patch drivers/devfreq/rk3399_dmc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index 9615658d04ae..e494d1497d60 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -38,6 +38,7 @@ struct rk3399_dmcfreq { struct device *dev; struct devfreq *devfreq; + struct devfreq_dev_profile profile; struct devfreq_simple_ondemand_data ondemand_data; struct clk *dmc_clk; struct devfreq_event_dev *edev; @@ -228,13 +229,6 @@ static int rk3399_dmcfreq_get_cur_freq(struct device *= dev, unsigned long *freq) return 0; } =20 -static struct devfreq_dev_profile rk3399_devfreq_dmc_profile =3D { - .polling_ms =3D 200, - .target =3D rk3399_dmcfreq_target, - .get_dev_status =3D rk3399_dmcfreq_get_dev_status, - .get_cur_freq =3D rk3399_dmcfreq_get_cur_freq, -}; - static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) { struct rk3399_dmcfreq *dmcfreq =3D dev_get_drvdata(dev); @@ -422,10 +416,16 @@ static int rk3399_dmcfreq_probe(struct platform_devic= e *pdev) data->volt =3D dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); =20 - rk3399_devfreq_dmc_profile.initial_freq =3D data->rate; + data->profile =3D (struct devfreq_dev_profile) { + .polling_ms =3D 200, + .target =3D rk3399_dmcfreq_target, + .get_dev_status =3D rk3399_dmcfreq_get_dev_status, + .get_cur_freq =3D rk3399_dmcfreq_get_cur_freq, + .initial_freq =3D data->rate, + }; =20 data->devfreq =3D devm_devfreq_add_device(dev, - &rk3399_devfreq_dmc_profile, + &data->profile, DEVFREQ_GOV_SIMPLE_ONDEMAND, &data->ondemand_data); if (IS_ERR(data->devfreq)) { --=20 2.35.1.616.g0bdcbb4464-goog