From nobody Tue Jun 23 08:13:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 896E0C4332F for ; Tue, 8 Mar 2022 16:38:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348402AbiCHQjK (ORCPT ); Tue, 8 Mar 2022 11:39:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235873AbiCHQjJ (ORCPT ); Tue, 8 Mar 2022 11:39:09 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AFB64B1ED for ; Tue, 8 Mar 2022 08:38:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646757491; x=1678293491; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qkoBji/qAVM+5IAIHA2GJqgBvfHl7DZb/CK2G9qovLI=; b=k4wuM1/cN1jWvR7WJrh4Z+KLJYbdw78kj5Dlisbi1xhJ7lTXvVrhnd1w thDuBt82nSZXeyWuqBhMD1Jer/eK3ZihTPm/HCb8vJFyV5QTxkpQ3t02W KhwSlJQkwXMqsnvcPKEi47w/wDNYmB+YTWsf4O53WDgTxOJd7RJQMzj3T Ecaqf4XsZq+sZNS5XqsGmUP60vP8ph5cbrqqDif/tu6ryGPDJbXY3N1u/ abkPrKYkNfu7/3a2b0mPOS6uSWrmuD8/YHRQgmZ+1eRUa+lre7sO/lzqZ d4m1u6Agmb86/nNTeSVAmOFct7zOpIU2W849v0CiVLbW/qL2seqCS3boJ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10280"; a="253564380" X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="253564380" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:11 -0800 X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="537630774" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:07 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tvrtko Ursulin Subject: [PATCH v10 1/5] drm/i915/gsc: add gsc as a mei auxiliary device Date: Tue, 8 Mar 2022 18:36:50 +0200 Message-Id: <20220308163654.942820-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220308163654.942820-1-alexander.usyskin@intel.com> References: <20220308163654.942820-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Acked-by: Tvrtko Ursulin --- MAINTAINERS | 1 + drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/gt/intel_gsc.c | 204 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++ drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_device_info.h | 2 + include/linux/mei_aux.h | 19 +++ 15 files changed, 303 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h create mode 100644 include/linux/mei_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index 2b1d296f92e9..d322e630d1d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9822,6 +9822,7 @@ S: Supported F: Documentation/driver-api/mei/* F: drivers/misc/mei/ F: drivers/watchdog/mei_wdt.c +F: include/linux/mei_aux.h F: include/linux/mei_cl_bus.h F: include/uapi/linux/mei.h F: samples/mei/* diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 98c5450b8eac..2660a85175d9 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -30,6 +30,7 @@ config DRM_I915 select VMAP_PFN select DRM_TTM select DRM_BUDDY + select AUXILIARY_BUS help Choose this option if you have a system that has "Intel Graphics Media Accelerator" or "HD Graphics" integrated graphics, diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 1a771ee5b1d0..9be7b13d8822 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -196,6 +196,9 @@ i915-y +=3D gt/uc/intel_uc.o \ gt/uc/intel_huc_debugfs.o \ gt/uc/intel_huc_fw.o =20 +# graphics system controller (GSC) support +i915-y +=3D gt/intel_gsc.o + # modesetting core code i915-y +=3D \ display/hsw_ips.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c new file mode 100644 index 000000000000..152804e7c41a --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "i915_reg.h" +#include "i915_drv.h" +#include "gt/intel_gt.h" +#include "intel_gsc.h" + +#define GSC_BAR_LENGTH 0x00000FFC + +static void gsc_irq_mask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static void gsc_irq_unmask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static struct irq_chip gsc_irq_chip =3D { + .name =3D "gsc_irq_chip", + .irq_mask =3D gsc_irq_mask, + .irq_unmask =3D gsc_irq_unmask, +}; + +static int gsc_irq_init(int irq) +{ + irq_set_chip_and_handler_name(irq, &gsc_irq_chip, + handle_simple_irq, "gsc_irq_handler"); + + return irq_set_chip_data(irq, NULL); +} + +struct intel_gsc_def { + const char *name; + unsigned long bar; + size_t bar_size; +}; + +/* gscfi (graphics system controller firmware interface) resources */ +static const struct intel_gsc_def intel_gsc_def_dg1[] =3D { + { + /* HECI1 not yet implemented. */ + }, + { + .name =3D "mei-gscfi", + .bar =3D GSC_DG1_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + } +}; + +static void intel_gsc_release_dev(struct device *dev) +{ + struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + + kfree(adev); +} + +static void intel_gsc_destroy_one(struct intel_gsc_intf *intf) +{ + if (intf->adev) { + auxiliary_device_delete(&intf->adev->aux_dev); + auxiliary_device_uninit(&intf->adev->aux_dev); + intf->adev =3D NULL; + } + if (intf->irq >=3D 0) + irq_free_desc(intf->irq); + intf->irq =3D -1; +} + +static void intel_gsc_init_one(struct drm_i915_private *i915, + struct intel_gsc_intf *intf, + unsigned int intf_id) +{ + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); + struct mei_aux_device *adev; + struct auxiliary_device *aux_dev; + const struct intel_gsc_def *def; + int ret; + + intf->irq =3D -1; + intf->id =3D intf_id; + + if (intf_id =3D=3D 0 && !HAS_HECI_PXP(i915)) + return; + + def =3D &intel_gsc_def_dg1[intf_id]; + + if (!def->name) { + drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1); + return; + } + + intf->irq =3D irq_alloc_desc(0); + if (intf->irq < 0) { + drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); + return; + } + + ret =3D gsc_irq_init(intf->irq); + if (ret < 0) { + drm_err(&i915->drm, "gsc irq init failed %d\n", ret); + goto fail; + } + + adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + goto fail; + + adev->irq =3D intf->irq; + adev->bar.parent =3D &pdev->resource[0]; + adev->bar.start =3D def->bar + pdev->resource[0].start; + adev->bar.end =3D adev->bar.start + def->bar_size - 1; + adev->bar.flags =3D IORESOURCE_MEM; + adev->bar.desc =3D IORES_DESC_NONE; + + aux_dev =3D &adev->aux_dev; + aux_dev->name =3D def->name; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D intel_gsc_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret < 0) { + drm_err(&i915->drm, "gsc aux init failed %d\n", ret); + kfree(adev); + goto fail; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret < 0) { + drm_err(&i915->drm, "gsc aux add failed %d\n", ret); + /* adev will be freed with the put_device() and .release sequence */ + auxiliary_device_uninit(aux_dev); + goto fail; + } + intf->adev =3D adev; + + return; +fail: + intel_gsc_destroy_one(intf); +} + +static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id) +{ + int ret; + + if (intf_id >=3D INTEL_GSC_NUM_INTERFACES) { + drm_warn_once(>->i915->drm, "GSC irq: intf_id %d is out of range", int= f_id); + return; + } + + if (!HAS_HECI_GSC(gt->i915)) { + drm_warn_once(>->i915->drm, "GSC irq: not supported"); + return; + } + + if (gt->gsc.intf[intf_id].irq < 0) { + drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set"); + return; + } + + ret =3D generic_handle_irq(gt->gsc.intf[intf_id].irq); + if (ret) + drm_err_ratelimited(>->i915->drm, "error handling GSC irq: %d\n", ret); +} + +void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir) +{ + if (iir & GSC_IRQ_INTF(0)) + gsc_irq_handler(gt, 0); + if (iir & GSC_IRQ_INTF(1)) + gsc_irq_handler(gt, 1); +} + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915) +{ + unsigned int i; + + if (!HAS_HECI_GSC(i915)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + intel_gsc_init_one(i915, &gsc->intf[i], i); +} + +void intel_gsc_fini(struct intel_gsc *gsc) +{ + struct intel_gt *gt =3D gsc_to_gt(gsc); + unsigned int i; + + if (!HAS_HECI_GSC(gt->i915)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + intel_gsc_destroy_one(&gsc->intf[i]); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/= intel_gsc.h new file mode 100644 index 000000000000..68582f912b21 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ +#ifndef __INTEL_GSC_DEV_H__ +#define __INTEL_GSC_DEV_H__ + +#include + +struct drm_i915_private; +struct intel_gt; +struct mei_aux_device; + +#define INTEL_GSC_NUM_INTERFACES 2 +/* + * The HECI1 bit corresponds to bit15 and HECI2 to bit14. + * The reason for this is to allow growth for more interfaces in the futur= e. + */ +#define GSC_IRQ_INTF(_x) BIT(15 - (_x)) + +/** + * struct intel_gsc - graphics security controller + * @intf : gsc interface + */ +struct intel_gsc { + struct intel_gsc_intf { + struct mei_aux_device *adev; + int irq; + unsigned int id; + } intf[INTEL_GSC_NUM_INTERFACES]; +}; + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_pr= iv); +void intel_gsc_fini(struct intel_gsc *gsc); +void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir); + +#endif /* __INTEL_GSC_DEV_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/i= ntel_gt.c index 8a2483ccbfb9..fd83ab4b8849 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -444,6 +444,8 @@ void intel_gt_chipset_flush(struct intel_gt *gt) =20 void intel_gt_driver_register(struct intel_gt *gt) { + intel_gsc_init(>->gsc, gt->i915); + intel_rps_driver_register(>->rps); =20 intel_gt_debugfs_register(gt); @@ -766,6 +768,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt) intel_wakeref_t wakeref; =20 intel_rps_driver_unregister(>->rps); + intel_gsc_fini(>->gsc); =20 intel_pxp_fini(>->pxp); =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/i= ntel_gt.h index 0f571c8ee22b..de779a505c21 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -34,6 +34,11 @@ static inline struct intel_gt *huc_to_gt(struct intel_hu= c *huc) return container_of(huc, struct intel_gt, uc.huc); } =20 +static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) +{ + return container_of(gsc, struct intel_gt, gsc); +} + void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i91= 5); void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i= 915); int intel_gt_assign_ggtt(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/= gt/intel_gt_irq.c index e443ac4c8059..917b85d0c189 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -68,6 +68,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 ins= tance, if (instance =3D=3D OTHER_KCR_INSTANCE) return intel_pxp_irq_handler(>->pxp, iir); =20 + if (instance =3D=3D OTHER_GSC_INSTANCE) + return intel_gsc_irq_handler(gt, iir); + WARN_ONCE(1, "unhandled other interrupt instance=3D0x%x, iir=3D0x%x\n", instance, iir); } @@ -184,6 +187,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); if (CCS_MASK(gt)) intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); =20 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); @@ -201,6 +206,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); =20 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); @@ -215,6 +222,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) { struct intel_uncore *uncore =3D gt->uncore; u32 irqs =3D GT_RENDER_USER_INTERRUPT; + const u32 gsc_mask =3D GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); u32 dmask; u32 smask; =20 @@ -233,6 +241,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); if (CCS_MASK(gt)) intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, + gsc_mask); =20 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); @@ -250,6 +261,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, 0); =20 /* * RPS interrupts will get enabled/disabled on demand when RPS itself diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915= /gt/intel_gt_regs.h index 19cd34f24263..a277fb480cc8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1483,6 +1483,7 @@ #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 #define OTHER_KCR_INSTANCE 4 +#define OTHER_GSC_INSTANCE 6 =20 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i91= 5/gt/intel_gt_types.h index f20687796490..5556d55f76ea 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -16,6 +16,7 @@ #include =20 #include "uc/intel_uc.h" +#include "intel_gsc.h" =20 #include "i915_vma.h" #include "intel_engine_types.h" @@ -72,6 +73,7 @@ struct intel_gt { struct i915_ggtt *ggtt; =20 struct intel_uc uc; + struct intel_gsc gsc; =20 struct mutex tlb_invalidate_lock; =20 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 943267393ecb..1c000c15493d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1327,6 +1327,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, =20 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) =20 +#define HAS_HECI_PXP(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_pxp) + +#define HAS_HECI_GSCFI(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_gscfi) + +#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(d= ev_priv)) + #define HAS_MSO(i915) (DISPLAY_VER(i915) >=3D 12) =20 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pc= i.c index 67b89769f577..a948f566bd3d 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -901,7 +901,8 @@ static const struct intel_device_info rkl_info =3D { .has_llc =3D 0, \ .has_pxp =3D 0, \ .has_snoop =3D 1, \ - .is_dgfx =3D 1 + .is_dgfx =3D 1, \ + .has_heci_gscfi =3D 1 =20 static const struct intel_device_info dg1_info =3D { GEN12_FEATURES, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index 70484f6f2b8b..0ed305ff07a9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -975,6 +975,8 @@ #define GEN12_COMPUTE1_RING_BASE 0x1c000 #define GEN12_COMPUTE2_RING_BASE 0x1e000 #define GEN12_COMPUTE3_RING_BASE 0x26000 +#define GSC_DG1_HECI1_BASE 0x00258000 +#define GSC_DG1_HECI2_BASE 0x00259000 #define BLT_RING_BASE 0x22000 =20 =20 diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i91= 5/intel_device_info.h index f9b955810593..576d15a04c9e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -141,6 +141,8 @@ enum intel_ppgtt_type { func(has_flat_ccs); \ func(has_global_mocs); \ func(has_gt_uc); \ + func(has_heci_pxp); \ + func(has_heci_gscfi); \ func(has_guc_deprivilege); \ func(has_l3_dpf); \ func(has_llc); \ diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h new file mode 100644 index 000000000000..587f25128848 --- /dev/null +++ b/include/linux/mei_aux.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Intel Corporation. All rights reserved. + */ +#ifndef _LINUX_MEI_AUX_H +#define _LINUX_MEI_AUX_H + +#include + +struct mei_aux_device { + struct auxiliary_device aux_dev; + int irq; + struct resource bar; +}; + +#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct mei_aux_device, aux_dev) + +#endif /* _LINUX_MEI_AUX_H */ --=20 2.32.0 From nobody Tue Jun 23 08:13:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E439BC433F5 for ; Tue, 8 Mar 2022 16:38:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348409AbiCHQjU (ORCPT ); Tue, 8 Mar 2022 11:39:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348400AbiCHQjN (ORCPT ); Tue, 8 Mar 2022 11:39:13 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B86314B1ED for ; Tue, 8 Mar 2022 08:38:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646757495; x=1678293495; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ABujj9gZX+5IQrBugoEyUmFa3b6p06JvUoxg+hEitHU=; b=h+Bdew7URWX+JaxkCHB5y2GvuwRRAT9NF/rxJpmQQuM50VShijDn8wCr IZaVSfxVOXvJpi6QMga0vaH9KK5MRNyFL3wn0NDA+ZlLma55W8VDGOpzv mfm3ijv6/cGG4AUgIu+FJxEcg2/4HmT6tMRODgI4efIAQNeXhuTJNuowU dbxzYseu0/d4769bdJg3g1zMDxDSu1nu/efU41jfoHP09+ARryQlSQUMv O02mc5l2v9zMgmkk4hOno9fRPYOHQiUGNA61SBvy3vB7WEgvzAxacErBe 160j2Zi/iAooGu6Sp31uoBr8qub4zb2RTyveLM46g5Gcf6g+wbY06ZNEB w==; X-IronPort-AV: E=McAfee;i="6200,9189,10280"; a="253564392" X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="253564392" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:15 -0800 X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="537630824" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:12 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 2/5] mei: add support for graphics system controller (gsc) devices Date: Tue, 8 Mar 2022 18:36:51 +0200 Message-Id: <20220308163654.942820-3-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220308163654.942820-1-alexander.usyskin@intel.com> References: <20220308163654.942820-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, based on CSE, it provides a chassis controller for graphics discrete cards, as well as it supports media protection on selected devices. mei_gsc binds to a auxiliary devices exposed by Intel discrete driver i915. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler --- drivers/misc/mei/Kconfig | 14 +++ drivers/misc/mei/Makefile | 3 + drivers/misc/mei/gsc-me.c | 186 ++++++++++++++++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 27 +++++- drivers/misc/mei/hw-me.h | 2 + 5 files changed, 230 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/mei/gsc-me.c diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 0e0bcd0da852..d21486d69df2 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -46,6 +46,20 @@ config INTEL_MEI_TXE Supported SoCs: Intel Bay Trail =20 +config INTEL_MEI_GSC + tristate "Intel MEI GSC embedded device" + depends on INTEL_MEI + depends on INTEL_MEI_ME + depends on X86 && PCI + depends on DRM_I915 + help + Intel auxiliary driver for GSC devices embedded in Intel graphics devic= es. + + An MEI device here called GSC can be embedded in an + Intel graphics devices, to support a range of chassis + tasks such as graphics card firmware update and security + tasks. + source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" =20 diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index d8e5165917f2..fb740d754900 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) +=3D mei-me.o mei-me-objs :=3D pci-me.o mei-me-objs +=3D hw-me.o =20 +obj-$(CONFIG_INTEL_MEI_GSC) +=3D mei-gsc.o +mei-gsc-objs :=3D gsc-me.o + obj-$(CONFIG_INTEL_MEI_TXE) +=3D mei-txe.o mei-txe-objs :=3D pci-txe.o mei-txe-objs +=3D hw-txe.o diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c new file mode 100644 index 000000000000..0afae70e0609 --- /dev/null +++ b/drivers/misc/mei/gsc-me.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + * + * Intel Management Engine Interface (Intel MEI) Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_dev.h" +#include "hw-me.h" +#include "hw-me-regs.h" + +#include "mei-trace.h" + +#define MEI_GSC_RPM_TIMEOUT 500 + +static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *= val) +{ + struct mei_me_hw *hw =3D to_me_hw(dev); + + *val =3D ioread32(hw->mem_addr + where + 0xC00); + + return 0; +} + +static int mei_gsc_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *aux_dev_id) +{ + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + struct mei_device *dev; + struct mei_me_hw *hw; + struct device *device; + const struct mei_cfg *cfg; + int ret; + + cfg =3D mei_me_get_cfg(aux_dev_id->driver_data); + if (!cfg) + return -ENODEV; + + device =3D &aux_dev->dev; + + dev =3D mei_me_dev_init(device, cfg); + if (IS_ERR(dev)) { + ret =3D PTR_ERR(dev); + goto err; + } + + hw =3D to_me_hw(dev); + hw->mem_addr =3D devm_ioremap_resource(device, &adev->bar); + if (IS_ERR(hw->mem_addr)) { + dev_err(device, "mmio not mapped\n"); + ret =3D PTR_ERR(hw->mem_addr); + goto err; + } + + hw->irq =3D adev->irq; + hw->read_fws =3D mei_gsc_read_hfs; + + dev_set_drvdata(&aux_dev->dev, dev); + + ret =3D devm_request_threaded_irq(device, hw->irq, + mei_me_irq_quick_handler, + mei_me_irq_thread_handler, + IRQF_ONESHOT, KBUILD_MODNAME, dev); + if (ret) { + dev_err(device, "irq register failed %d\n", ret); + goto err; + } + + pm_runtime_get_noresume(device); + pm_runtime_set_active(device); + pm_runtime_enable(device); + + if (mei_start(dev)) { + dev_err(device, "init hw failure.\n"); + ret =3D -ENODEV; + goto err; + } + + pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); + pm_runtime_use_autosuspend(device); + + ret =3D mei_register(dev, device); + if (ret) + goto register_err; + + pm_runtime_put_noidle(device); + return 0; + +register_err: + mei_stop(dev); + +err: + dev_err(device, "probe failed: %d\n", ret); + dev_set_drvdata(&aux_dev->dev, NULL); + return ret; +} + +static void mei_gsc_remove(struct auxiliary_device *aux_dev) +{ + struct mei_device *dev; + + dev =3D dev_get_drvdata(&aux_dev->dev); + if (!dev) + return; + + mei_stop(dev); + + mei_deregister(dev); + + pm_runtime_disable(&aux_dev->dev); +} + +static int __maybe_unused mei_gsc_pm_suspend(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + + mei_stop(dev); + + mei_disable_interrupts(dev); + + return 0; +} + +static int __maybe_unused mei_gsc_pm_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + int err; + + if (!dev) + return -ENODEV; + + err =3D mei_restart(dev); + if (err) + return err; + + /* Start timer if stopped in suspend */ + schedule_delayed_work(&dev->timer_work, HZ); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); + +static const struct auxiliary_device_id mei_gsc_id_table[] =3D { + { + .name =3D "i915.mei-gsc", + .driver_data =3D MEI_ME_GSC_CFG, + + }, + { + .name =3D "i915.mei-gscfi", + .driver_data =3D MEI_ME_GSCFI_CFG, + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table); + +static struct auxiliary_driver mei_gsc_driver =3D { + .probe =3D mei_gsc_probe, + .remove =3D mei_gsc_remove, + .driver =3D { + /* auxiliary_driver_register() sets .name to be the modname */ + .pm =3D &mei_gsc_pm_ops, + }, + .id_table =3D mei_gsc_id_table +}; +module_auxiliary_driver(mei_gsc_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_ALIAS("auxiliary:i915.mei-gsc"); +MODULE_ALIAS("auxiliary:i915.mei-gscfi"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index d3a6c0728645..9748d14849a1 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *d= ev_id) me_intr_disable(dev, hcsr); return IRQ_WAKE_THREAD; } +EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler); =20 /** * mei_me_irq_thread_handler - function called after ISR to handle the int= errupt @@ -1320,6 +1321,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *= dev_id) mutex_unlock(&dev->device_lock); return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); =20 static const struct mei_hw_ops mei_me_hw_ops =3D { =20 @@ -1433,6 +1435,12 @@ static bool mei_me_fw_type_sps(const struct pci_dev = *pdev) #define MEI_CFG_KIND_ITOUCH \ .kind =3D "itouch" =20 +#define MEI_CFG_TYPE_GSC \ + .kind =3D "gsc" + +#define MEI_CFG_TYPE_GSCFI \ + .kind =3D "gscfi" + #define MEI_CFG_FW_SPS \ .quirk_probe =3D mei_me_fw_type_sps =20 @@ -1565,6 +1573,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg =3D= { MEI_CFG_FW_SPS, }; =20 +/* Graphics System Controller */ +static const struct mei_cfg mei_me_gsc_cfg =3D { + MEI_CFG_TYPE_GSC, + MEI_CFG_PCH8_HFS, +}; + +/* Graphics System Controller Firmware Interface */ +static const struct mei_cfg mei_me_gscfi_cfg =3D { + MEI_CFG_TYPE_GSCFI, + MEI_CFG_PCH8_HFS, +}; + /* * mei_cfg_list - A list of platform platform specific configurations. * Note: has to be synchronized with enum mei_cfg_idx. @@ -1585,6 +1605,8 @@ static const struct mei_cfg *const mei_cfg_list[] =3D= { [MEI_ME_PCH12_SPS_ITOUCH_CFG] =3D &mei_me_pch12_itouch_sps_cfg, [MEI_ME_PCH15_CFG] =3D &mei_me_pch15_cfg, [MEI_ME_PCH15_SPS_CFG] =3D &mei_me_pch15_sps_cfg, + [MEI_ME_GSC_CFG] =3D &mei_me_gsc_cfg, + [MEI_ME_GSCFI_CFG] =3D &mei_me_gscfi_cfg, }; =20 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) @@ -1595,7 +1617,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t i= dx) return NULL; =20 return mei_cfg_list[idx]; -}; +} +EXPORT_SYMBOL_GPL(mei_me_get_cfg); =20 /** * mei_me_dev_init - allocates and initializes the mei device structure @@ -1630,4 +1653,4 @@ struct mei_device *mei_me_dev_init(struct device *par= ent, =20 return dev; } - +EXPORT_SYMBOL_GPL(mei_me_dev_init); diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index 00a7132ac7a2..a071c645e905 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -112,6 +112,8 @@ enum mei_cfg_idx { MEI_ME_PCH12_SPS_ITOUCH_CFG, MEI_ME_PCH15_CFG, MEI_ME_PCH15_SPS_CFG, + MEI_ME_GSC_CFG, + MEI_ME_GSCFI_CFG, MEI_ME_NUM_CFG, }; =20 --=20 2.32.0 From nobody Tue Jun 23 08:13:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68688C433EF for ; Tue, 8 Mar 2022 16:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229669AbiCHQj3 (ORCPT ); Tue, 8 Mar 2022 11:39:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348413AbiCHQj1 (ORCPT ); Tue, 8 Mar 2022 11:39:27 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8994BFDD for ; Tue, 8 Mar 2022 08:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646757510; x=1678293510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TLkqMr2jx01CyRrqkRPNdsu/Li2EYBHMmZncYyPe5+g=; b=UWWGa83AnyUInh/hkyUr7AKGymVa/IxLGNMr2vdBXAmzPtcIjqW6h0sn XYcLf/QNgT3rXGqM/LllO6ypxm0RsctaSTHcoTeEblQ2jaQPqlzm3ZsnR zUJDL0iRyFypDdV51+K7oNIF1kf1ns/PAeyjk0Ah8q+5cgCh6tc1VQlC/ 7hu0gr+0S0zLCQIvGDCRKVfpCad2eLqcGwc4DtLMsaAIDsRdJeAPE6nsT ud6cNW+dAdBTzzbSNfluZwIRD+2DYAYgMfjx610sMfK4VBiSjuomfogmd f1w0+rNB/YHJ2d5mK0u7ai/3JMNh7/ubIdrFnYPibnhYoT0BcAEE9e7pt g==; X-IronPort-AV: E=McAfee;i="6200,9189,10280"; a="315450338" X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="315450338" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:29 -0800 X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="537630938" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:16 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 3/5] mei: gsc: setup char driver alive in spite of firmware handshake failure Date: Tue, 8 Mar 2022 18:36:52 +0200 Message-Id: <20220308163654.942820-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220308163654.942820-1-alexander.usyskin@intel.com> References: <20220308163654.942820-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Setup char device in spite of firmware handshake failure. In order to provide host access to the firmware status registers and other information required for the manufacturing process. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/gsc-me.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 0afae70e0609..cf427f6fdec9 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -79,11 +79,12 @@ static int mei_gsc_probe(struct auxiliary_device *aux_d= ev, pm_runtime_set_active(device); pm_runtime_enable(device); =20 - if (mei_start(dev)) { - dev_err(device, "init hw failure.\n"); - ret =3D -ENODEV; - goto err; - } + /* Continue to char device setup in spite of firmware handshake failure. + * In order to provide access to the firmware status registers to the user + * space via sysfs. + */ + if (mei_start(dev)) + dev_warn(device, "init hw failure.\n"); =20 pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); pm_runtime_use_autosuspend(device); --=20 2.32.0 From nobody Tue Jun 23 08:13:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC9A4C433F5 for ; Tue, 8 Mar 2022 16:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348421AbiCHQjb (ORCPT ); Tue, 8 Mar 2022 11:39:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348400AbiCHQj2 (ORCPT ); Tue, 8 Mar 2022 11:39:28 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97E494F45C for ; Tue, 8 Mar 2022 08:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646757511; x=1678293511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jFUH4GegF6d5+JeCR9dkmblPZiL+BW4LtcHSJPjMPDI=; b=ab6VTw3S2MkuI4uSFKScfVkLBMhRbgv5EzwZp02SGghQ1SCnWQimoHYh XzwYCG5dRFuF2Z/TOFoSytR1F0W58dJob4rBpf5C5eqDvRJx9sh7LvlQc csYut/w1fbNHEUfUTq/wmKhoOMNWFgvPzaksFj6eWizn6UsDP34gozcpq 2CZDrHJiwTr9Ugnh1optWne5UBTS22aU9vmXPrH7xRUCBREsyO4Z0aj4Y ykmGX2MZJAWPkrJ/mkbXUfb1i2IupsmmA5vDHQlAtVldBPZRw0ekPMMEZ l7PZ9EIoUBAjXwhTOJH/7v/Ih5ChcNYuaeiyrrlOEehPQLVe9+GXRVJ6O A==; X-IronPort-AV: E=McAfee;i="6200,9189,10280"; a="315450345" X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="315450345" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:31 -0800 X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="537630941" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:20 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 4/5] mei: gsc: add runtime pm handlers Date: Tue, 8 Mar 2022 18:36:53 +0200 Message-Id: <20220308163654.942820-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220308163654.942820-1-alexander.usyskin@intel.com> References: <20220308163654.942820-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler Implement runtime handlers for mei-gsc, to track idle state of the device properly. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/misc/mei/gsc-me.c | 67 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index cf427f6fdec9..dac482ddab51 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -152,7 +152,72 @@ static int __maybe_unused mei_gsc_pm_resume(struct dev= ice *device) return 0; } =20 -static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); +static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + if (mei_write_is_idle(dev)) + pm_runtime_autosuspend(device); + + return -EBUSY; +} + +static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *devic= e) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + int ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + if (mei_write_is_idle(dev)) { + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_ON; + ret =3D 0; + } else { + ret =3D -EAGAIN; + } + + mutex_unlock(&dev->device_lock); + + return ret; +} + +static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + irqreturn_t irq_ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_OFF; + + mutex_unlock(&dev->device_lock); + + irq_ret =3D mei_me_irq_thread_handler(1, dev); + if (irq_ret !=3D IRQ_HANDLED) + dev_err(dev->dev, "thread handler fail %d\n", irq_ret); + + return 0; +} + +static const struct dev_pm_ops mei_gsc_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(mei_gsc_pm_suspend, + mei_gsc_pm_resume) + SET_RUNTIME_PM_OPS(mei_gsc_pm_runtime_suspend, + mei_gsc_pm_runtime_resume, + mei_gsc_pm_runtime_idle) +}; =20 static const struct auxiliary_device_id mei_gsc_id_table[] =3D { { --=20 2.32.0 From nobody Tue Jun 23 08:13:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF39C433F5 for ; Tue, 8 Mar 2022 16:38:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348433AbiCHQjd (ORCPT ); Tue, 8 Mar 2022 11:39:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242187AbiCHQj2 (ORCPT ); Tue, 8 Mar 2022 11:39:28 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8037C5132A for ; Tue, 8 Mar 2022 08:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646757512; x=1678293512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kZ/6QRCbXKz2uPbny7BLUdY7VrneEb9rP+jgHoalIWo=; b=VYwkVuUqRmdivm/R0mpCbHROjGSZwMwigaQIFwLEij32SxQxZdiZq58/ E7X5TEqignwq8f88pNhxh6kXcdnAesHSB+7QmAy2yaERaEhI1WwCrFwqC RV85mc1YOEmnen/5fjMcu2ucnYMG/IccpA9zTy0hE3S/kRUskRNHYlKMG sSpGmjGdGfN8z0GgfNrbV0gnn80cUHmf7JInr+d0Ul6+H233bZXzaku7P DZsWuujGCkGhHGH+052gwWlOtjlPPxP/sdetpNoKGG2zEZaLMX9Qib6Gg auOH3bXQed5w/w8T43C4FuYy+3hYuwZKaJoDPPPFaj8NZLqpiZxgiupcO w==; X-IronPort-AV: E=McAfee;i="6200,9189,10280"; a="315450347" X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="315450347" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:31 -0800 X-IronPort-AV: E=Sophos;i="5.90,165,1643702400"; d="scan'208";a="537630951" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2022 08:38:25 -0800 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ashutosh Dixit Subject: [PATCH v10 5/5] mei: gsc: retrieve the firmware version Date: Tue, 8 Mar 2022 18:36:54 +0200 Message-Id: <20220308163654.942820-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220308163654.942820-1-alexander.usyskin@intel.com> References: <20220308163654.942820-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a hook to retrieve the firmware version of the GSC devices to bus-fixup. GSC has a different MKHI clients GUIDs but the same message structure to retrieve the firmware version as MEI so mei_fwver() can be reused. CC: Ashutosh Dixit Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/bus-fixup.c | 25 +++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 2 ++ 2 files changed, 27 insertions(+) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 67844089db21..59506ba6fc48 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -30,6 +30,12 @@ static const uuid_le mei_nfc_info_guid =3D MEI_UUID_NFC_= INFO; #define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \ 0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb) =20 +#define MEI_UUID_IGSC_MKHI UUID_LE(0xE2C2AFA2, 0x3817, 0x4D19, \ + 0x9D, 0x95, 0x06, 0xB1, 0x6B, 0x58, 0x8A, 0x5D) + +#define MEI_UUID_IGSC_MKHI_FIX UUID_LE(0x46E0C1FB, 0xA546, 0x414F, \ + 0x91, 0x70, 0xB7, 0xF4, 0x6D, 0x57, 0xB4, 0xAD) + #define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \ 0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04) =20 @@ -241,6 +247,23 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev) mei_cldev_disable(cldev); } =20 +static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev) +{ + int ret; + + /* No need to enable the client if nothing is needed from it */ + if (!cldev->bus->fw_f_fw_ver_supported) + return; + + ret =3D mei_cldev_enable(cldev); + if (ret) + return; + + ret =3D mei_fwver(cldev); + if (ret < 0) + dev_err(&cldev->dev, "FW version command failed %d\n", ret); + mei_cldev_disable(cldev); +} /** * mei_wd - wd client on the bus, change protocol version * as the API has changed. @@ -492,6 +515,8 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc), MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), + MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), MEI_FIXUP(MEI_UUID_PAVP, whitelist), diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 9748d14849a1..7e77328142ff 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1577,12 +1577,14 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = =3D { static const struct mei_cfg mei_me_gsc_cfg =3D { MEI_CFG_TYPE_GSC, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* Graphics System Controller Firmware Interface */ static const struct mei_cfg mei_me_gscfi_cfg =3D { MEI_CFG_TYPE_GSCFI, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* --=20 2.32.0