From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4759C433FE for ; Tue, 8 Mar 2022 10:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345672AbiCHKLI (ORCPT ); Tue, 8 Mar 2022 05:11:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345650AbiCHKLD (ORCPT ); Tue, 8 Mar 2022 05:11:03 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB0A82251B for ; Tue, 8 Mar 2022 02:10:07 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id m11-20020a17090a7f8b00b001beef6143a8so1936713pjl.4 for ; Tue, 08 Mar 2022 02:10:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5/KGSiDUR6Oh1qS3ls1eTa+dOJRLWEHzu5UF9HK4Si4=; b=eDoPTw7FlfuMrMk7TZW4fd7c4dDPzW6nXHDmrXSbtsRK6vVG9dhIQ6WrXKOKLXV7aq pz9p+6TzCc1cAGkq3MxA4HyZXLYlRrprzCIS02q3HivJhzYBshHAXuBmUwnDRmScWVih 7AG4tW3YbthMaljSEsRgDx70cRXDSte2hvmI4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5/KGSiDUR6Oh1qS3ls1eTa+dOJRLWEHzu5UF9HK4Si4=; b=RPpgFtF1Hk3Ta4wYOTftppuWM4NoU2n17bfSD3Ax/8UP94uYT8AArkJTyNYD83jSYy 9GV6whHxZnO1MhdijSCr7aFfGuOvws7TP6BQQZXUXLXBtYmiI0+naMEy6DT/BwPALfx8 gzZHZd5yLNuUzebLwiqKf3fFOeVcxIltSbcKSTJ/nrP4oMCnDX/+9NzVBzyV3S/bRl9s d8T+yWjSNjzdzMRz7Kqp2cznN+ZLrOviysdX4F4j7dlv/GDyE4c0dlQC0uMXIKjV9nzF CXCFEtIsrlCo95OysKH4OvLyH4r+j4G8sudRWpzZ2gQcq91/ltlfABgAGSS/fCCftBy7 kCxw== X-Gm-Message-State: AOAM533Grf/lLNObBf855CwpMrH2dJcNz22l0D0qoeJKwQ4Q5I9z2yyq mlOfFZ87UQEfHyMC1vUB5Ejz1w== X-Google-Smtp-Source: ABdhPJxDGvhKYqfJXVj5tcUF1DdM4k4BYagm/EBulkoRUtJ1T6TWbFFUrKL/Ekqds5KSkBCbsoWkLw== X-Received: by 2002:a17:90a:4289:b0:1bc:275b:8986 with SMTP id p9-20020a17090a428900b001bc275b8986mr3758766pjg.153.1646734207017; Tue, 08 Mar 2022 02:10:07 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:06 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 01/11] pinctrl: pinconf-generic: Print arguments for bias-pull-* Date: Tue, 8 Mar 2022 18:09:46 +0800 Message-Id: <20220308100956.2750295-2-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The bias-pull-* properties, or PIN_CONFIG_BIAS_PULL_* pin config parameters, accept optional arguments in ohms denoting the strength of the pin bias. Print these values out in debugfs as well. Fixes: eec450713e5c ("pinctrl: pinconf-generic: Add flag to print arguments= ") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/pinctrl/pinconf-generic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-ge= neric.c index f8edcc88ac01..415d1df8f46a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] =3D { PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NU= LL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true= ), PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, - "input bias pull to pin specific state", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), + "input bias pull to pin specific state", "ohms", true), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, f= alse), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL,= false), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, fal= se), --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9C84C433F5 for ; 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Tue, 08 Mar 2022 02:10:08 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 02/11] pinctrl: mediatek: paris: Fix PIN_CONFIG_BIAS_* readback Date: Tue, 8 Mar 2022 18:09:47 +0800 Message-Id: <20220308100956.2750295-3-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When reading back pin bias settings, if the pin is not in the corresponding bias state, the function should return -EINVAL. Fix this in the mediatek-paris pinctrl library so that the read back state is not littered with bogus a "input bias disabled" combined with "pull up" or "pull down" states. Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements = the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index f9f9110f2107..7037560ecda9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -96,20 +96,16 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, err =3D hw->soc->bias_get_combo(hw, desc, &pullup, &ret); if (err) goto out; + if (ret =3D=3D MTK_PUPD_SET_R1R0_00) + ret =3D MTK_DISABLE; if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) { - if (ret =3D=3D MTK_PUPD_SET_R1R0_00) - ret =3D MTK_DISABLE; + if (ret !=3D MTK_DISABLE) + err =3D -EINVAL; } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) { - /* When desire to get pull-up value, return - * error if current setting is pull-down - */ - if (!pullup) + if (!pullup || ret =3D=3D MTK_DISABLE) err =3D -EINVAL; } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN) { - /* When desire to get pull-down value, return - * error if current setting is pull-up - */ - if (pullup) + if (pullup || ret =3D=3D MTK_DISABLE) err =3D -EINVAL; } } else { --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C690CC433FE for ; Tue, 8 Mar 2022 10:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345698AbiCHKLQ (ORCPT ); Tue, 8 Mar 2022 05:11:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345664AbiCHKLH (ORCPT ); Tue, 8 Mar 2022 05:11:07 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ABD22D1F4 for ; Tue, 8 Mar 2022 02:10:11 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id v4so16704353pjh.2 for ; Tue, 08 Mar 2022 02:10:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0mkHtiSV2mMzHIze/I73DmsEuzqXgbxwstSY7Z96a90=; b=MqSUVQddC79+cfbGd7rJlWaOGFHsKsVv3nxuDEb0d5t14RJm8RgxTNucAJmbCr/HNO aUoOwngfmNE0aHCLm/b7tOtkxPjhGIov5/taNy/0m8E6Jkm4+4R7zGhk6AAp83OyYTXo oghpwvy5LQLRP29YCov4efQTYND6/zUAVpnhY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0mkHtiSV2mMzHIze/I73DmsEuzqXgbxwstSY7Z96a90=; b=vg5WS+hd3YtxgTcchQIMy/EKPCxIixpXqOp3HyPDGjP1X+eZIvINeoUKyjNuk3tPNP EyywnKmcmI1Lk5LnuCm82A00J3idBcjQSZNsdljpenmMpwMiQEEr0wsN38LUd+sBQ2ms lLUkthlgT/AzM4e99tT8lidjkyt54XzftXIcQ6Sc1X5w0t3vy6Oc0nmeIl8Ch0/LVuzV Cyrv02mDlxZGL5rYF7/XxGB1CkHt36GwwXD89T/4H05qNl0F7frlA8zZEcQiHvgLgZeL UUiUoky4uahozcBTVXSAZKdaI2FLheH7A+hq7iWBWX98jaYB8VLG+ar9Yt+ivnmfNWFT wnIQ== X-Gm-Message-State: AOAM531VheBP977AUYEgeiHw2TAraxg43noDozBxn/D1Da0kIVl116D6 mf165lEmimix8jUOrtxZHYjQ+g== X-Google-Smtp-Source: ABdhPJyFRJs7+lYwOkpKY/+oHApZBU4Bq8/m6MYCzudRdQ6PI/A8Wr1FevXk8zt3kT4tAZVslfcZzw== X-Received: by 2002:a17:902:db0d:b0:14f:b047:8d22 with SMTP id m13-20020a170902db0d00b0014fb0478d22mr16271484plx.90.1646734210921; Tue, 08 Mar 2022 02:10:10 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:10 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 03/11] pinctrl: mediatek: paris: Fix "argument" argument type for mtk_pinconf_get() Date: Tue, 8 Mar 2022 18:09:48 +0800 Message-Id: <20220308100956.2750295-4-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For mtk_pinconf_get(), the "argument" argument is typically returned by pinconf_to_config_argument(), which holds the value for a given pinconf parameter. It certainly should not have the type of "enum pin_config_param", which describes the type of the pinconf parameter itself. Change the type to u32, which matches the return type of pinconf_to_config_argument(). Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements = the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 7037560ecda9..c668191933a0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -184,8 +184,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } =20 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - enum pin_config_param param, - enum pin_config_param arg) + enum pin_config_param param, u32 arg) { struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF994C433F5 for ; Tue, 8 Mar 2022 10:10:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345678AbiCHKLV (ORCPT ); Tue, 8 Mar 2022 05:11:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345687AbiCHKLO (ORCPT ); Tue, 8 Mar 2022 05:11:14 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 730113914C for ; Tue, 8 Mar 2022 02:10:13 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id k92so7588728pjh.5 for ; Tue, 08 Mar 2022 02:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=loBNgvfdq/vh+q5b0xP2M4wY6ZA7RodjlaGOVqoQIgQ=; b=FT0q3vmjV4Ofixirx3vGOE4K1bSUTlVNj1zkmWaEB3EX6y7v5tGukfnLjgf/JM4mYu 6HuQCZsYE/huFip+v5Ygfg+JBp7K5XS+cyFGhVfOCY4WJ09FItpUmUbz29q/U6oyX/LU VF3wg4h072C1MLIQjKushAzg7cYYjWfEhnqIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=loBNgvfdq/vh+q5b0xP2M4wY6ZA7RodjlaGOVqoQIgQ=; b=JrKu6n/V+TQMBVB7P9iWEceOtyHeay/DOyzhZ9UCNZs3uUbqZcKoX8vBmPatH799Rf E0vyqCXTurtJemqnGUH5kQ+vxc8x5LeXE5DLyASizKSWpr0KV2sgLRSoHh/9LzpSmFs5 SY6x2qDuwLx155qEBxtUZ7T+r/IeZo/AeAYY9wf33ND4gjCMJy4KIAmGaILGnwJcb/V7 2ZjO+xtf1T+wAhtvDSx5vP8iBj0rz6Jem66XEn2hFfhM6iIKkG7IlrqXYyH3YMUW14m5 w773+5UGzB1PnHI6PQUcLuQzvZsudL/rKGR1COq3B8occYC7bkjDTxyfvHvcVwQC+zVP Cidg== X-Gm-Message-State: AOAM531CWlr/snWGlh+saWP0XzpTtHUGy8BBzg28HocLvXSYdfUiQxTY QPz37ZUwWp54LnU3WHvoOuFb1A== X-Google-Smtp-Source: ABdhPJwF0uYyAvVJHLAKSPzAGWaO6LHCugVgwokBaJgUvBSb8BHs7+KBcJM96IyJnQmOWL8xCiZEuQ== X-Received: by 2002:a17:902:bcc6:b0:151:f36d:2658 with SMTP id o6-20020a170902bcc600b00151f36d2658mr6808467pls.125.1646734212808; Tue, 08 Mar 2022 02:10:12 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:12 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 04/11] pinctrl: mediatek: paris: Fix pingroup pin config state readback Date: Tue, 8 Mar 2022 18:09:49 +0800 Message-Id: <20220308100956.2750295-5-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mtk_pconf_group_get(), used to read back pingroup pin config state, simply returns a set of configs saved from a previous invocation of mtk_pconf_group_set(). This is an unfiltered, unvalidated set passed in from the pinconf core, which does not match the current hardware state. Since the driver library is designed to have one pin per group, pass through mtk_pconf_group_get() to mtk_pinconf_get(), to read back the current pin config state of the only pin in the group. Also drop the assignment of pin config state to the group. Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements = the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index c668191933a0..3bda1aac650b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -732,10 +732,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pc= tldev, unsigned group, unsigned long *config) { struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *grp =3D &hw->groups[group]; =20 - *config =3D hw->groups[group].config; - - return 0; + /* One pin per group only */ + return mtk_pinconf_get(pctldev, grp->pin, config); } =20 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, @@ -751,8 +751,6 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctl= dev, unsigned group, pinconf_to_config_argument(configs[i])); if (ret < 0) return ret; - - grp->config =3D configs[i]; } =20 return 0; --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B5D1C433FE for ; Tue, 8 Mar 2022 10:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343876AbiCHKLZ (ORCPT ); Tue, 8 Mar 2022 05:11:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345695AbiCHKLO (ORCPT ); Tue, 8 Mar 2022 05:11:14 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E05D41F93 for ; Tue, 8 Mar 2022 02:10:15 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id kx6-20020a17090b228600b001bf859159bfso1784816pjb.1 for ; Tue, 08 Mar 2022 02:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oGdSDDQNkWhUKe33kF4Pj3YfO7xrQa9jh28/YPNZHXQ=; b=Xc64V2C3B+kdpVRo+6vOPVtr+wdh+pkujfSHyLdve/PVnzSDyR8OAFEMyRnpsHi6jN eaFxWFfybXPd+S69UPSIo50ij3LSwFkygbdRkOTMcRDO8J6qh0fwexcLjDaxZJh9Yw70 LmXcfY33hytZUxq99hTKvsp3EiXSuWR/bIGeU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oGdSDDQNkWhUKe33kF4Pj3YfO7xrQa9jh28/YPNZHXQ=; b=kJn461DeWO4Yk4lA/haaLBmCQ2sdaeyeEYbRfUor4Jj7of2lezpud2hPg394a/abaL 7KO2esnEX+TTWRURRSPg0LGxTqGFMNVpDeGBfCEajWl4dWla1r57/aU02zyz7SDfQkbD OdyaCPd1O4W/toeYMQyHT9WXzKBPjcs1gKyBiFX91IMWZdfUR2hUOaMhIkCeVWd9hkX6 +5F2uL8czKR/Ty3N+H9va6QzS/0mgH1XjQrLydszNnMXEsO20Jzfzpayf8X7U74UcOqc /E9E5x0NEzkFEzJZiSFzuwgemCrJFPq4N03Zv/t8lNw0aiFQDUATiSMoFj0cmKGeOfim Unfw== X-Gm-Message-State: AOAM532S1C84s3lgi/oSLGJ0k/hu3tNwZngtUszUUMt2AXqtTegGSrwC UrBmj565LYdY9dAq3tneixTN1g== X-Google-Smtp-Source: ABdhPJxTWoED9DBGHXC3bbL4qawyt3m8I6aWwzNtsOMjlw76oLy6YYPISct3R0U33YSX/T9UDF9BFw== X-Received: by 2002:a17:902:d2d1:b0:151:ef69:c27d with SMTP id n17-20020a170902d2d100b00151ef69c27dmr7994753plc.34.1646734214813; Tue, 08 Mar 2022 02:10:14 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:14 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 05/11] pinctrl: mediatek: paris: Drop extra newline in mtk_pctrl_show_one_pin() Date: Tue, 8 Mar 2022 18:09:50 +0800 Message-Id: <20220308100956.2750295-6-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The caller of mtk_pctrl_show_one_pin() is responsible for printing the full line. mtk_pctrl_show_one_pin(), called through mtk_pctrl_dbg_show(), should only produce a string containing the extra information the driver wants included. Drop the extra newlines. Also unbreak the line that is only slightly over 80 characters to make it easier on the eye, and get rid of the braces now that each block in the conditionals is just one line. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration = dump via debugfs.") Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 3bda1aac650b..38a00a906daf 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -634,14 +634,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pullen, pullup); =20 - if (r1 !=3D -1) { - len +=3D scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", - r1, r0); - } else if (rsel !=3D -1) { - len +=3D scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); - } else { - len +=3D scnprintf(buf + len, buf_len - len, "\n"); - } + if (r1 !=3D -1) + len +=3D scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0); + else if (rsel !=3D -1) + len +=3D scnprintf(buf + len, buf_len - len, " (%1d)", rsel); =20 return len; } --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47069C433EF for ; Tue, 8 Mar 2022 10:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345215AbiCHKLa (ORCPT ); Tue, 8 Mar 2022 05:11:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345703AbiCHKLO (ORCPT ); Tue, 8 Mar 2022 05:11:14 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 551B542A11 for ; Tue, 8 Mar 2022 02:10:17 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id c16-20020a17090aa61000b001befad2bfaaso1952315pjq.1 for ; Tue, 08 Mar 2022 02:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YCEYLzINbSJ27Mxc1gQH0RSj42l80KVWvId+vHnO050=; b=VFlI3NcvOJtijZK9dnSyiiARFam7LJ8qmOTLKNc6BwqUaKaUlKU4+8f3icJASzdiix OthB+gk44a6lieASchFK+lLJcJ+pUaxnkcomxmj4/ef/plXlIWS42RAYtXU1/9+aRBkL h4lX3waAzusF3Hgh0IGsk99Q5//h4ggK0BCFc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YCEYLzINbSJ27Mxc1gQH0RSj42l80KVWvId+vHnO050=; b=I4kt9E3V6dY3lQKf2q/2iXxinQWgqbUIlYHok0rA85ywnrGB+dZpAMBSj4E0TKQw2B NhZC9L+qYxI1MHZZrKPvnMtPSJEtCB0mSJxjItyPCd1CrKN/IEawBEtisk4fFO0nmw19 YP2OGf3Uxlz3c8gJ5v1uNlzGZu18lvrfGrDMUgOOM9MVooQ+9JB/3YRuBfi0QGEjgQls mn4NJ/hORiVOJPnhLqpD8MeAO+llMtYDYXxG5HI0MoGRsqF7V7Ysu5/lB9wGG9J0T6eL 1oOP/Sma3aGRyLiGzJ0unIij52YJnvmFXKpz1IJ4Izao35/NmcITnI62536W6+zR9vNh QkOg== X-Gm-Message-State: AOAM531uLhU0EzGX8UNf6OKCI/lVdyF7hNbcnOosDphDCQQlO9zd5zq6 G2xF2nuLB6ZyLucKW4QqxswFig== X-Google-Smtp-Source: ABdhPJxvlMwg053TxzUU1yh1e9ywYI4FTa148KhAT6lQrsDtI61chzmA/3TvSGQDlNZ1lmoCT8ZRig== X-Received: by 2002:a17:902:ef4d:b0:14f:e82b:25fd with SMTP id e13-20020a170902ef4d00b0014fe82b25fdmr16531295plx.80.1646734216854; Tue, 08 Mar 2022 02:10:16 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:16 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 06/11] pinctrl: mediatek: paris: Skip custom extra pin config dump for virtual GPIOs Date: Tue, 8 Mar 2022 18:09:51 +0800 Message-Id: <20220308100956.2750295-7-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Virtual GPIOs do not have any hardware state associated with them. Any attempt to read back hardware state for these pins result in error codes. Skip dumping extra pin config information for these virtual GPIOs. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration = dump via debugfs.") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 38a00a906daf..39487e0c2726 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -581,6 +581,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, if (gpio >=3D hw->soc->npins) return -EINVAL; =20 + if (mtk_is_virt_gpio(hw, gpio)) + return -EINVAL; + desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; pinmux =3D mtk_pctrl_get_pinmux(hw, gpio); if (pinmux >=3D hw->soc->nfuncs) --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15BF7C433EF for ; Tue, 8 Mar 2022 10:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345689AbiCHKLd (ORCPT ); Tue, 8 Mar 2022 05:11:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345697AbiCHKLQ (ORCPT ); Tue, 8 Mar 2022 05:11:16 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8095737A32 for ; Tue, 8 Mar 2022 02:10:19 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id z4so16000975pgh.12 for ; Tue, 08 Mar 2022 02:10:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AN8AQlXUHY8dzoH7tRwXIxVaLJny20Q1qo/2QYSwxHk=; b=bvMT2jkFovcX32w1PT4TTZsspSO3e8SRTk4q/igiSkmk1cUsE98JgeoEY/AL+dcqqr jS34mDr+t3NiSxzysNh51S4J/5tPFK4zct+75oThi+ZUuqpucK6VNZsvlnz481UDatKe G827DuIdlh6BrRcFNn62siIpYzUjZpPJMfngo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AN8AQlXUHY8dzoH7tRwXIxVaLJny20Q1qo/2QYSwxHk=; b=DBEzVXNo/X6H6VYgECJ0N1tPbE/kJUxXngARja+KBMs/6ZZ+Ft45h4ih7UfUdU76O+ TbEPn0XeoQXloIoown7D/RylLaPN8FKBd1e2Hn8m2ZSQnpBPu/sLYCTeoHmoswpcBGes HKEezPCh/e3eQ/fnJAjDfXmC+5FpmrQzO8Lqv4FiIE4TtXHLsJeVAvBl7f/QXmQHE8T5 MQOl970EHDhTR7FV+UTdQ6LGf6TNTKPuVYZ2dGu6QSq3sLBaBxCkkaBodQczzGfSiRIK Wfl14N9YKYtduvmjXy/vyiq6ByCzvLS3V8YSKgD8jxWVASEtMTrVFA4lzwJqwau9Jpm0 rSxQ== X-Gm-Message-State: AOAM530Ba3zR7tLyb+Cpx5U3uW+zMiFVmsZbGwAjsMShJUFgLjjswmVX BSz/HTCKBuIlgANjGtvzAeKvYg== X-Google-Smtp-Source: ABdhPJwL9D+0SHRBS3XhC6nSpflTUI/0erBZkhgu01psg9Z8qe64mE6poyKANJlHUDzPcjgGtUO/Ag== X-Received: by 2002:a63:2ccb:0:b0:37c:626c:d7e with SMTP id s194-20020a632ccb000000b0037c626c0d7emr13324616pgs.290.1646734218922; Tue, 08 Mar 2022 02:10:18 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:18 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 07/11] pinctrl: mediatek: paris: Rework mtk_pinconf_{get,set} switch/case logic Date: Tue, 8 Mar 2022 18:09:52 +0800 Message-Id: <20220308100956.2750295-8-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current code deals with optional features by testing for the function pointers and returning -ENOTSUPP if it is not valid. This is done for multiple pin config settings and results in the code that handles the supporting cases to get indented by one level. This is aggrevated by the fact that some features require another level of conditionals. Instead of assigning the same error code in all unsupported optional feature cases, simply have that error code as the default, and break out of the switch/case block whenever a feature is unsupported, or an error is returned. This reduces indentation by one level for the useful code. Also replace the goto statements with break statements. The result is the same, as the gotos simply exit the switch/case block, which can also be achieved with a break statement. With the latter the intent is clear and easier to understand. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 144 ++++++++++------------- 1 file changed, 61 insertions(+), 83 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 39487e0c2726..1ea3f3c54ef3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -79,37 +79,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); u32 param =3D pinconf_to_config_param(*config); - int pullup, err, reg, ret =3D 1; + int pullup, reg, err =3D -ENOTSUPP, ret =3D 1; const struct mtk_pin_desc *desc; =20 - if (pin >=3D hw->soc->npins) { - err =3D -EINVAL; - goto out; - } + if (pin >=3D hw->soc->npins) + return -EINVAL; + desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[pin]; =20 switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get_combo) { - err =3D hw->soc->bias_get_combo(hw, desc, &pullup, &ret); - if (err) - goto out; - if (ret =3D=3D MTK_PUPD_SET_R1R0_00) - ret =3D MTK_DISABLE; - if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) { - if (ret !=3D MTK_DISABLE) - err =3D -EINVAL; - } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) { - if (!pullup || ret =3D=3D MTK_DISABLE) - err =3D -EINVAL; - } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN) { - if (pullup || ret =3D=3D MTK_DISABLE) - err =3D -EINVAL; - } - } else { - err =3D -ENOTSUPP; + if (!hw->soc->bias_get_combo) + break; + err =3D hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + break; + if (ret =3D=3D MTK_PUPD_SET_R1R0_00) + ret =3D MTK_DISABLE; + if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) { + if (ret !=3D MTK_DISABLE) + err =3D -EINVAL; + } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) { + if (!pullup || ret =3D=3D MTK_DISABLE) + err =3D -EINVAL; + } else if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN) { + if (pullup || ret =3D=3D MTK_DISABLE) + err =3D -EINVAL; } break; case PIN_CONFIG_SLEW_RATE: @@ -119,7 +116,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: err =3D mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* CONFIG Current direction return value * ------------- ----------------- ---------------------- * OUTPUT_ENABLE output 1 (=3D HW value) @@ -134,23 +131,21 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctlde= v, case PIN_CONFIG_INPUT_SCHMITT_ENABLE: err =3D mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* return error when in output mode * because schmitt trigger only work in input mode */ if (ret) { err =3D -EINVAL; - goto out; + break; } =20 err =3D mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret); - break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_get) - err =3D hw->soc->drive_get(hw, desc, &ret); - else - err =3D -ENOTSUPP; + if (!hw->soc->drive_get) + break; + err =3D hw->soc->drive_get(hw, desc, &ret); break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -160,23 +155,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctlde= v, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_get) { - pullup =3D param =3D=3D MTK_PIN_CONFIG_PU_ADV; - err =3D hw->soc->adv_pull_get(hw, desc, pullup, &ret); - } else - err =3D -ENOTSUPP; + if (!hw->soc->adv_pull_get) + break; + pullup =3D param =3D=3D MTK_PIN_CONFIG_PU_ADV; + err =3D hw->soc->adv_pull_get(hw, desc, pullup, &ret); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_get) - err =3D hw->soc->adv_drive_get(hw, desc, &ret); - else - err =3D -ENOTSUPP; + if (!hw->soc->adv_drive_get) + break; + err =3D hw->soc->adv_drive_get(hw, desc, &ret); break; - default: - err =3D -ENOTSUPP; } =20 -out: if (!err) *config =3D pinconf_to_config_packed(param, ret); =20 @@ -188,33 +178,29 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctlde= v, unsigned int pin, { struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; - int err =3D 0; + int err =3D -ENOTSUPP; u32 reg; =20 - if (pin >=3D hw->soc->npins) { - err =3D -EINVAL; - goto err; - } + if (pin >=3D hw->soc->npins) + return -EINVAL; + desc =3D (const struct mtk_pin_desc *)&hw->soc->pins[pin]; =20 switch ((u32)param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_set_combo) - err =3D hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); - else - err =3D -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err =3D hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set_combo) - err =3D hw->soc->bias_set_combo(hw, desc, 1, arg); - else - err =3D -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err =3D hw->soc->bias_set_combo(hw, desc, 1, arg); break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set_combo) - err =3D hw->soc->bias_set_combo(hw, desc, 0, arg); - else - err =3D -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err =3D hw->soc->bias_set_combo(hw, desc, 0, arg); break; case PIN_CONFIG_OUTPUT_ENABLE: err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, @@ -223,7 +209,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev,= unsigned int pin, * does not have SMT control */ if (err !=3D -ENOTSUPP) - goto err; + break; =20 err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -232,7 +218,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev,= unsigned int pin, /* regard all non-zero value as enable */ err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg); if (err) - goto err; + break; =20 err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); @@ -245,7 +231,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev,= unsigned int pin, err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, arg); if (err) - goto err; + break; =20 err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -257,15 +243,14 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctlde= v, unsigned int pin, */ err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg); if (err) - goto err; + break; =20 err =3D mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg); break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_set) - err =3D hw->soc->drive_set(hw, desc, arg); - else - err =3D -ENOTSUPP; + if (!hw->soc->drive_set) + break; + err =3D hw->soc->drive_set(hw, desc, arg); break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -275,26 +260,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctlde= v, unsigned int pin, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_set) { - bool pullup; - - pullup =3D param =3D=3D MTK_PIN_CONFIG_PU_ADV; - err =3D hw->soc->adv_pull_set(hw, desc, pullup, - arg); - } else - err =3D -ENOTSUPP; + if (!hw->soc->adv_pull_set) + break; + err =3D hw->soc->adv_pull_set(hw, desc, + (param =3D=3D MTK_PIN_CONFIG_PU_ADV), + arg); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_set) - err =3D hw->soc->adv_drive_set(hw, desc, arg); - else - err =3D -ENOTSUPP; + if (!hw->soc->adv_drive_set) + break; + err =3D hw->soc->adv_drive_set(hw, desc, arg); break; - default: - err =3D -ENOTSUPP; } =20 -err: return err; } =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DF97C433EF for ; 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Tue, 08 Mar 2022 02:10:20 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: Chen-Yu Tsai , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v2 08/11] pinctrl: mediatek: paris: Support generic PIN_CONFIG_DRIVE_STRENGTH_UA Date: Tue, 8 Mar 2022 18:09:53 +0800 Message-Id: <20220308100956.2750295-9-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the MediaTek chips that utilize the Paris pinctrl driver library support a lower drive strength (<=3D 1mA) than the standard drive strength settings (2~16 mA) on certain pins. This was previously supported by the custom MTK_PIN_CONFIG_DRV_ADV parameter along with the "mediatek,drive-strength-adv" device tree property. The drive strength values for this hardware are 125, 250, 500, and 1000 mA, and can be readily described by the existing "drive-strength-microamp" property, which then gets parsed by the generic pinconf library into the parameter PIN_CONFIG_DRIVE_STRENGTH_UA. Add support for PIN_CONFIG_DRIVE_STRENGTH_UA while keeping the old custom parameter around for backward compatibility. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-paris.c | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 1ea3f3c54ef3..25d999848c2a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] =3D { "func12", "func13", "func14", "func15", }; =20 +/* + * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV + * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs. + * + * The custom value encodes three hardware bits as follows: + * + * | Bits | + * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA) + * ------------------------------------------------ + * | x | x | 0 | disabled, use standard drive strength + * ------------------------------------- + * | 0 | 0 | 1 | 125 uA + * | 0 | 1 | 1 | 250 uA + * | 1 | 0 | 1 | 500 uA + * | 1 | 1 | 1 | 1000 uA + */ +static const int mtk_drv_adv_uA[] =3D { 125, 250, 500, 1000 }; + +static int mtk_drv_adv_to_uA(int val) +{ + /* This should never happen. */ + if (WARN_ON_ONCE(val < 0 || val > 7)) + return -EINVAL; + + /* Bit 0 simply enables this hardware part */ + if (!(val & BIT(0))) + return -EINVAL; + + return mtk_drv_adv_uA[(val >> 1)]; +} + +static int mtk_drv_uA_to_adv(int val) +{ + switch (val) { + case 125: + return 0x1; + case 250: + return 0x3; + case 500: + return 0x5; + case 1000: + return 0x7; + } + + return -EINVAL; +} + static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) @@ -145,8 +192,35 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: if (!hw->soc->drive_get) break; + + if (hw->soc->adv_drive_get) { + err =3D hw->soc->adv_drive_get(hw, desc, &ret); + if (!err) { + err =3D mtk_drv_adv_to_uA(ret); + if (err > 0) { + /* PIN_CONFIG_DRIVE_STRENGTH_UA used */ + err =3D -EINVAL; + break; + } + } + } + err =3D hw->soc->drive_get(hw, desc, &ret); break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_get) + break; + + err =3D hw->soc->adv_drive_get(hw, desc, &ret); + if (err) + break; + err =3D mtk_drv_adv_to_uA(ret); + if (err < 0) + break; + + ret =3D err; + err =3D 0; + break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: reg =3D (param =3D=3D MTK_PIN_CONFIG_TDSEL) ? @@ -252,6 +326,15 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev= , unsigned int pin, break; err =3D hw->soc->drive_set(hw, desc, arg); break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_set) + break; + + err =3D mtk_drv_uA_to_adv(arg); + if (err < 0) + break; + err =3D hw->soc->adv_drive_set(hw, desc, err); + break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: reg =3D (param =3D=3D MTK_PIN_CONFIG_TDSEL) ? @@ -720,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctl= dev, unsigned group, { struct mtk_pinctrl *hw =3D pinctrl_dev_get_drvdata(pctldev); struct mtk_pinctrl_group *grp =3D &hw->groups[group]; + bool drive_strength_uA_found =3D false; + bool adv_drve_strength_found =3D false; int i, ret; =20 for (i =3D 0; i < num_configs; i++) { @@ -728,8 +813,22 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pct= ldev, unsigned group, pinconf_to_config_argument(configs[i])); if (ret < 0) return ret; + + if (pinconf_to_config_param(configs[i]) =3D=3D PIN_CONFIG_DRIVE_STRENGTH= _UA) + drive_strength_uA_found =3D true; + if (pinconf_to_config_param(configs[i]) =3D=3D MTK_PIN_CONFIG_DRV_ADV) + adv_drve_strength_found =3D true; } =20 + /* + * Disable advanced drive strength mode if drive-strength-microamp + * is not set. However, mediatek,drive-strength-adv takes precedence + * as its value can explicitly request the mode be enabled or not. + */ + if (hw->soc->adv_drive_set && !drive_strength_uA_found && + !adv_drve_strength_found) + hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0); + return 0; } =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91201C433F5 for ; Tue, 8 Mar 2022 10:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345757AbiCHKLp (ORCPT ); Tue, 8 Mar 2022 05:11:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345712AbiCHKLW (ORCPT ); Tue, 8 Mar 2022 05:11:22 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65D4F39815 for ; Tue, 8 Mar 2022 02:10:23 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id bx5so16687119pjb.3 for ; Tue, 08 Mar 2022 02:10:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2QEmSIEQFxB2Wc84ArL948mjUQ6bp5HIyQKnBGn7bWA=; b=e5hlsZ8M6FrXSm5O1f+PV6XxTqqhgfqU73P/IYJh4E0hSqqWGYVO0tRmckACGlOYw7 /UOEQpi/SLYAuvbg6741+WVuaxEb1MV6seNKX4C0R7k/xBIHIXhx+GyyjIUl/PxX9nq+ Gio7RkFHIVNjGn7Ma5LMRTdCDaTpZuUesPNVY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2QEmSIEQFxB2Wc84ArL948mjUQ6bp5HIyQKnBGn7bWA=; b=vGFnKP6l7/eSsagPIhRbaFygWTgGPoiCVvhOxKmogGzND3kwnIYEYTDA/SL66bvAXV 7QFNeZ6fCXN2OJE7TEFM0HZa6/vY4rMnWUyICAZfSZby4ZVO1wtw6Deo0m9Gat2oQuDO xPRbkyE8wyujQftJC/9RRJZBWz1FyuMbmt4JktiRLxq2koHne5G0987FRwIhhhiXRb4/ r5vIcmSy5JVoVGzHQknVYvYAXw4dpaL7DN0RUMwnt0mpFS+m0zIyCUCugRbdOb4QgZse /MAlEeSJJgQuFjQcz9LQiolxcWOD+ICl2UhV4tcrKI3Pep/QLgtYe7dVEN4HykSty+m9 sYoQ== X-Gm-Message-State: AOAM532PjK1M9UOFgc0DB763qPrpNYDuzp9p8XMFdvVqc1bLyB0GyxOQ V2K5TCbL7wGadBpEmuiTny18pw== X-Google-Smtp-Source: ABdhPJzUIGM7/aLnoqVgZbi6x5gKdbjCUJrwbdnqiMSuTVYjMyywx1haZYeF+oYRHLRbmkLV6lNEOg== X-Received: by 2002:a17:902:f785:b0:14d:d2b6:b7c with SMTP id q5-20020a170902f78500b0014dd2b60b7cmr16603240pln.68.1646734222911; Tue, 08 Mar 2022 02:10:22 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:22 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai Subject: [PATCH v2 09/11] pinctrl: mediatek: pinctrl-moore: Simplify with dev_err_probe() Date: Tue, 8 Mar 2022 18:09:54 +0800 Message-Id: <20220308100956.2750295-10-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-moore.c | 25 +++++++++--------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/med= iatek/pinctrl-moore.c index 5bfaa84839c7..526faaebaf77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw) int mtk_moore_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc) { + struct device *dev =3D &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pd= ev, hw->soc =3D soc; hw->dev =3D &pdev->dev; =20 - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } =20 hw->base =3D devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *p= dev, =20 /* Setup groups descriptions per SoC types */ err =3D mtk_build_groups(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build groups\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build groups\n"); =20 /* Setup functions descriptions per SoC types */ err =3D mtk_build_functions(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build functions\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build functions\n"); =20 /* For able to make pinctrl_claim_hogs, we must not enable pinctrl * until all groups and functions are being added one. @@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pd= ev, =20 /* Build gpiochip should be after pinctrl_enable is done */ err =3D mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); =20 platform_set_drvdata(pdev, hw); =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD02C433EF for ; Tue, 8 Mar 2022 10:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345751AbiCHKLn (ORCPT ); Tue, 8 Mar 2022 05:11:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345718AbiCHKLW (ORCPT ); Tue, 8 Mar 2022 05:11:22 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7230A42A18 for ; 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Tue, 08 Mar 2022 02:10:24 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:73f8:5e3f:6894:8f44]) by smtp.gmail.com with ESMTPSA id k19-20020a056a00135300b004f734327960sm1707553pfu.106.2022.03.08.02.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Mar 2022 02:10:24 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai Subject: [PATCH v2 10/11] pinctrl: mediatek: pinctrl-paris: Simplify with dev_err_probe() Date: Tue, 8 Mar 2022 18:09:55 +0800 Message-Id: <20220308100956.2750295-11-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-paris.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/med= iatek/pinctrl-paris.c index 25d999848c2a..b587379eef4b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -1024,6 +1024,7 @@ static int mtk_pctrl_build_state(struct platform_devi= ce *pdev) int mtk_paris_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc) { + struct device *dev =3D &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -1036,11 +1037,9 @@ int mtk_paris_pinctrl_probe(struct platform_device *= pdev, hw->soc =3D soc; hw->dev =3D &pdev->dev; =20 - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } =20 hw->base =3D devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -1065,10 +1064,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *= pdev, spin_lock_init(&hw->lock); =20 err =3D mtk_pctrl_build_state(pdev); - if (err) { - dev_err(&pdev->dev, "build state failed: %d\n", err); - return -EINVAL; - } + if (err) + return dev_err_probe(dev, err, "build state failed\n"); =20 /* Copy from internal struct mtk_pin_desc to register to the core */ pins =3D devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), @@ -1106,10 +1103,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *= pdev, =20 /* Build gpiochip should be after pinctrl_enable is done */ err =3D mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); =20 platform_set_drvdata(pdev, hw); =20 --=20 2.35.1.616.g0bdcbb4464-goog From nobody Sun Sep 22 07:41:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6167BC433EF for ; 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Tue, 08 Mar 2022 02:10:26 -0800 (PST) From: Chen-Yu Tsai To: Sean Wang , Linus Walleij , Matthias Brugger Cc: AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai Subject: [PATCH v2 11/11] pinctrl: mediatek: pinctrl-mtk-common: Simplify with dev_err_probe() Date: Tue, 8 Mar 2022 18:09:56 +0800 Message-Id: <20220308100956.2750295-12-wenst@chromium.org> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308100956.2750295-1-wenst@chromium.org> References: <20220308100956.2750295-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 25 ++++++++----------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.c index 5f7c421ab6e7..6f8dfa6ae5a0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1013,10 +1013,12 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, = struct platform_device *pdev) return mtk_eint_do_init(pctl->eint); } =20 +/* This is used as a common probe function */ int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap) { + struct device *dev =3D &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; struct device_node *np =3D pdev->dev.of_node, *node; @@ -1030,10 +1032,9 @@ int mtk_pctrl_init(struct platform_device *pdev, platform_set_drvdata(pdev, pctl); =20 prop =3D of_find_property(np, "pins-are-numbered", NULL); - if (!prop) { - dev_err(&pdev->dev, "only support pins-are-numbered format\n"); - return -EINVAL; - } + if (!prop) + return dev_err_probe(dev, -EINVAL, + "only support pins-are-numbered format\n"); =20 node =3D of_parse_phandle(np, "mediatek,pctl-regmap", 0); if (node) { @@ -1043,8 +1044,7 @@ int mtk_pctrl_init(struct platform_device *pdev, } else if (regmap) { pctl->regmap1 =3D regmap; } else { - dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); - return -EINVAL; + return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); } =20 /* Only 8135 has two base addr, other SoCs have only one. */ @@ -1057,10 +1057,8 @@ int mtk_pctrl_init(struct platform_device *pdev, =20 pctl->devdata =3D data; ret =3D mtk_pctrl_build_state(pdev); - if (ret) { - dev_err(&pdev->dev, "build state failed: %d\n", ret); - return -EINVAL; - } + if (ret) + return dev_err_probe(dev, ret, "build state failed\n"); =20 pins =3D devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), GFP_KERNEL); @@ -1081,10 +1079,9 @@ int mtk_pctrl_init(struct platform_device *pdev, =20 pctl->pctl_dev =3D devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, pctl); - if (IS_ERR(pctl->pctl_dev)) { - dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return PTR_ERR(pctl->pctl_dev); - } + if (IS_ERR(pctl->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev), + "Couldn't register pinctrl driver\n"); =20 pctl->chip =3D devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); if (!pctl->chip) --=20 2.35.1.616.g0bdcbb4464-goog