From nobody Sun Sep 22 09:30:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A814AC433EF for ; Tue, 8 Mar 2022 07:24:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344587AbiCHHZx (ORCPT ); Tue, 8 Mar 2022 02:25:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230012AbiCHHZr (ORCPT ); Tue, 8 Mar 2022 02:25:47 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C1DE3DA49; Mon, 7 Mar 2022 23:24:46 -0800 (PST) X-UUID: 761774f7553a4f738949973e9d494bd7-20220308 X-UUID: 761774f7553a4f738949973e9d494bd7-20220308 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1803571036; Tue, 08 Mar 2022 15:24:41 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Mar 2022 15:24:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Mar 2022 15:24:41 +0800 From: Trevor Wu To: , , , CC: , , , , , , , Subject: [PATCH 1/5] ASoC: mediatek: mt8195: add reset controller Date: Tue, 8 Mar 2022 15:24:31 +0800 Message-ID: <20220308072435.22460-2-trevor.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220308072435.22460-1-trevor.wu@mediatek.com> References: <20220308072435.22460-1-trevor.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Audio hardware is possibly used in the firmware stage, so resetting audio hardware before regcache records default register values is required. Signed-off-by: Trevor Wu Reviewed-by: AngeloGioacchino Del Regno --- sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c b/sound/soc/mediate= k/mt8195/mt8195-afe-pcm.c index 550636500949..72b2c6d629b9 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-pcm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "mt8195-afe-common.h" #include "mt8195-afe-clk.h" #include "mt8195-reg.h" @@ -3056,6 +3057,7 @@ static int mt8195_afe_pcm_dev_probe(struct platform_d= evice *pdev) struct mtk_base_afe *afe; struct mt8195_afe_private *afe_priv; struct device *dev =3D &pdev->dev; + struct reset_control *rstc; int i, irq_id, ret; struct snd_soc_component *component; =20 @@ -3092,6 +3094,20 @@ static int mt8195_afe_pcm_dev_probe(struct platform_= device *pdev) return ret; } =20 + /* reset controller to reset audio regs before regmap cache */ + rstc =3D devm_reset_control_get_exclusive(dev, "audiosys"); + if (IS_ERR(rstc)) { + ret =3D PTR_ERR(rstc); + dev_err(dev, "could not get audiosys reset:%d\n", ret); + return ret; + } + + ret =3D reset_control_reset(rstc); + if (ret) { + dev_err(dev, "failed to trigger audio reset:%d\n", ret); + return ret; + } + spin_lock_init(&afe_priv->afe_ctrl_lock); =20 mutex_init(&afe->irq_alloc_lock); --=20 2.18.0