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Wysocki" , Viresh Kumar , Rob Herring , Liam Girdwood , Mark Brown , Matthias Brugger , Jia-Wei Chang CC: , , , , , , , , , , , Jia-Wei Chang Subject: [PATCH 1/4] dt-bindings: cpufreq: mediatek: transform cpufreq-mediatek into yaml Date: Mon, 7 Mar 2022 20:21:48 +0800 Message-ID: <20220307122151.11666-2-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220307122151.11666-1-jia-wei.chang@mediatek.com> References: <20220307122151.11666-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" convert Mediatek cpufreq devicetree binding to YAML. Signed-off-by: Jia-Wei Chang --- .../bindings/cpufreq/cpufreq-mediatek.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-media= tek.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yam= l b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml new file mode 100644 index 000000000000..584946eb3790 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek CPUFREQ driver Device Tree Bindings + +maintainers: + - Jia-Wei Chang + +description: | + CPUFREQ is used for scaling clock frequency of CPUs. + The module cooperates with CCI DEVFREQ to manage frequency for some Medi= atek + SoCs. + +properties: + clocks: + items: + - description: + The first one is the multiplexer for clock input of CPU cluster. + - description: + The other is used as an intermediate clock source when the origi= nal + CPU is under transition and not stable yet. + + clock-names: + items: + - const: "cpu" + - const: "intermediate" + + operating-points-v2: + description: + For details, please refer to + Documentation/devicetree/bindings/opp/opp-v2.yaml + + opp-table: true + + proc-supply: + description: + Phandle of the regulator for CPU cluster that provides the supply + voltage. + + sram-supply: + description: + Phandle of the regulator for sram of CPU cluster that provides the s= upply + voltage. When present, the cpufreq driver needs to do "voltage track= ing" + to step by step scale up/down Vproc and Vsram to fit SoC specific ne= eds. + When absent, the voltage scaling flow is handled by hardware, hence = no + software "voltage tracking" is needed. + + "#cooling-cells": + description: + For details, please refer to + Documentation/devicetree/bindings/thermal/thermal-cooling-devices.ya= ml + +required: + - clocks + - clock-names + - operating-points-v2 + - proc-supply + +additionalProperties: false + +examples: + - | + /* Example 1 (MT7623 SoC) */ + #include + cpu_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + opp-598000000 { + opp-hz =3D /bits/ 64 <598000000>; + opp-microvolt =3D <1050000>; + }; + + /* ... */ + + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a7"; + reg =3D <0x0>; + clocks =3D <&infracfg CLK_INFRA_CPUSEL>, <&apmixedsys CLK_APMIXED_= MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cpu_opp_table>; + proc-supply =3D <&mt6380_vcpu_reg>; + #cooling-cells =3D <2>; + }; + + /* ... */ + + }; + + - | + /* Example 2 (MT8173 SoC) */ + #include + cluster1_opp: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + opp-507000000 { + opp-hz =3D /bits/ 64 <507000000>; + opp-microvolt =3D <828000>; + }; + + /* ... */ + + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0x100>; + enable-method =3D "psci"; + cpu-idle-states =3D <&CPU_SLEEP_0>; + #cooling-cells =3D <2>; + clocks =3D <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED= _MAINPLL>; + clock-names =3D "cpu", "intermediate"; + operating-points-v2 =3D <&cluster1_opp>; + proc-supply =3D <&mt6397_vpca15_reg>; + }; + + /* ... */ + + }; --=20 2.18.0