From nobody Tue Jun 23 11:16:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EAEDC433F5 for ; Mon, 7 Mar 2022 08:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236206AbiCGIeW (ORCPT ); Mon, 7 Mar 2022 03:34:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236203AbiCGIeS (ORCPT ); Mon, 7 Mar 2022 03:34:18 -0500 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3E2713D26 for ; Mon, 7 Mar 2022 00:33:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646642001; x=1678178001; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=mhhc4KiuxbavjISsXlMiWu5G1CPhO3zCf6Xz+ptSOuQ=; b=JSRk6HM0syu9KGBVQr2Ht/qUIIYLdf/iFjisceZMBQiAmzeareXoqfy8 e3e0XjfvG6ClxVBX2L3t08o/YJPux9NGKgcAMQHzc2qd3TiVbx3WB0pnH 3fjwghQLOqmTdR5hP0rxDYi9hkBA3pzufFgtAGwVz03wYOqGUFMRGECcz 7+p7k1A4+0EMpHRf7ebC+mBSJDq6Vzb3+UaVOpf+22pNnfy5i7AnzG/C8 D0ykAYAY5tH/exwej/ZMhkON0QiX2z+OECGXeFNpBa8yLKYWydz9/2y+G 6Dor9/0I944RNmECFxP+tpF9RZDP07tfmR99OHbB+ekdsOBUvDdw1exeN g==; From: Vincent Whitchurch To: Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski CC: , Vincent Whitchurch , Alim Akhtar , , , Subject: [PATCH] clocksource/drivers/exynos_mct: Support using only local timer Date: Mon, 7 Mar 2022 09:32:55 +0100 Message-ID: <20220307083255.1577365-1-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 boots first and starts the global FRC and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots, we should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this, add a module param to set the local timer starting index. If this parameter is non-zero, the global timer clock events device is not registered and we don't write to the global FRC if it is already started. Signed-off-by: Vincent Whitchurch --- drivers/clocksource/exynos_mct.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index f29c812b70c9..7ea2919b1808 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -33,7 +33,7 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x))) #define EXYNOS4_MCT_L_MASK (0xffffff00) =20 #define MCT_L_TCNTB_OFFSET (0x00) @@ -77,6 +77,13 @@ static unsigned long clk_rate; static unsigned int mct_int_type; static int mct_irqs[MCT_NR_IRQS]; =20 +/* + * First local timer index to use. If non-zero, global + * timer is not written to. + */ +static unsigned int mct_local_idx; +module_param_named(local_idx, mct_local_idx, int, 0); + struct mct_clock_event_device { struct clock_event_device evt; unsigned long base; @@ -157,6 +164,17 @@ static void exynos4_mct_frc_start(void) u32 reg; =20 reg =3D readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); + + /* + * If the FRC is already running, we don't need to start it again. We + * could probably just do this on all systems, but, to avoid any risk + * for regressions, we only do it on systems where it's absolutely + * necessary (i.e., on systems where writes to the global registers + * need to be avoided). + */ + if (mct_local_idx && (reg & MCT_G_TCON_START)) + return; + reg |=3D MCT_G_TCON_START; exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); } @@ -449,7 +467,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt =3D &mevt->evt; =20 - mevt->base =3D EXYNOS4_MCT_L_BASE(cpu); + mevt->base =3D EXYNOS4_MCT_L_BASE(mct_local_idx + cpu); snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); =20 evt->name =3D mevt->name; @@ -554,13 +572,14 @@ static int __init exynos4_timer_interrupts(struct dev= ice_node *np, } else { for_each_possible_cpu(cpu) { int mct_irq; + unsigned int irqidx =3D MCT_L0_IRQ + mct_local_idx + cpu; struct mct_clock_event_device *pcpu_mevt =3D per_cpu_ptr(&percpu_mct_tick, cpu); =20 pcpu_mevt->evt.irq =3D -1; - if (MCT_L0_IRQ + cpu >=3D ARRAY_SIZE(mct_irqs)) + if (irqidx >=3D ARRAY_SIZE(mct_irqs)) break; - mct_irq =3D mct_irqs[MCT_L0_IRQ + cpu]; + mct_irq =3D mct_irqs[irqidx]; =20 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -619,7 +638,7 @@ static int __init mct_init_dt(struct device_node *np, u= nsigned int int_type) if (ret) return ret; =20 - return exynos4_clockevent_init(); + return (mct_local_idx =3D=3D 0) ? exynos4_clockevent_init() : ret; } =20 =20 --=20 2.34.1