From nobody Tue Jun 23 11:16:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D642DC433EF for ; Mon, 7 Mar 2022 06:45:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235624AbiCGGqp (ORCPT ); Mon, 7 Mar 2022 01:46:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234325AbiCGGqm (ORCPT ); Mon, 7 Mar 2022 01:46:42 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9221560049 for ; Sun, 6 Mar 2022 22:45:48 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id e13so12928896plh.3 for ; Sun, 06 Mar 2022 22:45:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rciQvAdJAp0wrAJqlzPMAqWlc/W/aINkrwMy8JhMIqo=; b=v9zmeOjOXqd6A+THRKPCA5156dw0B/TgfqvxUnreRlNEEpvCLldrX90bCAXEEx17C7 3c8BfsQVMExrdiNmewW20zwqs3i1ZlP0kN34k7lcOcyp6jwUcZpgoRljCybxyyo5ztte ElSSwSCSI/gfUopxe84JfxeckpNijlFoAx7rRXwxbspMdh0iIET/5yv2vbgbZ/7DnmC6 czH+yIu2o5ejTcWuL7C/GI0KiDCJTv0lpzzfiBw821f01VZMh825k8IE81EiYszlDgQG 9bgYgm+46piTfec1udyGAPhdOGQ1y1zSo2kfcz4njBDatOJpqME30zC6JQj3W3B0vjds /qkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rciQvAdJAp0wrAJqlzPMAqWlc/W/aINkrwMy8JhMIqo=; b=5eSTnUmjYvGNaccpLRU+i0zupCG7tXhFGkYc7aDIlXVCCY1dCs1vuVO9xPz6JHzdNG D9Zl5vrkRDVU7dNx9JiTVqxbtYXTMTLg5XMpLzktjdpeiqE3m36/JHVQRwPXjlJU8/Oc S0+61Jascqe9t65jGXvG5MMuMg/xwrkhWjMUs6ZVE0ih7RDQs3yq/pxl1FgnZOS+v1up zp3jH6hoCQeH+yTgL3k7DImEWmx1bNm3r4Eq1qTIimutZlkQqcZBo/kCABZSBvtpWGPD CoduPFYpY1YDj0iq/c8qegO8esChP3ScgZFlzSIoNtMiuqWog+pNLu6Lqqp+obmHzPxX 3IdQ== X-Gm-Message-State: AOAM5325BpTkIAORvdn5VSOeLFYOzu6MSyWYK6AbcxnpSo4Esiy5wYx3 saQjzAKCDftsmyE9FzQJUTU3 X-Google-Smtp-Source: ABdhPJxilUwLasF6c4NRwnyi8wdmFSt+i8aQBYX5gMYzf2RBhd6yIJabVZTugkZ1Y+a9XYWfSOmiMA== X-Received: by 2002:a17:902:b189:b0:14d:6f87:7c25 with SMTP id s9-20020a170902b18900b0014d6f877c25mr10896202plr.31.1646635547979; Sun, 06 Mar 2022 22:45:47 -0800 (PST) Received: from localhost.localdomain ([117.207.25.157]) by smtp.gmail.com with ESMTPSA id s7-20020a056a00178700b004e1a15e7928sm15841940pfg.145.2022.03.06.22.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Mar 2022 22:45:47 -0800 (PST) From: Manivannan Sadhasivam To: rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, angelogioacchino.delregno@somainline.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH 1/2] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings Date: Mon, 7 Mar 2022 12:15:30 +0530 Message-Id: <20220307064531.47678-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307064531.47678-1-manivannan.sadhasivam@linaro.org> References: <20220307064531.47678-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert Qualcomm cpufreq devicetree binding to YAML. Signed-off-by: Manivannan Sadhasivam Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 201 ++++++++++++++++++ 2 files changed, 201 insertions(+), 172 deletions(-) delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-= hw.txt create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-= hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt = b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt deleted file mode 100644 index 9299028ee712..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ /dev/null @@ -1,172 +0,0 @@ -Qualcomm Technologies, Inc. CPUFREQ Bindings - -CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (= QTI) -SoCs to manage frequency in hardware. It is capable of controlling frequen= cy -for multiple clusters. - -Properties: -- compatible - Usage: required - Value type: - Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". - -- clocks - Usage: required - Value type: From common clock binding. - Definition: clock handle for XO clock and GPLL0 clock. - -- clock-names - Usage: required - Value type: From common clock binding. - Definition: must be "xo", "alternate". - -- reg - Usage: required - Value type: - Definition: Addresses and sizes for the memory of the HW bases in - each frequency domain. -- reg-names - Usage: Optional - Value type: - Definition: Frequency domain name i.e. - "freq-domain0", "freq-domain1". - -- #freq-domain-cells: - Usage: required. - Definition: Number of cells in a freqency domain specifier. - -* Property qcom,freq-domain -Devices supporting freq-domain must set their "qcom,freq-domain" property = with -phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. - - -Example: - -Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster swit= ch -DCVS state together. - -/ { - cpus { - #address-cells =3D <2>; - #size-cells =3D <0>; - - CPU0: cpu@0 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x0>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - L3_0: l3-cache { - compatible =3D "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x100>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_100>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x200>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_200>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x300>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_300>; - qcom,freq-domain =3D <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x400>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_400>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_400: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x500>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_500>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_500: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x600>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_600>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type =3D "cpu"; - compatible =3D "qcom,kryo385"; - reg =3D <0x0 0x700>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_700>; - qcom,freq-domain =3D <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible =3D "cache"; - next-level-cache =3D <&L3_0>; - }; - }; - }; - - soc { - cpufreq_hw: cpufreq@17d43000 { - compatible =3D "qcom,cpufreq-hw"; - reg =3D <0x17d43000 0x1400>, <0x17d45800 0x1400>; - reg-names =3D "freq-domain0", "freq-domain1"; - - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - - #freq-domain-cells =3D <1>; - }; -} diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml new file mode 100644 index 000000000000..2f1b8b6852a0 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Manivannan Sadhasivam + +description: | + + CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc.= (QTI) + SoCs to manage frequency in hardware. It is capable of controlling frequ= ency + for multiple clusters. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw + + - description: v2 of CPUFREQ HW (EPSS) + items: + - enum: + - qcom,sm8250-cpufreq-epss + - const: qcom,cpufreq-epss + + reg: + minItems: 2 + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + - description: Frequency domain 2 register region + + reg-names: + minItems: 2 + items: + - const: freq-domain0 + - const: freq-domain1 + - const: freq-domain2 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + '#freq-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#freq-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a clust= er + // switch DCVS state together. + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_100>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_200>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_300>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_400>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_400: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_500>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_500: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_600>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_600: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo385"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_700>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + L2_700: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + }; + + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpufreq@17d43000 { + compatible =3D "qcom,cpufreq-hw"; + reg =3D <0x17d43000 0x1400>, <0x17d45800 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + }; + }; +... --=20 2.25.1 From nobody Tue Jun 23 11:16:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E8E5C433EF for ; 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Sun, 06 Mar 2022 22:45:52 -0800 (PST) From: Manivannan Sadhasivam To: rafael@kernel.org, viresh.kumar@linaro.org, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, angelogioacchino.delregno@somainline.org, Manivannan Sadhasivam , Hector Yuan , Sudeep Holla Subject: [PATCH 2/2] dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example Date: Mon, 7 Mar 2022 12:15:31 +0530 Message-Id: <20220307064531.47678-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307064531.47678-1-manivannan.sadhasivam@linaro.org> References: <20220307064531.47678-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom CPUFREQ HW don't have the support for generic performance domains yet. So use MediaTek CPUFREQ HW that has the support available in mainline. This also silences the below dtschema warnings for "cpufreq-qcom-hw.yaml": Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: reg: [[305397760, 4096]] is too short From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: 'clocks' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: 'clock-names' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: '#freq-domain-cells' is a required property From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Documentation/devicetree/bindings/dvfs/performance-domain.example.dt.yaml: = performance-controller@12340000: '#performance-domain-cells' does not match= any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/cpufreq/cpufreq-qcom= -hw.yaml Cc: Hector Yuan Cc: Sudeep Holla Signed-off-by: Manivannan Sadhasivam --- .../bindings/dvfs/performance-domain.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml= b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml index c8b91207f34d..9e0bcf1a89fe 100644 --- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -52,10 +52,16 @@ additionalProperties: true =20 examples: - | - performance: performance-controller@12340000 { - compatible =3D "qcom,cpufreq-hw"; - reg =3D <0x12340000 0x1000>; - #performance-domain-cells =3D <1>; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + performance: performance-controller@11bc00 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + + #performance-domain-cells =3D <1>; + }; }; =20 // The node above defines a performance controller that is a performan= ce --=20 2.25.1