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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id g6-20020a5d5406000000b001f049726044sm4937307wrv.79.2022.03.04.08.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Mar 2022 08:15:32 -0800 (PST) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.or Cc: matthias.bgg@gmail.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, khilman@baylibre.com, Alexandre Bailon Subject: [PATCH v4 7/7] ARM64: mt8183: Add support of APU to mt8183 Date: Fri, 4 Mar 2022 17:15:14 +0100 Message-Id: <20220304161514.994128-8-abailon@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220304161514.994128-1-abailon@baylibre.com> References: <20220304161514.994128-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the support of APU to mt8183. Signed-off-by: Alexandre Bailon --- .../boot/dts/mediatek/mt8183-pumpkin.dts | 50 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 40 +++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/b= oot/dts/mediatek/mt8183-pumpkin.dts index ee912825cfc6..155c89c998d3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -37,6 +37,42 @@ scp_mem_reserved: scp_mem_region@50000000 { reg =3D <0 0x50000000 0 0x2900000>; no-map; }; + + vdev0buffer: vdev0buffer@52900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x52900000 0 0x4000>; + no-map; + }; + + vdev0vring0: vdev0vring0@52904000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x52904000 0 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@52906000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x52906000 0 0x2000>; + no-map; + }; + + vdev1buffer: vdev1buffer@52908000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x52908000 0 0x4000>; + no-map; + }; + + vdev1vring0: vdev1vring0@5290C000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x5290C000 0 0x2000>; + no-map; + }; + + vdev1vring1: vdev1vring1@5290E000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x5290E000 0 0x2000>; + no-map; + }; }; =20 leds { @@ -381,3 +417,17 @@ &scp { &dsi0 { status =3D "disabled"; }; + +&apu0 { + memory-region =3D <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>; + memory-region-names =3D "vdev0buffer", "vdev0vring0", "vdev0vring1"; + memory-region-da =3D <0x6fff8000>, <0x6fffc000>, <0x6fffe000>; + status =3D "okay"; +}; + +&apu1 { + memory-region =3D <&vdev1buffer>, <&vdev1vring0>, <&vdev1vring1>; + memory-region-names =3D "vdev1buffer", "vdev1vring0", "vdev1vring1"; + memory-region-da =3D <0x6fff0000>, <0x6fff4000>, <0x6fff6000>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index ba4584faca5a..cb02f57e000d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1542,12 +1542,52 @@ ipu_adl: syscon@19010000 { #clock-cells =3D <1>; }; =20 + apu0: apu@0x19100000 { + compatible =3D "mediatek,mt8183-apu"; + reg =3D <0 0x19180000 0 0x14000>; + interrupts =3D ; + + iommus =3D <&iommu M4U_PORT_IMG_IPUO>, + <&iommu M4U_PORT_IMG_IPU3O>, + <&iommu M4U_PORT_IMG_IPUI>; + + clocks =3D <&ipu_core0 CLK_IPU_CORE0_AXI>, + <&ipu_core0 CLK_IPU_CORE0_IPU>, + <&ipu_core0 CLK_IPU_CORE0_JTAG>; + + clock-names =3D "axi", "ipu", "jtag"; + + power-domains =3D <&spm MT8183_POWER_DOMAIN_VPU_CORE0>; + + status =3D "disabled"; + }; + ipu_core0: syscon@19180000 { compatible =3D "mediatek,mt8183-ipu_core0", "syscon"; reg =3D <0 0x19180000 0 0x1000>; #clock-cells =3D <1>; }; =20 + apu1: apu@19200000 { + compatible =3D "mediatek,mt8183-apu"; + reg =3D <0 0x19280000 0 0x14000>; + interrupts =3D ; + + iommus =3D <&iommu M4U_PORT_CAM_IPUO>, + <&iommu M4U_PORT_CAM_IPU2O>, + <&iommu M4U_PORT_CAM_IPU3O>; + + clocks =3D <&ipu_core0 CLK_IPU_CORE1_AXI>, + <&ipu_core0 CLK_IPU_CORE1_IPU>, + <&ipu_core0 CLK_IPU_CORE1_JTAG>; + + clock-names =3D "axi", "ipu", "jtag"; + + power-domains =3D <&spm MT8183_POWER_DOMAIN_VPU_CORE1>; + + status =3D "disabled"; + }; + ipu_core1: syscon@19280000 { compatible =3D "mediatek,mt8183-ipu_core1", "syscon"; reg =3D <0 0x19280000 0 0x1000>; --=20 2.34.1