From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB41FC433F5 for ; Fri, 4 Mar 2022 13:35:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237132AbiCDNfw (ORCPT ); Fri, 4 Mar 2022 08:35:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231596AbiCDNfo (ORCPT ); Fri, 4 Mar 2022 08:35:44 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79D8F1B7627 for ; Fri, 4 Mar 2022 05:34:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646400896; x=1677936896; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yt27LNUTflYgzhTyHkUhcmzYyrzGjKVHAKDiaE7aibE=; b=BlKb9utF2Noz9+2D4IZrgnpAHbQOcbtMn245SS3i5jAmRMRaMJAPCf4n 8IH3N5B4ZyLYsNWL9cv7e7z4S3V3y8jWfuyWEHUcIYSNJMY1dLIZFwKPB 7RlvYPjlRMX9MHNbYbSSZoUeGnJY4qcrwkxCnpMfLv4BVmCVuk/k2Ieya jtH/nQkxbV5jEz3yU9EAhhnP3hIhf8tQfQiiKN/O2+ujfotS+BJ61YLRL 9+pZH3ST09/ZwTNAkiQVmqsPvWS8uIv8RBlw1IGAnhuSlUn59J2dvtzIo HB4zwYxbiXy1Xh0DcUfJ+N6HYyl3TKODDCVlNoegJEk7cM9wlrz8JW2Xh g==; X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="148098670" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:34:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:34:54 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:53 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 1/6] clocksource/drivers/timer-microchip-pit64b: remove mmio selection Date: Fri, 4 Mar 2022 15:35:56 +0200 Message-ID: <20220304133601.2404086-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PIT64B timer driver doesn't depend on CLKSRC_MMIO since commit e85c1d21b16b ("clocksource/drivers/timer-microchip-pit64b: Add clocksource suspend/resume"). Remove the selection. Signed-off-by: Claudiu Beznea --- drivers/clocksource/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cfb8ea0df3b1..1ea556e75494 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -713,7 +713,6 @@ config INGENIC_OST config MICROCHIP_PIT64B bool "Microchip PIT64B support" depends on OF || COMPILE_TEST - select CLKSRC_MMIO select TIMER_OF help This option enables Microchip PIT64B timer for Atmel --=20 2.32.0 From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A51CC433F5 for ; Fri, 4 Mar 2022 13:35:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238580AbiCDNfy (ORCPT ); Fri, 4 Mar 2022 08:35:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236713AbiCDNfp (ORCPT ); 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04 Mar 2022 06:34:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:34:56 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:55 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 2/6] clocksource/drivers/timer-microchip-pit64b: use notrace Date: Fri, 4 Mar 2022 15:35:57 +0200 Message-ID: <20220304133601.2404086-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use notrace for mchp_pit64b_sched_read_clk() to avoid recursive call of prepare_ftrace_return() when issuing: echo function_graph > /sys/kernel/debug/tracing/current_tracer Fixes: 625022a5f160 ("clocksource/drivers/timer-microchip-pit64b: Add Micro= chip PIT64B support") Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index cfa4ec7ef396..790d2c9b42a7 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -165,7 +165,7 @@ static u64 mchp_pit64b_clksrc_read(struct clocksource *= cs) return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); } =20 -static u64 mchp_pit64b_sched_read_clk(void) +static u64 notrace mchp_pit64b_sched_read_clk(void) { return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); } --=20 2.32.0 From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EC7EC433EF for ; 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X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="148098685" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:34:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:34:58 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:56 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 3/6] clocksource/drivers/timer-microchip-pit64b: use 5MHz for clockevent Date: Fri, 4 Mar 2022 15:35:58 +0200 Message-ID: <20220304133601.2404086-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use 5MHz clock for clockevent timers. This increases timer's resolution. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index 790d2c9b42a7..abce83d2f00b 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -42,8 +42,7 @@ #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) -#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */ -#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */ +#define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */ =20 #define MCHP_PIT64B_NAME "pit64b" =20 @@ -418,7 +417,6 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_p= it64b_timer *timer, static int __init mchp_pit64b_dt_init_timer(struct device_node *node, bool clkevt) { - u32 freq =3D clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ; struct mchp_pit64b_timer timer; unsigned long clk_rate; u32 irq =3D 0; @@ -446,7 +444,7 @@ static int __init mchp_pit64b_dt_init_timer(struct devi= ce_node *node, } =20 /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ - ret =3D mchp_pit64b_init_mode(&timer, freq); + ret =3D mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ); if (ret) goto irq_unmap; =20 --=20 2.32.0 From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7942AC433F5 for ; Fri, 4 Mar 2022 13:35:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239034AbiCDNgA (ORCPT ); Fri, 4 Mar 2022 08:36:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238413AbiCDNft (ORCPT ); Fri, 4 Mar 2022 08:35:49 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F6B01B7627 for ; Fri, 4 Mar 2022 05:35:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646400901; x=1677936901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CGECGO3DLDF9kAjkJpmPmmKockfvvVD5RT0cNRq2/PE=; b=Y0USkb2ZBl0vrjI2e8UInGT1IBXaeVI9ALniq3ArF8YcVA8LupJ/UlX9 r5LHgokNy43cb1HnVqHfWIWVPUPAAANl53mh1RQilxAw+iXaJwfIFEdOG 6BQXTm9yD70p51hv4dRId3HUwQAJzRHIFGpVeoJN7omuOsU65v/ukfQ+M fLKv4U9ySuG3l0qm5OKHTrOVqlm13WHhaDunwayWoxFalpw9k9Me6M9D3 46KGJ8zCAb5zNNTyysYczpxuwo8+6pOITBZqqcCSvq13wGxdLWfhVaBw/ EVlw1yd/h/k8jNmEoPk29SqdT84g8HjwKC2CKocY9gc5o+XFzL/iT+2UW w==; X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="87833826" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:35:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:35:00 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:34:58 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 4/6] clocksource/drivers/timer-microchip-pit64b: remove suspend/resume ops for ce Date: Fri, 4 Mar 2022 15:35:59 +0200 Message-ID: <20220304133601.2404086-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index abce83d2f00b..b51259395ac3 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -173,7 +173,8 @@ static int mchp_pit64b_clkevt_shutdown(struct clock_eve= nt_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); + if (!clockevent_state_detached(cedev)) + mchp_pit64b_suspend(timer); =20 return 0; } @@ -182,35 +183,37 @@ static int mchp_pit64b_clkevt_set_periodic(struct clo= ck_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_suspend(timer); -} - -static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) -{ - struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); + mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + MCHP_PIT64B_IER_PERIOD); =20 - mchp_pit64b_resume(timer); + return 0; } =20 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) @@ -395,9 +398,8 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_p= it64b_timer *timer, ce->clkevt.rating =3D 150; ce->clkevt.set_state_shutdown =3D mchp_pit64b_clkevt_shutdown; ce->clkevt.set_state_periodic =3D mchp_pit64b_clkevt_set_periodic; + ce->clkevt.set_state_oneshot =3D mchp_pit64b_clkevt_set_oneshot; ce->clkevt.set_next_event =3D mchp_pit64b_clkevt_set_next_event; - ce->clkevt.suspend =3D mchp_pit64b_clkevt_suspend; - ce->clkevt.resume =3D mchp_pit64b_clkevt_resume; ce->clkevt.cpumask =3D cpumask_of(0); ce->clkevt.irq =3D irq; =20 --=20 2.32.0 From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 268D5C433FE for ; Fri, 4 Mar 2022 13:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238952AbiCDNgD (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="164541129" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:35:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:35:01 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:35:00 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 5/6] clocksource/drivers/timer-microchip-pit64b: use mchp_pit64b_{suspend, resume} Date: Fri, 4 Mar 2022 15:36:00 +0200 Message-ID: <20220304133601.2404086-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 24 ++++---------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index b51259395ac3..f50705698283 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -344,6 +344,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, if (!cs) return -ENOMEM; =20 + mchp_pit64b_resume(timer); mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); =20 mchp_pit64b_cs_base =3D timer->base; @@ -365,8 +366,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); =20 /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); + mchp_pit64b_suspend(timer); kfree(cs); =20 return ret; @@ -450,19 +450,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, if (ret) goto irq_unmap; =20 - ret =3D clk_prepare_enable(timer.pclk); - if (ret) - goto irq_unmap; - - if (timer.mode & MCHP_PIT64B_MR_SGCLK) { - ret =3D clk_prepare_enable(timer.gclk); - if (ret) - goto pclk_unprepare; - + if (timer.mode & MCHP_PIT64B_MR_SGCLK) clk_rate =3D clk_get_rate(timer.gclk); - } else { + else clk_rate =3D clk_get_rate(timer.pclk); - } clk_rate =3D clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); =20 if (clkevt) @@ -471,15 +462,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, ret =3D mchp_pit64b_init_clksrc(&timer, clk_rate); =20 if (ret) - goto gclk_unprepare; + goto irq_unmap; =20 return 0; =20 -gclk_unprepare: - if (timer.mode & MCHP_PIT64B_MR_SGCLK) - clk_disable_unprepare(timer.gclk); -pclk_unprepare: - clk_disable_unprepare(timer.pclk); irq_unmap: irq_dispose_mapping(irq); io_unmap: --=20 2.32.0 From nobody Tue Jun 23 13:10:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF4C0C433F5 for ; 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X-IronPort-AV: E=Sophos;i="5.90,155,1643698800"; d="scan'208";a="87833845" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Mar 2022 06:35:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 4 Mar 2022 06:35:03 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 4 Mar 2022 06:35:02 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH v3 6/6] clocksource/drivers/timer-microchip-pit64b: fix compilation warnings Date: Fri, 4 Mar 2022 15:36:01 +0200 Message-ID: <20220304133601.2404086-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220304133601.2404086-1-claudiu.beznea@microchip.com> References: <20220304133601.2404086-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following compilation warnings: timer-microchip-pit64b.c:68: warning: cannot understand function prototype:= 'struct mchp_pit64b_clkevt ' timer-microchip-pit64b.c:82: warning: cannot understand function prototype:= 'struct mchp_pit64b_clksrc ' timer-microchip-pit64b.c:283: warning: Function parameter or member 'timer'= not described in 'mchp_pit64b_init_mode' timer-microchip-pit64b.c:283: warning: Function parameter or member 'max_ra= te' not described in 'mchp_pit64b_init_mode' Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index f50705698283..d5f1436f33d9 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -61,7 +61,7 @@ struct mchp_pit64b_timer { }; =20 /** - * mchp_pit64b_clkevt - PIT64B clockevent data structure + * struct mchp_pit64b_clkevt - PIT64B clockevent data structure * @timer: PIT64B timer * @clkevt: clockevent */ @@ -75,7 +75,7 @@ struct mchp_pit64b_clkevt { struct mchp_pit64b_clkevt, clkevt)) =20 /** - * mchp_pit64b_clksrc - PIT64B clocksource data structure + * struct mchp_pit64b_clksrc - PIT64B clocksource data structure * @timer: PIT64B timer * @clksrc: clocksource */ @@ -245,8 +245,10 @@ static void __init mchp_pit64b_pres_compute(u32 *pres,= u32 clk_rate, } =20 /** - * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at - * runtime; this includes prescaler and SGCLK bit + * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used= at + * runtime; this includes prescaler and SGCLK bit + * @timer: pointer to pit64b timer to init + * @max_rate: maximum rate that timer's clock could use * * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has= to * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk ra= te --=20 2.32.0