From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B40C433F5 for ; Fri, 4 Mar 2022 13:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237618AbiCDNJ0 (ORCPT ); Fri, 4 Mar 2022 08:09:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236240AbiCDNJM (ORCPT ); Fri, 4 Mar 2022 08:09:12 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB5DC5EDE6; Fri, 4 Mar 2022 05:08:20 -0800 (PST) X-UUID: 5afedb7958194c65808cde9cf970ecfd-20220304 X-UUID: 5afedb7958194c65808cde9cf970ecfd-20220304 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 445547100; Fri, 04 Mar 2022 21:08:14 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:13 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 01/21] arm64: dts: mt8192: Add pwrap node Date: Fri, 4 Mar 2022 21:07:49 +0800 Message-ID: <20220304130809.12924-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 411feb294613..76428599444e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names =3D "clk13m"; }; =20 + pwrap: pwrap@10026000 { + compatible =3D "mediatek,mt6873-pwrap"; + reg =3D <0 0x10026000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names =3D "spi", "wrap"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F326C4332F for ; Fri, 4 Mar 2022 13:08:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236712AbiCDNJQ (ORCPT ); Fri, 4 Mar 2022 08:09:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236156AbiCDNJL (ORCPT ); Fri, 4 Mar 2022 08:09:11 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 236025EBE0; Fri, 4 Mar 2022 05:08:19 -0800 (PST) X-UUID: 4326699cc3454f37a5803bf0512dae02-20220304 X-UUID: 4326699cc3454f37a5803bf0512dae02-20220304 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 869231909; Fri, 04 Mar 2022 21:08:15 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 4 Mar 2022 21:08:14 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:14 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 02/21] arm64: dts: mt8192: Add spmi node Date: Fri, 4 Mar 2022 21:07:50 +0800 Message-ID: <20220304130809.12924-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add spmi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 76428599444e..0f9f211ca986 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -535,6 +535,23 @@ assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; }; =20 + spmi: spmi@10027000 { + compatible =3D "mediatek,mt6873-spmi"; + reg =3D <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names =3D "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks =3D <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_OSC_D10>; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04E82C4332F for ; Fri, 4 Mar 2022 13:08:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237132AbiCDNJV (ORCPT ); Fri, 4 Mar 2022 08:09:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235212AbiCDNJM (ORCPT ); Fri, 4 Mar 2022 08:09:12 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B765660ABC; Fri, 4 Mar 2022 05:08:22 -0800 (PST) X-UUID: 94f73cf443b947fcbaecf1d9f3fec53a-20220304 X-UUID: 94f73cf443b947fcbaecf1d9f3fec53a-20220304 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1345187692; Fri, 04 Mar 2022 21:08:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:15 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 03/21] arm64: dts: mt8192: Add gce node Date: Fri, 4 Mar 2022 21:07:51 +0800 Message-ID: <20220304130809.12924-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add gce node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 0f9f211ca986..9e1b563bebab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; #include +#include #include #include #include @@ -552,6 +553,15 @@ #size-cells =3D <0>; }; =20 + gce: mailbox@10228000 { + compatible =3D "mediatek,mt8192-gce"; + reg =3D <0 0x10228000 0 0x4000>; + interrupts =3D ; + #mbox-cells =3D <3>; + clocks =3D <&infracfg CLK_INFRA_GCE>; + clock-names =3D "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA89C433F5 for ; Fri, 4 Mar 2022 13:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237010AbiCDNJa (ORCPT ); Fri, 4 Mar 2022 08:09:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236299AbiCDNJM (ORCPT ); Fri, 4 Mar 2022 08:09:12 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B5F365802; Fri, 4 Mar 2022 05:08:21 -0800 (PST) X-UUID: 049f972cca0248a397894656129695c4-20220304 X-UUID: 049f972cca0248a397894656129695c4-20220304 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1671238394; Fri, 04 Mar 2022 21:08:17 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:15 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 04/21] arm64: dts: mt8192: Add SCP node Date: Fri, 4 Mar 2022 21:07:52 +0800 Message-ID: <20220304130809.12924-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 9e1b563bebab..195d50894df4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -706,6 +706,18 @@ status =3D "disabled"; }; =20 + scp: scp@10500000 { + compatible =3D "mediatek,mt8192-scp"; + reg =3D <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names =3D "sram", "l1tcm", "cfg"; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_SCPSYS>; + clock-names =3D "main"; + status =3D "disabled"; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2AFDC433EF for ; Fri, 4 Mar 2022 13:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238982AbiCDNKM (ORCPT ); Fri, 4 Mar 2022 08:10:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236571AbiCDNJP (ORCPT ); Fri, 4 Mar 2022 08:09:15 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A692289AA; Fri, 4 Mar 2022 05:08:22 -0800 (PST) X-UUID: a5baf1e29c8947e489da30c2439f2fb3-20220304 X-UUID: a5baf1e29c8947e489da30c2439f2fb3-20220304 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1085374712; Fri, 04 Mar 2022 21:08:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 4 Mar 2022 21:08:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:16 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 05/21] arm64: dts: mt8192: Add usb-phy node Date: Fri, 4 Mar 2022 21:07:53 +0800 Message-ID: <20220304130809.12924-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 195d50894df4..28b93b76fe17 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -875,6 +875,28 @@ #clock-cells =3D <1>; }; =20 + u3phy0: t-phy@11e40000 { + compatible =3D "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11e40000 0x1000>; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + + u3port0: usb-phy@700 { + reg =3D <0x700 0x900>; + clocks =3D <&clk26m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C252CC433EF for ; Fri, 4 Mar 2022 13:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239248AbiCDNJu (ORCPT ); Fri, 4 Mar 2022 08:09:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbiCDNJN (ORCPT ); Fri, 4 Mar 2022 08:09:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37A9D6D1BB; Fri, 4 Mar 2022 05:08:25 -0800 (PST) X-UUID: 51db633fc7474f3283e31b5eb2a1ce97-20220304 X-UUID: 51db633fc7474f3283e31b5eb2a1ce97-20220304 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1520759150; Fri, 04 Mar 2022 21:08:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:17 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 06/21] arm64: dts: mt8192: Add xhci node Date: Fri, 4 Mar 2022 21:07:54 +0800 Message-ID: <20220304130809.12924-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 28b93b76fe17..6bc36a4076f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include =20 / { @@ -718,6 +719,29 @@ status =3D "disabled"; }; =20 + xhci: usb@11200000 { + compatible =3D "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts-extended =3D <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "host"; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names =3D "sys_ck", "xhci_ck", "ref_ck"; + wakeup-source; + mediatek,syscon-wakeup =3D <&pericfg 0x420 102>; + status =3D "disabled"; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48E4C433F5 for ; Fri, 4 Mar 2022 13:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238503AbiCDNJn (ORCPT ); Fri, 4 Mar 2022 08:09:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236361AbiCDNJN (ORCPT ); Fri, 4 Mar 2022 08:09:13 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 823885EBE0; Fri, 4 Mar 2022 05:08:25 -0800 (PST) X-UUID: bcc7b0641d8346f5bc20d4450f339d88-20220304 X-UUID: bcc7b0641d8346f5bc20d4450f339d88-20220304 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 799099668; Fri, 04 Mar 2022 21:08:20 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:18 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 07/21] arm64: dts: mt8192: Add audio-related nodes Date: Fri, 4 Mar 2022 21:07:55 +0800 Message-ID: <20220304130809.12924-8-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add audio-related nodes in audsys for mt8192 SoC. - Move audsys node in ascending order. - Increase the address range's length from 0x1000 to 0x2000. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++- 1 file changed, 128 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 6bc36a4076f4..40cf6dacca3e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -742,6 +742,134 @@ status =3D "disabled"; }; =20 + audsys: syscon@11210000 { + compatible =3D "mediatek,mt8192-audsys", "syscon"; + reg =3D <0 0x11210000 0 0x2000>; + #clock-cells =3D <1>; + afe: mt8192-afe-pcm { + compatible =3D "mediatek,mt8192-audio"; + interrupts =3D ; + resets =3D <&watchdog 17>; + reset-names =3D "audiosys"; + mediatek,apmixedsys =3D <&apmixedsys>; + mediatek,infracfg =3D <&infracfg>; + mediatek,topckgen =3D <&topckgen>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_AUDIO>; + clocks =3D <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_22M>, + <&audsys CLK_AUD_24M>, + <&audsys CLK_AUD_APLL_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TDM>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_NLE>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES_TML>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_3RD_DAC>, + <&audsys CLK_AUD_3RD_DAC_PREDIS>, + <&audsys CLK_AUD_3RD_DAC_TML>, + <&audsys CLK_AUD_3RD_DAC_HIRES>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&topckgen CLK_TOP_APLL12_DIV5>, + <&topckgen CLK_TOP_APLL12_DIV6>, + <&topckgen CLK_TOP_APLL12_DIV7>, + <&topckgen CLK_TOP_APLL12_DIV8>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&clk26m>; + clock-names =3D "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adda6_adc_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_tdm_clk", + "aud_tml_clk", + "aud_nle", + "aud_dac_hires_clk", + "aud_adc_hires_clk", + "aud_adc_hires_tml", + "aud_adda6_adc_hires_clk", + "aud_3rd_dac_clk", + "aud_3rd_dac_predis_clk", + "aud_3rd_dac_tml", + "aud_3rd_dac_hires_clk", + "aud_infra_clk", + "aud_infra_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d4_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d4", + "top_mux_aud_eng2", + "top_apll2_d4", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_i2s6_m_sel", + "top_i2s7_m_sel", + "top_i2s8_m_sel", + "top_i2s9_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_apll12_div5", + "top_apll12_div6", + "top_apll12_div7", + "top_apll12_div8", + "top_apll12_div9", + "top_mux_audio_h", + "top_clk26m_clk"; + }; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; @@ -757,12 +885,6 @@ status =3D "disable"; }; =20 - audsys: clock-controller@11210000 { - compatible =3D "mediatek,mt8192-audsys", "syscon"; - reg =3D <0 0x11210000 0 0x1000>; - #clock-cells =3D <1>; - }; - i2c3: i2c@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DDFBC433EF for ; Fri, 4 Mar 2022 13:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238096AbiCDNJk (ORCPT ); Fri, 4 Mar 2022 08:09:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236371AbiCDNJN (ORCPT ); Fri, 4 Mar 2022 08:09:13 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B59646D393; Fri, 4 Mar 2022 05:08:25 -0800 (PST) X-UUID: a030dbcb76764b93ba923df41b4a9524-20220304 X-UUID: a030dbcb76764b93ba923df41b4a9524-20220304 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 104143303; Fri, 04 Mar 2022 21:08:21 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 4 Mar 2022 21:08:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:19 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 08/21] arm64: dts: mt8192: Add infracfg_rst node Date: Fri, 4 Mar 2022 21:07:56 +0800 Message-ID: <20220304130809.12924-9-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add infracfg_rst node for mt8192 SoC. - Add simple-mfd to allow probing the ti,syscon-reset node. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 40cf6dacca3e..82de1af3f6aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -267,10 +268,23 @@ #clock-cells =3D <1>; }; =20 - infracfg: syscon@10001000 { - compatible =3D "mediatek,mt8192-infracfg", "syscon"; + infracfg: infracfg@10001000 { + compatible =3D "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; + + infracfg_rst: reset-controller { + compatible =3D "ti,syscon-reset"; + #reset-cells =3D <1>; + + ti,reset-bits =3D < + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: l= vts_ap */ + 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1:= lvts_mcu */ + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2:= pcie phy */ + 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: p= cie top */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: s= vs */ + >; + }; }; =20 pericfg: syscon@10003000 { --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE7CC433F5 for ; Fri, 4 Mar 2022 13:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232991AbiCDNKI (ORCPT ); Fri, 4 Mar 2022 08:10:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236777AbiCDNJQ (ORCPT ); Fri, 4 Mar 2022 08:09:16 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 195776D868; Fri, 4 Mar 2022 05:08:27 -0800 (PST) X-UUID: 59710d584cd640fcb882bd5fd89c8dae-20220304 X-UUID: 59710d584cd640fcb882bd5fd89c8dae-20220304 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 700838028; Fri, 04 Mar 2022 21:08:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:20 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:20 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 09/21] arm64: dts: mt8192: Add PCIe node Date: Fri, 4 Mar 2022 21:07:57 +0800 Message-ID: <20220304130809.12924-10-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 82de1af3f6aa..3a7f93d8eeaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -884,6 +884,44 @@ }; }; =20 + pcie: pcie@11230000 { + compatible =3D "mediatek,mt8192-pcie"; + device_type =3D "pci"; + reg =3D <0 0x11230000 0 0x2000>; + reg-names =3D "pcie-mac"; + #address-cells =3D <3>; + #size-cells =3D <2>; + clocks =3D <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>, + <&infracfg CLK_INFRA_PCIE_PL_P_250M>; + clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", + "obff_ck0", "axi_ck0", "pipe_ck0"; + assigned-clocks =3D <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D6_D4>; + resets =3D <&infracfg_rst 2>, + <&infracfg_rst 3>; + reset-names =3D "phy", "mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + nor_flash: spi@11234000 { compatible =3D "mediatek,mt8192-nor"; reg =3D <0 0x11234000 0 0xe0>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1638C433EF for ; Fri, 4 Mar 2022 13:09:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239478AbiCDNKB (ORCPT ); Fri, 4 Mar 2022 08:10:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236778AbiCDNJQ (ORCPT ); Fri, 4 Mar 2022 08:09:16 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B62CD5EDE6; Fri, 4 Mar 2022 05:08:28 -0800 (PST) X-UUID: a2896a1989c249b9a08047537ba5956c-20220304 X-UUID: a2896a1989c249b9a08047537ba5956c-20220304 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 455563723; Fri, 04 Mar 2022 21:08:23 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:21 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:21 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 10/21] arm64: dts: mt8192: Fix nor_flash status disable typo Date: Fri, 4 Mar 2022 21:07:58 +0800 Message-ID: <20220304130809.12924-11-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Correct nor_flash status disable typo of mt8192 SoC. Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 3a7f93d8eeaa..75c21edccf85 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -934,7 +934,7 @@ assigned-clock-parents =3D <&clk26m>; #address-cells =3D <1>; #size-cells =3D <0>; - status =3D "disable"; + status =3D "disabled"; }; =20 i2c3: i2c@11cb0000 { --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D55C433F5 for ; Fri, 4 Mar 2022 13:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238638AbiCDNJy (ORCPT ); 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Fri, 4 Mar 2022 21:08:22 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 11/21] arm64: dts: mt8192: Add efuse node Date: Fri, 4 Mar 2022 21:07:59 +0800 Message-ID: <20220304130809.12924-12-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add efuse node for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 75c21edccf85..6220d6962f58 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -937,6 +937,21 @@ status =3D "disabled"; }; =20 + efuse: efuse@11c10000 { + compatible =3D "mediatek,efuse"; + reg =3D <0 0x11c10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_e_data1: data1@1c0 { + reg =3D <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg =3D <0x580 0x68>; + }; + }; + i2c3: i2c@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96118C433EF for ; Fri, 4 Mar 2022 13:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239772AbiCDNKl (ORCPT ); Fri, 4 Mar 2022 08:10:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236945AbiCDNJU (ORCPT ); Fri, 4 Mar 2022 08:09:20 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ACA9289AA; Fri, 4 Mar 2022 05:08:30 -0800 (PST) X-UUID: 33f478a9507c41f4ad4cab90fb3c3f2b-20220304 X-UUID: 33f478a9507c41f4ad4cab90fb3c3f2b-20220304 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1864907984; Fri, 04 Mar 2022 21:08:25 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:24 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:23 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 12/21] arm64: dts: mt8192: Add mmc device nodes Date: Fri, 4 Mar 2022 21:08:00 +0800 Message-ID: <20220304130809.12924-13-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mmc nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 6220d6962f58..4e4081ea7db5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1150,10 +1150,36 @@ #clock-cells =3D <1>; }; =20 - msdc: clock-controller@11f60000 { - compatible =3D "mediatek,mt8192-msdc"; - reg =3D <0 0x11f60000 0 0x1000>; - #clock-cells =3D <1>; + mmc0: mmc@11f60000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status =3D "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible =3D "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>; + clock-names =3D "source", "hclk", "source_cg", "sys_cg", + "axi_cg", "ahb_cg", "pclk_cg"; + status =3D "disabled"; }; =20 mfgcfg: clock-controller@13fbf000 { --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F6DBC433FE for ; Fri, 4 Mar 2022 13:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239107AbiCDNJ6 (ORCPT ); Fri, 4 Mar 2022 08:09:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236961AbiCDNJR (ORCPT ); Fri, 4 Mar 2022 08:09:17 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 880056D952; Fri, 4 Mar 2022 05:08:29 -0800 (PST) X-UUID: ef0dc1374c6349fbb22c95d99db9f0b5-20220304 X-UUID: ef0dc1374c6349fbb22c95d99db9f0b5-20220304 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1640516081; Fri, 04 Mar 2022 21:08:25 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:24 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 13/21] arm64: dts: mt8192: Add mipi_tx node Date: Fri, 4 Mar 2022 21:08:01 +0800 Message-ID: <20220304130809.12924-14-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 4e4081ea7db5..b9e51a9dda08 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1110,6 +1110,16 @@ }; }; =20 + mipi_tx0: dsi-dphy@11e50000 { + compatible =3D "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11e50000 0 0x1000>; + clocks =3D <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + clock-output-names =3D "mipi_tx0_pll"; + status =3D "disabled"; + }; + i2c0: i2c@11f00000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11f00000 0 0x1000>, --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA2FBC433F5 for ; Fri, 4 Mar 2022 13:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239716AbiCDNK1 (ORCPT ); Fri, 4 Mar 2022 08:10:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237327AbiCDNJV (ORCPT ); Fri, 4 Mar 2022 08:09:21 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B758665802; Fri, 4 Mar 2022 05:08:31 -0800 (PST) X-UUID: 0930fa9ef5294fb58179998de99bf944-20220304 X-UUID: 0930fa9ef5294fb58179998de99bf944-20220304 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 880956830; Fri, 04 Mar 2022 21:08:27 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:25 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 14/21] arm64: dts: mt8192: Add m4u and smi nodes Date: Fri, 4 Mar 2022 21:08:02 +0800 Message-ID: <20220304130809.12924-15-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index b9e51a9dda08..1c804c925021 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -1204,24 +1205,114 @@ #clock-cells =3D <1>; }; =20 + smi_common: smi@14002000 { + compatible =3D "mediatek,mt8192-smi-common"; + reg =3D <0 0x14002000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names =3D "apb", "smi", "gals0", "gals1"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,larb-id =3D <0>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,larb-id =3D <1>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible =3D "mediatek,mt8192-m4u"; + reg =3D <0 0x1401d000 0 0x1000>; + mediatek,larbs =3D <&larb0>, <&larb1>, <&larb2>, + <&larb4>, <&larb5>, <&larb7>, + <&larb9>, <&larb11>, <&larb13>, + <&larb14>, <&larb16>, <&larb17>, + <&larb18>, <&larb19>, <&larb20>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_SMI_IOMMU>; + clock-names =3D "bclk"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells =3D <1>; + }; + imgsys: clock-controller@15020000 { compatible =3D "mediatek,mt8192-imgsys"; reg =3D <0 0x15020000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb9: larb@1502e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1502e000 0 0x1000>; + mediatek,larb-id =3D <9>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible =3D "mediatek,mt8192-imgsys2"; reg =3D <0 0x15820000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb11: larb@1582e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1582e000 0 0x1000>; + mediatek,larb-id =3D <11>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1600d000 0 0x1000>; + mediatek,larb-id =3D <5>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible =3D "mediatek,mt8192-vdecsys_soc"; reg =3D <0 0x1600f000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb4: larb@1602e000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1602e000 0 0x1000>; + mediatek,larb-id =3D <4>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible =3D "mediatek,mt8192-vdecsys"; reg =3D <0 0x1602f000 0 0x1000>; @@ -1234,12 +1325,78 @@ #clock-cells =3D <1>; }; =20 + larb7: larb@17010000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x17010000 0 0x1000>; + mediatek,larb-id =3D <7>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; }; =20 + larb13: larb@1a001000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a001000 0 0x1000>; + mediatek,larb-id =3D <13>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a002000 0 0x1000>; + mediatek,larb-id =3D <14>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a00f000 0 0x1000>; + mediatek,larb-id =3D <16>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a010000 0 0x1000>; + mediatek,larb-id =3D <17>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1a011000 0 0x1000>; + mediatek,larb-id =3D <18>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible =3D "mediatek,mt8192-camsys_rawa"; reg =3D <0 0x1a04f000 0 0x1000>; @@ -1264,10 +1421,43 @@ #clock-cells =3D <1>; }; =20 + larb20: larb@1b00f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1b00f000 0 0x1000>; + mediatek,larb-id =3D <20>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1b10f000 0 0x1000>; + mediatek,larb-id =3D <19>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible =3D "mediatek,mt8192-mdpsys"; reg =3D <0 0x1f000000 0 0x1000>; #clock-cells =3D <1>; }; + + larb2: larb@1f002000 { + compatible =3D "mediatek,mt8192-smi-larb"; + reg =3D <0 0x1f002000 0 0x1000>; + mediatek,larb-id =3D <2>; + mediatek,smi =3D <&smi_common>; + clocks =3D <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names =3D "apb", "smi"; + power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FF0FC433F5 for ; Fri, 4 Mar 2022 13:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239683AbiCDNKa (ORCPT ); Fri, 4 Mar 2022 08:10:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237834AbiCDNJX (ORCPT ); Fri, 4 Mar 2022 08:09:23 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 388D56D964; Fri, 4 Mar 2022 05:08:34 -0800 (PST) X-UUID: cd15fd70a60c404d971211b188407445-20220304 X-UUID: cd15fd70a60c404d971211b188407445-20220304 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1716779487; Fri, 04 Mar 2022 21:08:28 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 4 Mar 2022 21:08:27 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:26 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 15/21] arm64: dts: mt8192: Add H264 venc device node Date: Fri, 4 Mar 2022 21:08:03 +0800 Message-ID: <20220304130809.12924-16-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds H264 venc node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 1c804c925021..ac69033737bb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1336,6 +1336,29 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; }; =20 + vcodec_enc: vcodec@17020000 { + compatible =3D "mediatek,mt8192-vcodec-enc"; + reg =3D <0 0x17020000 0 0x2000>; + iommus =3D <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts =3D ; + mediatek,scp =3D <&scp>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VENC>; + clocks =3D <&vencsys CLK_VENC_SET1_VENC>; + clock-names =3D "venc-set1"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + camsys: clock-controller@1a000000 { compatible =3D "mediatek,mt8192-camsys"; reg =3D <0 0x1a000000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CBBCC433F5 for ; Fri, 4 Mar 2022 13:09:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239734AbiCDNKS (ORCPT ); Fri, 4 Mar 2022 08:10:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237672AbiCDNJX (ORCPT ); Fri, 4 Mar 2022 08:09:23 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B90E415F631; Fri, 4 Mar 2022 05:08:34 -0800 (PST) X-UUID: faa89d39760340329c60c4ebf0e7ba30-20220304 X-UUID: faa89d39760340329c60c4ebf0e7ba30-20220304 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1325909548; Fri, 04 Mar 2022 21:08:29 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:27 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 16/21] arm64: dts: mt8192: Add vcodec lat and core nodes Date: Fri, 4 Mar 2022 21:08:04 +0800 Message-ID: <20220304130809.12924-17-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vcodec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index ac69033737bb..5fd1fed354d0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1285,6 +1285,64 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: vcodec-dec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + + vcodec_lat: vcodec-lat@16010000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x16010000 0 0x800>; /* VDEC_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", + "vdec-vdec", "vdec-top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vcodec_core: vcodec-core@16025000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", + "vdec-vdec", "vdec-top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E61BC433FE for ; Fri, 4 Mar 2022 13:09:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239787AbiCDNKY (ORCPT ); Fri, 4 Mar 2022 08:10:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237464AbiCDNJW (ORCPT ); Fri, 4 Mar 2022 08:09:22 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 494F66D1BB; Fri, 4 Mar 2022 05:08:33 -0800 (PST) X-UUID: c5fd0a6bd64c4d5dbb59c361fb1d718e-20220304 X-UUID: c5fd0a6bd64c4d5dbb59c361fb1d718e-20220304 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 355013215; Fri, 04 Mar 2022 21:08:30 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:29 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 21:08:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:28 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 17/21] arm64: dts: mt8192: Add dpi node Date: Fri, 4 Mar 2022 21:08:05 +0800 Message-ID: <20220304130809.12924-18-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 5fd1fed354d0..039aba7ac0e2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1236,6 +1236,17 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + dpi0: dpi@14016000 { + compatible =3D "mediatek,mt8192-dpi"; + reg =3D <0 0x14016000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names =3D "pixel", "engine", "pll"; + status =3D "disabled"; + }; + iommu0: m4u@1401d000 { compatible =3D "mediatek,mt8192-m4u"; reg =3D <0 0x1401d000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08288C433F5 for ; Fri, 4 Mar 2022 13:09:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239665AbiCDNKO (ORCPT ); Fri, 4 Mar 2022 08:10:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237244AbiCDNJV (ORCPT ); Fri, 4 Mar 2022 08:09:21 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E1206D957; Fri, 4 Mar 2022 05:08:32 -0800 (PST) X-UUID: 2af58bfbfa564a63927302052f290172-20220304 X-UUID: 2af58bfbfa564a63927302052f290172-20220304 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 891676909; Fri, 04 Mar 2022 21:08:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 4 Mar 2022 21:08:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:29 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 18/21] arm64: dts: mt8192: Add display nodes Date: Fri, 4 Mar 2022 21:08:06 +0800 Message-ID: <20220304130809.12924-19-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 039aba7ac0e2..94f88e52776b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1205,6 +1205,13 @@ #clock-cells =3D <1>; }; =20 + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8192-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + }; + smi_common: smi@14002000 { compatible =3D "mediatek,mt8192-smi-common"; reg =3D <0 0x14002000 0 0x1000>; @@ -1236,6 +1243,110 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; }; =20 + ovl0: ovl@14005000 { + compatible =3D "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + ovl_2l0: ovl@14006000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8192-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + interrupts =3D ; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,larb =3D <&larb0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + color0: color@14009000 { + compatible =3D "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400a000 { + compatible =3D "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@1400b000 { + compatible =3D "mediatek,mt8192-disp-aal", + "mediatek,mt8193-disp-aal"; + reg =3D <0 0x1400b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@1400c000 { + compatible =3D "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400c000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + postmask0: postmask@1400d000 { + compatible =3D "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + iommus =3D <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + }; + + dither0: dither@1400e000 { + compatible =3D "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400e000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + }; + + ovl_2l2: ovl@14014000 { + compatible =3D "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + }; + + rdma4: rdma@14015000 { + compatible =3D "mediatek,mt8192-disp-rdma"; + reg =3D <0 0x14015000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; + iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size =3D <2048>; + }; + dpi0: dpi@14016000 { compatible =3D "mediatek,mt8192-dpi"; reg =3D <0 0x14016000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC06FC433F5 for ; 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Fri, 4 Mar 2022 21:08:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:29 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 19/21] arm64: dts: mt8192: Add dsi node Date: Fri, 4 Mar 2022 21:08:07 +0800 Message-ID: <20220304130809.12924-20-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dsi ndoe for mt8192 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 94f88e52776b..3d16cb0b3ea1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1327,6 +1327,20 @@ clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; }; =20 + dsi0: dsi@14010000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0 0x14010000 0 0x1000>; + interrupts =3D ; + mediatek,syscon-dsi =3D <&mmsys 0x140>; + clocks =3D <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + status =3D "disabled"; + }; + ovl_2l2: ovl@14014000 { compatible =3D "mediatek,mt8192-disp-ovl-2l"; reg =3D <0 0x14014000 0 0x1000>; --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE3FC433F5 for ; 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Fri, 4 Mar 2022 21:08:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:30 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 20/21] arm64: dts: mt8192: Add gce info for display nodes Date: Fri, 4 Mar 2022 21:08:08 +0800 Message-ID: <20220304130809.12924-21-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add gce info for display nodes - It's required to get drivers' CMDQ support Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 3d16cb0b3ea1..70b50aa0a03c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1202,6 +1202,9 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8192-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; #clock-cells =3D <1>; }; =20 @@ -1210,6 +1213,8 @@ reg =3D <0 0x14001000 0 0x1000>; interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events =3D , + ; }; =20 smi_common: smi@14002000 { @@ -1251,6 +1256,7 @@ iommus =3D <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; }; =20 ovl_2l0: ovl@14006000 { @@ -1261,6 +1267,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; }; =20 rdma0: rdma@14007000 { @@ -1272,6 +1279,7 @@ mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <5120>; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; }; =20 color0: color@14009000 { @@ -1281,6 +1289,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; =20 ccorr0: ccorr@1400a000 { @@ -1289,6 +1298,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; =20 aal0: aal@1400b000 { @@ -1298,6 +1308,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; =20 gamma0: gamma@1400c000 { @@ -1307,6 +1318,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; =20 postmask0: postmask@1400d000 { @@ -1316,6 +1328,7 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; iommus =3D <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; =20 dither0: dither@1400e000 { @@ -1325,6 +1338,7 @@ interrupts =3D ; power-domains =3D <&spm MT8192_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 dsi0: dsi@14010000 { @@ -1349,6 +1363,7 @@ clocks =3D <&mmsys CLK_MM_DISP_OVL2_2L>; iommus =3D <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; =20 rdma4: rdma@14015000 { @@ -1359,6 +1374,7 @@ clocks =3D <&mmsys CLK_MM_DISP_RDMA4>; iommus =3D <&iommu0 M4U_PORT_L1_DISP_RDMA4>; mediatek,rdma-fifo-size =3D <2048>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; =20 dpi0: dpi@14016000 { --=20 2.18.0 From nobody Sun Sep 22 07:35:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55A7DC433EF for ; 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Fri, 4 Mar 2022 21:08:31 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 21:08:31 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Allen-KH Cheng Subject: [PATCH v3 21/21] arm64: dts: mt8192: Add pwm node Date: Fri, 4 Mar 2022 21:08:09 +0800 Message-ID: <20220304130809.12924-22-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> References: <20220304130809.12924-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 70b50aa0a03c..f97d954a755a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -624,6 +624,17 @@ status =3D "disabled"; }; =20 + pwm0: pwm@1100e000 { + compatible =3D "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + #pwm-cells =3D <2>; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names =3D "main", "mm"; + status =3D "disabled"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8192-spi", "mediatek,mt6765-spi"; --=20 2.18.0