From nobody Tue Jun 23 13:01:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E529C433EF for ; Fri, 4 Mar 2022 06:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236778AbiCDGdt (ORCPT ); Fri, 4 Mar 2022 01:33:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232484AbiCDGdm (ORCPT ); Fri, 4 Mar 2022 01:33:42 -0500 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 965F82A277 for ; Thu, 3 Mar 2022 22:32:52 -0800 (PST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 2246MIZl041905; Fri, 4 Mar 2022 14:22:18 +0800 (GMT-8) (envelope-from tommy_huang@aspeedtech.com) Received: from tommy0527-VirtualBox.aspeedtech.com (192.168.2.141) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 14:31:44 +0800 From: Tommy Haung To: , , , , , , , , , CC: Subject: [PATCH v1 1/2] drm/aspeed: Add gfx flags and clock selection for AST2600 Date: Fri, 4 Mar 2022 14:31:36 +0800 Message-ID: <20220304063137.12970-2-tommy_huang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304063137.12970-1-tommy_huang@aspeedtech.com> References: <20220304063137.12970-1-tommy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.141] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 2246MIZl041905 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clock selection code for AST2600. At AST2600 user could select more than one dispaly timing. Add gfx flags for future usage. Signed-off-by: Tommy Haung --- drivers/gpu/drm/aspeed/aspeed_gfx.h | 11 +++++++++++ drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 14 ++++++++++++++ drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 4 ++++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/a= speed_gfx.h index 4e6a442c3886..eb4c267cde5e 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h @@ -16,6 +16,7 @@ struct aspeed_gfx { u32 vga_scratch_reg; u32 throd_val; u32 scan_line_max; + u32 flags; =20 struct drm_simple_display_pipe pipe; struct drm_connector connector; @@ -106,3 +107,13 @@ int aspeed_gfx_create_output(struct drm_device *drm); /* CRT_THROD */ #define CRT_THROD_LOW(x) (x) #define CRT_THROD_HIGH(x) ((x) << 8) + +/* SCU control */ +#define SCU_G6_CLK_COURCE 0x300 + +/* GFX FLAGS */ +#define CLK_MASK BIT(0) +#define CLK_G6 BIT(0) + +#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10)) +#define G6_USB_40_CLK BIT(9) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/asp= eed/aspeed_gfx_crtc.c index 827e62c1daba..a24fab22eac4 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct aspeed_= gfx *priv) regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } =20 +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) +{ + switch (priv->flags & CLK_MASK) { + case CLK_G6: + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, 0x0); + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, G6_USB_40_= CLK); + break; + default: + break; + } +} + static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) { struct drm_display_mode *m =3D &priv->pipe.crtc.state->adjusted_mode; @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_g= fx *priv) if (err) return; =20 + aspeed_gfx_set_clk(priv); + #if 0 /* TODO: we have only been able to test with the 40MHz USB clock. The * clock is fixed, so we cannot adjust it here. */ diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspe= ed/aspeed_gfx_drv.c index d10246b1d1c2..af56ffdccc65 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -64,6 +64,7 @@ struct aspeed_gfx_config { u32 vga_scratch_reg; /* VGA scratch register in SCU */ u32 throd_val; /* Default Threshold Seting */ u32 scan_line_max; /* Max memory size of one scan line */ + u32 gfx_flags; /* Flags for gfx chip caps */ }; =20 static const struct aspeed_gfx_config ast2400_config =3D { @@ -72,6 +73,7 @@ static const struct aspeed_gfx_config ast2400_config =3D { .vga_scratch_reg =3D 0x50, .throd_val =3D CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12), .scan_line_max =3D 64, + .gfx_flags =3D 0, }; =20 static const struct aspeed_gfx_config ast2500_config =3D { @@ -80,6 +82,7 @@ static const struct aspeed_gfx_config ast2500_config =3D { .vga_scratch_reg =3D 0x50, .throd_val =3D CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c), .scan_line_max =3D 128, + .gfx_flags =3D 0, }; =20 static const struct aspeed_gfx_config ast2600_config =3D { @@ -88,6 +91,7 @@ static const struct aspeed_gfx_config ast2600_config =3D { .vga_scratch_reg =3D 0x50, .throd_val =3D CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70), .scan_line_max =3D 128, + .gfx_flags =3D CLK_G6, }; =20 static const struct of_device_id aspeed_gfx_match[] =3D { --=20 2.17.1 From nobody Tue Jun 23 13:01:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 413BBC433EF for ; Fri, 4 Mar 2022 06:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238416AbiCDGdx (ORCPT ); Fri, 4 Mar 2022 01:33:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232625AbiCDGdm (ORCPT ); Fri, 4 Mar 2022 01:33:42 -0500 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 968ED2B264 for ; Thu, 3 Mar 2022 22:32:52 -0800 (PST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 2246MIcb041906; Fri, 4 Mar 2022 14:22:18 +0800 (GMT-8) (envelope-from tommy_huang@aspeedtech.com) Received: from tommy0527-VirtualBox.aspeedtech.com (192.168.2.141) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 14:31:44 +0800 From: Tommy Haung To: , , , , , , , , , CC: Subject: [PATCH v1 2/2] drm/aspeed: Add 1024x768 mode for AST2600 Date: Fri, 4 Mar 2022 14:31:37 +0800 Message-ID: <20220304063137.12970-3-tommy_huang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304063137.12970-1-tommy_huang@aspeedtech.com> References: <20220304063137.12970-1-tommy_huang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.141] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 2246MIcb041906 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the aspeed_gfx_set_clk with display width. At AST2600, the display clock could be coming from HPLL clock / 16 =3D 75MHz. It would fit 1024x768@70Hz. Another chip will still keep 800x600. Signed-off-by: Tommy Haung --- drivers/gpu/drm/aspeed/aspeed_gfx.h | 12 ++++++---- drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 29 ++++++++++++++++++++---- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 16 +++++++++++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14 +++++++++++- 4 files changed, 60 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/a= speed_gfx.h index eb4c267cde5e..c7aefee0657a 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h @@ -109,11 +109,15 @@ int aspeed_gfx_create_output(struct drm_device *drm); #define CRT_THROD_HIGH(x) ((x) << 8) =20 /* SCU control */ -#define SCU_G6_CLK_COURCE 0x300 +#define G6_CLK_SOURCE 0x300 +#define G6_CLK_SOURCE_MASK (BIT(8) | BIT(9) | BIT(10)) +#define G6_CLK_SOURCE_HPLL (BIT(8) | BIT(9) | BIT(10)) +#define G6_CLK_SOURCE_USB BIT(9) +#define G6_CLK_SEL3 0x308 +#define G6_CLK_DIV_MASK 0x3F000 +#define G6_CLK_DIV_16 (BIT(16)|BIT(15)|BIT(13)|BIT(12)) +#define G6_USB_40_CLK BIT(9) =20 /* GFX FLAGS */ #define CLK_MASK BIT(0) #define CLK_G6 BIT(0) - -#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10)) -#define G6_USB_40_CLK BIT(9) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/asp= eed/aspeed_gfx_crtc.c index a24fab22eac4..5829be9c7c67 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -23,6 +23,28 @@ drm_pipe_to_aspeed_gfx(struct drm_simple_display_pipe *p= ipe) return container_of(pipe, struct aspeed_gfx, pipe); } =20 +static void aspeed_gfx_set_clock_source(struct aspeed_gfx *priv, int mode_= width) +{ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, G6_CLK_SOURCE_MASK, 0x0); + regmap_update_bits(priv->scu, G6_CLK_SEL3, G6_CLK_DIV_MASK, 0x0); + + switch (mode_width) { + case 1024: + /* hpll div 16 =3D 75Mhz */ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_HPLL); + regmap_update_bits(priv->scu, G6_CLK_SEL3, + G6_CLK_DIV_MASK, G6_CLK_DIV_16); + break; + case 800: + default: + /* usb 40Mhz */ + regmap_update_bits(priv->scu, G6_CLK_SOURCE, + G6_CLK_SOURCE_MASK, G6_CLK_SOURCE_USB); + break; + } +} + static int aspeed_gfx_set_pixel_fmt(struct aspeed_gfx *priv, u32 *bpp) { struct drm_crtc *crtc =3D &priv->pipe.crtc; @@ -77,12 +99,11 @@ static void aspeed_gfx_disable_controller(struct aspeed= _gfx *priv) regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } =20 -static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv, int mode_width) { switch (priv->flags & CLK_MASK) { case CLK_G6: - regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, 0x0); - regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, G6_USB_40_= CLK); + aspeed_gfx_set_clock_source(priv, mode_width); break; default: break; @@ -99,7 +120,7 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_= gfx *priv) if (err) return; =20 - aspeed_gfx_set_clk(priv); + aspeed_gfx_set_clk(priv, m->hdisplay); =20 #if 0 /* TODO: we have only been able to test with the 40MHz USB clock. The diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspe= ed/aspeed_gfx_drv.c index af56ffdccc65..e1a814aebc2d 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -110,6 +110,7 @@ static const struct drm_mode_config_funcs aspeed_gfx_mo= de_config_funcs =3D { =20 static int aspeed_gfx_setup_mode_config(struct drm_device *drm) { + struct aspeed_gfx *priv =3D to_aspeed_gfx(drm); int ret; =20 ret =3D drmm_mode_config_init(drm); @@ -118,8 +119,18 @@ static int aspeed_gfx_setup_mode_config(struct drm_dev= ice *drm) =20 drm->mode_config.min_width =3D 0; drm->mode_config.min_height =3D 0; - drm->mode_config.max_width =3D 800; - drm->mode_config.max_height =3D 600; + + switch (priv->flags & CLK_MASK) { + case CLK_G6: + drm->mode_config.max_width =3D 1024; + drm->mode_config.max_height =3D 768; + break; + default: + drm->mode_config.max_width =3D 800; + drm->mode_config.max_height =3D 600; + break; + } + drm->mode_config.funcs =3D &aspeed_gfx_mode_config_funcs; =20 return ret; @@ -167,6 +178,7 @@ static int aspeed_gfx_load(struct drm_device *drm) priv->vga_scratch_reg =3D config->vga_scratch_reg; priv->throd_val =3D config->throd_val; priv->scan_line_max =3D config->scan_line_max; + priv->flags =3D config->gfx_flags; =20 priv->scu =3D syscon_regmap_lookup_by_phandle(np, "syscon"); if (IS_ERR(priv->scu)) { diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c b/drivers/gpu/drm/aspe= ed/aspeed_gfx_out.c index 6759cb88415a..5d5e04f15c59 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_out.c @@ -10,7 +10,19 @@ =20 static int aspeed_gfx_get_modes(struct drm_connector *connector) { - return drm_add_modes_noedid(connector, 800, 600); + struct aspeed_gfx *priv =3D container_of(connector, struct aspeed_gfx, co= nnector); + int mode_count =3D 0; + + switch (priv->flags & CLK_MASK) { + case CLK_G6: + mode_count =3D drm_add_modes_noedid(connector, 1024, 768); + break; + default: + mode_count =3D drm_add_modes_noedid(connector, 800, 600); + break; + } + + return mode_count; } =20 static const struct --=20 2.17.1