From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D8D4C4321E for ; Wed, 2 Mar 2022 20:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243484AbiCBUbz (ORCPT ); Wed, 2 Mar 2022 15:31:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243471AbiCBUbu (ORCPT ); Wed, 2 Mar 2022 15:31:50 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 801F8CE924 for ; Wed, 2 Mar 2022 12:31:03 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id p17so2569316plo.9 for ; Wed, 02 Mar 2022 12:31:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g11sci1g7elBgDqwDkIww3iURlfsGrxIIuaKlSKDbrU=; b=Rw3jcqSZCZ1vmJXAdgh/+bwdTkwGr9/04ntUuK/sbNkA55vJpVp5VBOj3qoKrcNCtb 6cwILjxtxfZCX36e3R9ifjIPNhZVQhq6uChZDHdPncGbxVecDSvG3/GoTC38muQ9jE50 AovKrawIGHmB5Wx8KZzo+rFN/r/tbbFuH1WWqf+2NBHHzCOu/bbuT12fvVbsMOfqXWHu al2uF1+O8zpJt6a+pF4KW+diM+9QH6GZkXzn2XjHCjFQY4R4eP72Lz3vuV7e0raoe09F 1XkjaA/x9IVfhXs8rASx7mJGh/YTZTwH7RkI3YboV1JTSJAO9Ze+D1JbFEHuSK1x/BbD KbAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g11sci1g7elBgDqwDkIww3iURlfsGrxIIuaKlSKDbrU=; b=se2q61MTg8KMMHTrB37Yq6qAnNUQqAlsAA8x/i01OCrkuntipGqQX1x1iE7Z2lPQ8D n2g1Nq2Vndo5+fCwFhXBmZatCQakLanCGGjbVwIAY2VOec90E8Ek6Z0E6ouVjzCMXkaN mk2/GDJp+UZ5LezxgGmiFk92dHZYHWc1PYSdV2CQQPFPQRQLXHL+ArnCXnfqA/tD07KZ wBUYpaemKQeUhgi2qegmegaUCY9Vw2A/ZrF1DJTrhaRHvfzXJ8H8IOJNQlgknZifSzRo wRQfQoF3+lrFLqcJlZAutxJRbkXRJZlNtsIGNugN7g8/22LJVy1IWagLZPRfjqnfAjnu xv3w== X-Gm-Message-State: AOAM531tFqD+NIxpb7sAgXzjtyl325xVnX10BP+EA1PNoqhsFFUnYVU2 inAmyfMIG4CzBGcqEPYW8xvbkQ== X-Google-Smtp-Source: ABdhPJyhjo4ntKrVS36JVnPPurPWA7B4mWW7sqgCoPxfKzyHqFGRQiUlyHUBokTrfvUDLiDHQ5E0gQ== X-Received: by 2002:a17:903:250:b0:151:6aef:b562 with SMTP id j16-20020a170903025000b001516aefb562mr16877585plh.30.1646253063011; Wed, 02 Mar 2022 12:31:03 -0800 (PST) Received: from localhost.localdomain ([182.64.85.91]) by smtp.gmail.com with ESMTPSA id b1-20020a17090aa58100b001bcb7bad374sm5963410pjq.17.2022.03.02.12.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:31:02 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Rob Herring Subject: [PATCH v3 1/7] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC Date: Thu, 3 Mar 2022 02:00:39 +0530 Message-Id: <20220302203045.184500-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to the one used on SM8250. Cc: Lorenzo Pieralisi Cc: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Document= ation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..a023f97daf84 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8150" for sm8150 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 =20 @@ -157,7 +158,7 @@ - "pipe" PIPE clock =20 - clock-names: - Usage: required for sc8180x and sm8250 + Usage: required for sc8180x, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -246,7 +247,7 @@ - "ahb" AHB reset =20 - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68435C433F5 for ; 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Wed, 02 Mar 2022 12:31:07 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Rob Herring Subject: [PATCH v3 2/7] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings Date: Thu, 3 Mar 2022 02:00:40 +0530 Message-Id: <20220302203045.184500-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the following two PCIe PHYs found on SM8150, to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Acked-by: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e417cd667997..9e0f60e682c4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -38,6 +38,8 @@ properties: - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm6115-qmp-ufs-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy @@ -333,6 +335,8 @@ allOf: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B38CC43217 for ; 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Wed, 02 Mar 2022 12:31:13 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org Subject: [PATCH v3 3/7] clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 Date: Thu, 3 Mar 2022 02:00:41 +0530 Message-Id: <20220302203045.184500-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma --- drivers/clk/qcom/gcc-sm8150.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 ++ 2 files changed, 22 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 245794485719..7e478dc2cefe 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3448,6 +3448,24 @@ static struct clk_branch gcc_video_xo_clk =3D { }, }; =20 +static struct gdsc pcie_0_gdsc =3D { + .gdscr =3D 0x6b004, + .pd =3D { + .name =3D "pcie_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + +static struct gdsc pcie_1_gdsc =3D { + .gdscr =3D 0x8d004, + .pd =3D { + .name =3D "pcie_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR, +}; + static struct gdsc usb30_prim_gdsc =3D { .gdscr =3D 0xf004, .pd =3D { @@ -3714,6 +3732,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[= ] =3D { }; =20 static struct gdsc *gcc_sm8150_gdscs[] =3D { + [PCIE_0_GDSC] =3D &pcie_0_gdsc, + [PCIE_1_GDSC] =3D &pcie_1_gdsc, [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, [USB30_SEC_GDSC] =3D &usb30_sec_gdsc, }; diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindi= ngs/clock/qcom,gcc-sm8150.h index 3e1a91876610..ae9c16410420 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -241,6 +241,8 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 =20 /* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 =20 --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7F77C433F5 for ; Wed, 2 Mar 2022 20:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243613AbiCBUcM (ORCPT ); Wed, 2 Mar 2022 15:32:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243765AbiCBUcD (ORCPT ); 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Wed, 02 Mar 2022 12:31:18 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Vinod Koul Subject: [PATCH v3 4/7] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Date: Thu, 3 Mar 2022 02:00:42 +0530 Message-Id: <20220302203045.184500-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8150 has multiple (different) PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Add support for these with relevant init sequence. Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma --- drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy= -qcom-qmp.c index 8ea87c69f463..0805c1bab690 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] =3D= { "aux", "cfg_ahb", "ref", "refgen", }; =20 +/* the pcie phy on sm8150 doesn't have a ref clock */ +static const char * const sm8150_pciephy_clk_l[] =3D { + "aux", "cfg_ahb", "refgen", +}; + static const char * const qmp_v4_phy_clk_l[] =3D { "aux", "ref_clk_src", "ref", "com_aux", }; @@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_c= fg =3D { .pwrdn_delay_max =3D 1005, /* us */ }; =20 +static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 1, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec =3D sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 2, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .is_dual_lane_phy =3D true, + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg =3D { .type =3D PHY_TYPE_PCIE, .nlanes =3D 1, @@ -6004,6 +6088,12 @@ static const struct of_device_id qcom_qmp_phy_of_mat= ch_table[] =3D { }, { .compatible =3D "qcom,sm6115-qmp-ufs-phy", .data =3D &sm6115_ufsphy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy", + .data =3D &sm8150_qmp_gen3x1_pciephy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy", + .data =3D &sm8150_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,sm8150-qmp-ufs-phy", .data =3D &sm8150_ufsphy_cfg, --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D8BBC433FE for ; Wed, 2 Mar 2022 20:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243941AbiCBUcY (ORCPT ); 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Wed, 02 Mar 2022 12:31:24 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Vinod Koul , Dmitry Baryshkov Subject: [PATCH v3 5/7] PCI: qcom: Add SM8150 SoC support Date: Thu, 3 Mar 2022 02:00:43 +0530 Message-Id: <20220302203045.184500-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on SM8250. Hence the support is added reusing the members of ops_1_9_0. Cc: Vinod Koul Cc: Rob Herring Reviewed-by: Dmitry Baryshkov Signed-off-by: Bhupesh Sharma --- drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c19cd506ed3f..564e2f10ea65 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1511,6 +1511,13 @@ static const struct qcom_pcie_cfg sdm845_cfg =3D { .ops =3D &ops_2_7_0, }; =20 +static const struct qcom_pcie_cfg sm8150_cfg =3D { + /* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as + * 1.9.0, so reuse the same. + */ + .ops =3D &ops_1_9_0, +}; + static const struct qcom_pcie_cfg sm8250_cfg =3D { .ops =3D &ops_1_9_0, }; @@ -1626,6 +1633,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-ipq4019", .data =3D &ipq4019_cfg }, { .compatible =3D "qcom,pcie-qcs404", .data =3D &ipq4019_cfg }, { .compatible =3D "qcom,pcie-sdm845", .data =3D &sdm845_cfg }, + { .compatible =3D "qcom,pcie-sm8150", .data =3D &sm8150_cfg }, { .compatible =3D "qcom,pcie-sm8250", .data =3D &sm8250_cfg }, { .compatible =3D "qcom,pcie-sc8180x", .data =3D &sm8250_cfg }, { .compatible =3D "qcom,pcie-sc7280", .data =3D &sc7280_cfg }, --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C93D8C433EF for ; Wed, 2 Mar 2022 20:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243808AbiCBUcc (ORCPT ); Wed, 2 Mar 2022 15:32:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243681AbiCBUcU (ORCPT ); Wed, 2 Mar 2022 15:32:20 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64D56DB849 for ; Wed, 2 Mar 2022 12:31:31 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id z12-20020a17090ad78c00b001bf022b69d6so1735125pju.2 for ; Wed, 02 Mar 2022 12:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ZB0wmcHb/vPxT3OXeuOvQMbxgsgyn+6ztoW0hvGJJA=; b=J6aCv62JRv8pXKSN4faWU++P8+CfLEZhXxOFQNT7HfYNhIEB5EhOknuDcp7y90Wsam PaVTrXj/fKbQE7u1oWbVQRx0RjvIBQvkTXECdtmEwjw9dzeCuBdIwFnydrP7xDtH/UFb ED/xiCG1RhCOxuEu8ja7Zq7f08eL/Iyj4XoSBCaKZ2RJHHMsMHf1HI0quqXEDVyv0HMp rtcvFN9IS+eEynrmaJRJZAc4tMD75bkdzDPMI31DWLb4bhPYdAgCCpjCAnymiSYDHmVq bCETryp6zYTQRvFyP87TuGqfEv2chYjD+vxjB189GXg7wv3oF+qC3jrY2BW551ZwovjB EFnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ZB0wmcHb/vPxT3OXeuOvQMbxgsgyn+6ztoW0hvGJJA=; b=NTEPTQikRAkR6YVG8mLywhBNX0IWRV19EtfkRleZAImINMLBwCTVxJdGEW2ny7JJVa AewIjPEf9MSSPz4meG8AIaBbiFOlhcorg1ut1tYPkGewzOpo4IIdGn5A/MjCXcbueQzm Pn8rQqgawMW70dza+Ty8i/1j5JeKd+0uL/PisErUFK44c9uMPcijjJ5pMaRZi4lBDCsG sQpmpFo0lOt5ZayJp/QTGPYX+UFKjq4JySqjnztM7nSWKaYe9lPV1L1Y3Ib6Kcn8VlzF LZJCjNmZUUCSUcG6ZyfeY+piGBI5NTFHVJMzfvbAnoIEeRDJNRTHPWwK4Y/Pav2WSSVF V/sg== X-Gm-Message-State: AOAM532xlu62xm1HF3kNE69kABK9s1n7DIeBseGeTsOYvEW+gy4N0BKn qWTskJTqm8DsSG/kFgXuJGeeHw== X-Google-Smtp-Source: ABdhPJyYuh2Fbf8DNP4cMJhNZHLXeireD7xt0LcQmeEs6jt/bpr0UnDN0KyUO0ZDi7d88WtLnvTfOw== X-Received: by 2002:a17:90a:8582:b0:1b9:b0da:9ca9 with SMTP id m2-20020a17090a858200b001b9b0da9ca9mr1603031pjn.146.1646253090636; Wed, 02 Mar 2022 12:31:30 -0800 (PST) Received: from localhost.localdomain ([182.64.85.91]) by smtp.gmail.com with ESMTPSA id b1-20020a17090aa58100b001bcb7bad374sm5963410pjq.17.2022.03.02.12.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:31:30 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org Subject: [PATCH v3 6/7] arm64: dts: qcom: sm8150: Add PCIe nodes Date: Thu, 3 Mar 2022 02:00:44 +0530 Message-Id: <20220302203045.184500-7-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for the two PCIe controllers found on the SM8150 SoC. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 6012322a5984..598bc3d1ce69 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1626,6 +1626,203 @@ system-cache-controller@9200000 { interrupts =3D ; }; =20 + pcie0: pci@1c00000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommus =3D <&apps_smmu 0x1d80 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie0_lane: phy@1c06200 { + reg =3D <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1e00 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c0e000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie1_lane: phy@1c0e200 { + reg =3D <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default { drive-strength =3D <6>; bias-disable; }; + + pcie0_default_state: pcie0-default { + perst { + pins =3D "gpio35"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio36"; + function =3D "pci_e0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio37"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio103"; + function =3D "pci_e1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio104"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; }; =20 remoteproc_mpss: remoteproc@4080000 { --=20 2.35.1 From nobody Tue Jun 23 16:15:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE635C43217 for ; Wed, 2 Mar 2022 20:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235803AbiCBUc3 (ORCPT ); Wed, 2 Mar 2022 15:32:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244002AbiCBUcY (ORCPT ); Wed, 2 Mar 2022 15:32:24 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A66EFCFB83 for ; Wed, 2 Mar 2022 12:31:36 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id e13so2592034plh.3 for ; Wed, 02 Mar 2022 12:31:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6aVyDbY8mWFDs86ZSUd7TuJOdBkBFLjs80gN0LS4pVY=; b=Tl7NEZvhUZpdTwcmNe+f/k3vBpnZvUbtaafcgnb2OUtQN33/NOBKA/oOQ83psaAVPk ggqvLNZym/zESiPo+8EUetAQy/d9qUY7s2BiZt0LZkm0sKEeA5/D8/HwZvEckCcIEdrY OQanc3Gn4bz62tkHmduupGz7wi+r28JZYuSuoQBa2yQRigViwFSMqIzy7JDPEbcoOms8 7eO7Nrxq3LZKUCFVQjdIrgMFoRgJQRgcTujW9CfhQ5Z4NZRH9Ylgnl8iamL1PuTHzPXz iNpAIRTpPJKf57odccoTGvQgJMBzIzUUxAFP8IDV5dBcD90xXnj2fDLHZ1bq8MQvAzRK Kjxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6aVyDbY8mWFDs86ZSUd7TuJOdBkBFLjs80gN0LS4pVY=; b=h4n0pkjtX5nZzVHuT2vj/NVVR2w+nOANtcI+709NADzvgQKCcZpRzN0xC9YpaGMROb igFCl8HAT6cw/ihGzZngdLhWde2DsVPDXjSqYnA6iSm5eDfgoYqhasEQnS6/g2dh6xsA 14ufL7fxHBXlouoNLlB+M8wcbj84YG7v4JmBbcDw38afpx8z47T54wv/fF7R7VdhOSE8 BsL/v3yUuFQR/tQ4i9ay+DXLRqdxBnMlyVPsRq9fRLNTP00dl+RtGM/OGlrHN6x5/R9v Ze6XgQ3WIbDreuEUC/SCeTkP4CRmrpQIEbIuEW65fIPt2lUdTtH3LHuTzlzE94up30HB a+SQ== X-Gm-Message-State: AOAM530dIdB70OnMdHNnmHZE6yKdF3xrSDqwkSsuCo72lU5ln6Q6K+NI mEuVpmJ8UC+TvMlxiYcPimdlYw== X-Google-Smtp-Source: ABdhPJxMxp1gqbVtF9DFn3Tc3YJZqRD1Zo0skonvDO+wrA4GxmhhC4lZ0Rzrnob3c5L5q3wx3aE5MQ== X-Received: by 2002:a17:90b:f8a:b0:1be:dccd:e4f7 with SMTP id ft10-20020a17090b0f8a00b001bedccde4f7mr1627856pjb.92.1646253096058; Wed, 02 Mar 2022 12:31:36 -0800 (PST) Received: from localhost.localdomain ([182.64.85.91]) by smtp.gmail.com with ESMTPSA id b1-20020a17090aa58100b001bcb7bad374sm5963410pjq.17.2022.03.02.12.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:31:35 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Vinod Koul Subject: [PATCH v3 7/7] arm64: dts: qcom: sa8155: Enable PCIe nodes Date: Thu, 3 Mar 2022 02:00:45 +0530 Message-Id: <20220302203045.184500-8-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220302203045.184500-1-bhupesh.sharma@linaro.org> References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8155p-adp.dts index 8756c2b25c7e..3f6b3ee404f5 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -387,9 +387,51 @@ &usb_2_qmpphy { vdda-pll-supply =3D <&vdda_usb_ss_dp_core_1>; }; =20 +&pcie0 { + status =3D "okay"; +}; + +&pcie0_phy { + status =3D "okay"; + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + &tlmm { gpio-reserved-ranges =3D <0 4>; =20 + bt_en_default: bt_en_default { + mux { + pins =3D "gpio172"; + function =3D "gpio"; + }; + + config { + pins =3D "gpio172"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + wlan_en_default: wlan_en_default { + mux { + pins =3D "gpio169"; + function =3D "gpio"; + }; + + config { + pins =3D "gpio169"; + drive-strength =3D <16>; + output-high; + bias-pull-up; + }; + }; + usb2phy_ac_en1_default: usb2phy_ac_en1_default { mux { pins =3D "gpio113"; --=20 2.35.1