From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 780A7C433F5 for ; Tue, 1 Mar 2022 12:33:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234768AbiCAMed (ORCPT ); Tue, 1 Mar 2022 07:34:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234681AbiCAMec (ORCPT ); Tue, 1 Mar 2022 07:34:32 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D82E59287A for ; Tue, 1 Mar 2022 04:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138030; x=1677674030; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yt27LNUTflYgzhTyHkUhcmzYyrzGjKVHAKDiaE7aibE=; b=VjuS0P5vrOmjLrJ7IOaD3LTaqcSjPQ0wIpbnI9L+iD8Eq7khDIRVDQS0 JdEgybzlk0OsFwNcivRxPxIWFe17ieCg/Sy4GAkE6TRGEcNUCOWEwkLlQ PuWueN1wkGd0kwyLB1lcy3aiHoxGBUTLGHsnMOKE/JUV2KksfngJ/Ha3n f5TLc5W7YYdS6MzY+vcjKHa4CvaULMJnp6XkyRYdMdFuVsbd4CR3Tej5A OQvES1m0fF5o+y1RpLjyW1xLJTqDOVRMtierh7JNwbCavHr2PIoAsnOYG I7YJ9k2hBSdaNvRoym7UUXIUUiAJ58jHd3ZILnVcMr5TeK1eEDeQI2uj1 A==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="150385095" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:33:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:49 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:48 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 1/7] clocksource/drivers/timer-microchip-pit64b: remove mmio selection Date: Tue, 1 Mar 2022 14:34:43 +0200 Message-ID: <20220301123449.2816625-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PIT64B timer driver doesn't depend on CLKSRC_MMIO since commit e85c1d21b16b ("clocksource/drivers/timer-microchip-pit64b: Add clocksource suspend/resume"). Remove the selection. Signed-off-by: Claudiu Beznea --- drivers/clocksource/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cfb8ea0df3b1..1ea556e75494 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -713,7 +713,6 @@ config INGENIC_OST config MICROCHIP_PIT64B bool "Microchip PIT64B support" depends on OF || COMPILE_TEST - select CLKSRC_MMIO select TIMER_OF help This option enables Microchip PIT64B timer for Atmel --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC4AC433F5 for ; Tue, 1 Mar 2022 12:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234785AbiCAMek (ORCPT ); Tue, 1 Mar 2022 07:34:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234708AbiCAMec (ORCPT ); Tue, 1 Mar 2022 07:34:32 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6731592D2A for ; Tue, 1 Mar 2022 04:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138032; x=1677674032; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kVbe5kyjR6LZvsZoGI+3OLtGGwUKh9RENE9A7JuYgqA=; b=tTRUTFDcTltst6ZHrHrcQ2Xtg24IlzmG0A9eQLjlkXCnLqHXS6hUIxuB t2yb9Up5or/kgwiRoSGoGgiiozLiKESWiRKtYTAFxsiN2ML967X6+rLIX hwmNXChqhn1PwIJZGPnY9xUzwIbxUeWP61WIUxCSvdw3pRdaIsmhcHz3r AiEyAW8rdm66VkBunSm7HfDGg2ESfLLGKiNR9rZ8DqnViXHCfEWU2Mqfd TFt04adzaKeIwSe5EuGp//s85kgEq8Wr2iFYWftlHJW8ikoTHWtN+ixnD Inr5v2MF5VkVRDoxFNJFazZlqs/TyR5I+WYO/56SEKaYAYdjKRnOk89im A==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="87382485" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:33:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:51 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:50 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 2/7] clocksource/drivers/timer-microchip-pit64b: remove timer-of depenency Date: Tue, 1 Mar 2022 14:34:44 +0200 Message-ID: <20220301123449.2816625-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PIT64B driver doesn't use timer-of APIs. Thus, remove the selection. Signed-off-by: Claudiu Beznea Reported-by: kernel test robot --- drivers/clocksource/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 1ea556e75494..3aee0ffad1fe 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -713,7 +713,6 @@ config INGENIC_OST config MICROCHIP_PIT64B bool "Microchip PIT64B support" depends on OF || COMPILE_TEST - select TIMER_OF help This option enables Microchip PIT64B timer for Atmel based system. It supports the oneshot, the periodic --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F364C433EF for ; Tue, 1 Mar 2022 12:34:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234803AbiCAMeo (ORCPT ); Tue, 1 Mar 2022 07:34:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234693AbiCAMee (ORCPT ); Tue, 1 Mar 2022 07:34:34 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 235FE92D2A for ; Tue, 1 Mar 2022 04:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138035; x=1677674035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3OTySUvfj9YLZ+NLvxOpjOu3QfEnAa4NzFTMBjne5gU=; b=bEQD7fPk2YD6WkS5TYVDGIP+INT94fLaNyJcgJBmfiFXhK6YpUZxKliw IudSlsksewk12MF92CL+AZCwKhEWXMmetZStmo01XkFczue3X19jyVDjt pfmW0HzVyT1vvyAF2Aof3hMVeK7L4LHFY5Gd8cgI8uATND/OE9MgOZPiB 9sI3lzUeu11Gr34tRGgDa5mNDmT8/gEcVeLx9MJj8XmTjDX/nwH4Pmv60 Tel/gZNPGfv0qWmHtZqXlF8vbpXLOy0UE6us6GEfnpBcU3UYmVLmmtn63 k5N1sbSHCRqX/yQFBcmo/TGfXQg1eNFIg0qI6DhHQ6s7GIA1MZvCgeatC Q==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="147642333" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:33:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:53 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:51 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 3/7] clocksource/drivers/timer-microchip-pit64b: use notrace Date: Tue, 1 Mar 2022 14:34:45 +0200 Message-ID: <20220301123449.2816625-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use notrace for mchp_pit64b_sched_read_clk() to avoid recursive call of prepare_ftrace_return() when issuing: echo function_graph > /sys/kernel/debug/tracing/current_tracer Fixes: 625022a5f160 ("clocksource/drivers/timer-microchip-pit64b: Add Micro= chip PIT64B support") Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index cfa4ec7ef396..790d2c9b42a7 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -165,7 +165,7 @@ static u64 mchp_pit64b_clksrc_read(struct clocksource *= cs) return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); } =20 -static u64 mchp_pit64b_sched_read_clk(void) +static u64 notrace mchp_pit64b_sched_read_clk(void) { return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); } --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C50C433EF for ; Tue, 1 Mar 2022 12:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234811AbiCAMer (ORCPT ); Tue, 1 Mar 2022 07:34:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234776AbiCAMeg (ORCPT ); Tue, 1 Mar 2022 07:34:36 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 964489681F for ; Tue, 1 Mar 2022 04:33:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138035; x=1677674035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jti6Lf93/pkshsUoxGsmUk/NZEDKA40Cet1PtYYdvz4=; b=X1JMbmD6swKofxwq1wnJmHZ8Fk/qyFUgZF6nkGEzVM4VG5Oi84n+E5/m 5n2KihTMTRz0k8TFYcDvloGM6eOXXFasb3p//RAoMAYNGw3oNCZIOfE7j /NoCBQ8LdppABbZ6HLw7Bkd+5Gd4S3ZgTtVRyL9k8jsbMWzRJ2PlfWoaG t2p92ZASH2f4QSHisBQYeUeIrGqrp32bi2eOWN6B2hADhNsgSzqT/oX96 pszoTne9YaqcGy1qMs9GxdP9KTYgjcEOT9lINxJcAsZhOWNx6S8grs6Cc W8aH0oJrC8cwV2dxQN4U3GRS8mQ65UjM8apxNMSFFLKn/YGgLetPhQRit Q==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="150385102" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:33:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:54 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:53 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 4/7] clocksource/drivers/timer-microchip-pit64b: use 5MHz for clockevent Date: Tue, 1 Mar 2022 14:34:46 +0200 Message-ID: <20220301123449.2816625-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use 5MHz clock for clockevent timers. This increases timer's resolution. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index 790d2c9b42a7..abce83d2f00b 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -42,8 +42,7 @@ #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) -#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */ -#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */ +#define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */ =20 #define MCHP_PIT64B_NAME "pit64b" =20 @@ -418,7 +417,6 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_p= it64b_timer *timer, static int __init mchp_pit64b_dt_init_timer(struct device_node *node, bool clkevt) { - u32 freq =3D clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ; struct mchp_pit64b_timer timer; unsigned long clk_rate; u32 irq =3D 0; @@ -446,7 +444,7 @@ static int __init mchp_pit64b_dt_init_timer(struct devi= ce_node *node, } =20 /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ - ret =3D mchp_pit64b_init_mode(&timer, freq); + ret =3D mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ); if (ret) goto irq_unmap; =20 --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3F9AC433F5 for ; Tue, 1 Mar 2022 12:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234809AbiCAMet (ORCPT ); Tue, 1 Mar 2022 07:34:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234780AbiCAMei (ORCPT ); Tue, 1 Mar 2022 07:34:38 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9D759683A for ; Tue, 1 Mar 2022 04:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138037; x=1677674037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CGECGO3DLDF9kAjkJpmPmmKockfvvVD5RT0cNRq2/PE=; b=cJXnX/mbCDrjNLbPcgMOropnspHSblNsFp7GJxKiaaLycaaNNnCbeM3a D/uOo9ZOrI6ulHfvVnnnmnxpkkpA4kW89ZIjofSlEpg1nkDyRcAKOHLPB WUtRMa5tZWntFa69lgcWn7qNlh1+GcnLXg0R8zUecM9e9hTDC8WTHWtIR deqIdZ3oBvVn59MUr8u50/bhd6ePfyFp9ZGtg2CXrcdwHXKwf5CTLz27R 6t1HpkVnFyMVyhYR392SZTf6IQVWbHfzk7wSyS9eGAvMJAcfhrUbc3Wkx 7RRMbYO/UMVkehuzYteyo1I4LrmF46TeUk7IbMOC37xeJ4UbiRd6+VDbD w==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="155253478" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:33:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:56 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:55 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 5/7] clocksource/drivers/timer-microchip-pit64b: remove suspend/resume ops for ce Date: Tue, 1 Mar 2022 14:34:47 +0200 Message-ID: <20220301123449.2816625-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 30 +++++++++++--------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index abce83d2f00b..b51259395ac3 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -173,7 +173,8 @@ static int mchp_pit64b_clkevt_shutdown(struct clock_eve= nt_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); + if (!clockevent_state_detached(cedev)) + mchp_pit64b_suspend(timer); =20 return 0; } @@ -182,35 +183,37 @@ static int mchp_pit64b_clkevt_set_periodic(struct clo= ck_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + if (clockevent_state_shutdown(cedev)) + mchp_pit64b_resume(timer); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT, MCHP_PIT64B_IER_PERIOD); =20 return 0; } =20 -static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) +static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) { struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); =20 - mchp_pit64b_suspend(timer); -} - -static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) -{ - struct mchp_pit64b_timer *timer =3D clkevt_to_mchp_pit64b_timer(cedev); + mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, + MCHP_PIT64B_IER_PERIOD); =20 - mchp_pit64b_resume(timer); + return 0; } =20 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) @@ -395,9 +398,8 @@ static int __init mchp_pit64b_init_clkevt(struct mchp_p= it64b_timer *timer, ce->clkevt.rating =3D 150; ce->clkevt.set_state_shutdown =3D mchp_pit64b_clkevt_shutdown; ce->clkevt.set_state_periodic =3D mchp_pit64b_clkevt_set_periodic; + ce->clkevt.set_state_oneshot =3D mchp_pit64b_clkevt_set_oneshot; ce->clkevt.set_next_event =3D mchp_pit64b_clkevt_set_next_event; - ce->clkevt.suspend =3D mchp_pit64b_clkevt_suspend; - ce->clkevt.resume =3D mchp_pit64b_clkevt_resume; ce->clkevt.cpumask =3D cpumask_of(0); ce->clkevt.irq =3D irq; =20 --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 013D0C433F5 for ; Tue, 1 Mar 2022 12:34:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234829AbiCAMez (ORCPT ); Tue, 1 Mar 2022 07:34:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234783AbiCAMej (ORCPT ); Tue, 1 Mar 2022 07:34:39 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E77B295A30 for ; Tue, 1 Mar 2022 04:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138040; x=1677674040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=43qiS6l/WyBCSmUqkK2jh3Y6sKNvcyLpeI6tzHqMrPE=; b=Il6yuQ1elDuFTze4gx8Qhb8rCShd5ZWQv6KblkEkGwrEDpV1sXWPSiAh qiiokYSlmKVAFKspA8yeEr18Iqxuk03t/JscRfW4Yffhtfr6QR95+NTEJ c+BqVKOSJee/v7ggXhSJXMae2QHGlYzzJvVnmvhgalT62zqfTjmFw6wFA peszpYVYVUFkr1kc5rDcWephHM7HMGmOl0hyQ3rB1WFPxMokXkwl6ceLz 8tt4lndBjat7sc7LEGHxkVG1JNrUJ7enb5C9e4qRY/Y5hubgJU+L93YOL woSILsw+7gaiMT1oRhdsbQoGq/IkndZbl17fEtggyudYAMsOJlnRjNHbg A==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="147642347" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:34:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:58 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:56 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 6/7] clocksource/drivers/timer-microchip-pit64b: use mchp_pit64b_{suspend, resume} Date: Tue, 1 Mar 2022 14:34:48 +0200 Message-ID: <20220301123449.2816625-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 24 ++++---------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index b51259395ac3..f50705698283 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -344,6 +344,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, if (!cs) return -ENOMEM; =20 + mchp_pit64b_resume(timer); mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); =20 mchp_pit64b_cs_base =3D timer->base; @@ -365,8 +366,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); =20 /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); + mchp_pit64b_suspend(timer); kfree(cs); =20 return ret; @@ -450,19 +450,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, if (ret) goto irq_unmap; =20 - ret =3D clk_prepare_enable(timer.pclk); - if (ret) - goto irq_unmap; - - if (timer.mode & MCHP_PIT64B_MR_SGCLK) { - ret =3D clk_prepare_enable(timer.gclk); - if (ret) - goto pclk_unprepare; - + if (timer.mode & MCHP_PIT64B_MR_SGCLK) clk_rate =3D clk_get_rate(timer.gclk); - } else { + else clk_rate =3D clk_get_rate(timer.pclk); - } clk_rate =3D clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); =20 if (clkevt) @@ -471,15 +462,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, ret =3D mchp_pit64b_init_clksrc(&timer, clk_rate); =20 if (ret) - goto gclk_unprepare; + goto irq_unmap; =20 return 0; =20 -gclk_unprepare: - if (timer.mode & MCHP_PIT64B_MR_SGCLK) - clk_disable_unprepare(timer.gclk); -pclk_unprepare: - clk_disable_unprepare(timer.pclk); irq_unmap: irq_dispose_mapping(irq); io_unmap: --=20 2.32.0 From nobody Tue Jun 23 17:22:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94CEAC433EF for ; Tue, 1 Mar 2022 12:34:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234837AbiCAMe6 (ORCPT ); Tue, 1 Mar 2022 07:34:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234794AbiCAMem (ORCPT ); Tue, 1 Mar 2022 07:34:42 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6ECA97BB7 for ; Tue, 1 Mar 2022 04:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646138040; x=1677674040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YvuB2Ay0dLnc800oXNRcutbEZNg7vLBu/3a/pjG1aOE=; b=izTfY8YgQUGuzaw636wp/15i7p/ByI4S1ca1YF5Vxib+4DoN91YVRott baF10rvuwkI17htv4v9Dl587QqO31Rr5Lieb2HJ29eSNGTdM5TXvOG+jK fljMcvebFc7bp9rR3ZQNLgCDIMwgSycPAkmqQtcYb+fl40jqVqfh4MfNT cEVLLpfvpsN95Il1v6CpelBgtrbqaun8USibUpt0VM8tSGaHG8h10kYjA Pb4FCKaUdXT8C4hRELIcPzUeRIuut5oolgMggem9ay4yEexgzErKlkSDF 7waUj4n/k3iq0trhfU5XqRCS7w4h99BTwODA5u3+tgEoOO6PhMgSKdWfi g==; X-IronPort-AV: E=Sophos;i="5.90,146,1643698800"; d="scan'208";a="155253494" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Mar 2022 05:34:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 1 Mar 2022 05:33:59 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 1 Mar 2022 05:33:58 -0700 From: Claudiu Beznea To: , CC: , , Claudiu Beznea Subject: [PATCH 7/7] clocksource/drivers/timer-microchip-pit64b: fix compilation warnings Date: Tue, 1 Mar 2022 14:34:49 +0200 Message-ID: <20220301123449.2816625-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220301123449.2816625-1-claudiu.beznea@microchip.com> References: <20220301123449.2816625-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following compilation warnings: timer-microchip-pit64b.c:68: warning: cannot understand function prototype:= 'struct mchp_pit64b_clkevt ' timer-microchip-pit64b.c:82: warning: cannot understand function prototype:= 'struct mchp_pit64b_clksrc ' timer-microchip-pit64b.c:283: warning: Function parameter or member 'timer'= not described in 'mchp_pit64b_init_mode' timer-microchip-pit64b.c:283: warning: Function parameter or member 'max_ra= te' not described in 'mchp_pit64b_init_mode' Signed-off-by: Claudiu Beznea --- drivers/clocksource/timer-microchip-pit64b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index f50705698283..5ce206723700 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -46,7 +46,7 @@ =20 #define MCHP_PIT64B_NAME "pit64b" =20 -/** +/* * struct mchp_pit64b_timer - PIT64B timer data structure * @base: base address of PIT64B hardware block * @pclk: PIT64B's peripheral clock @@ -60,7 +60,7 @@ struct mchp_pit64b_timer { u32 mode; }; =20 -/** +/* * mchp_pit64b_clkevt - PIT64B clockevent data structure * @timer: PIT64B timer * @clkevt: clockevent @@ -74,7 +74,7 @@ struct mchp_pit64b_clkevt { ((struct mchp_pit64b_timer *)container_of(x,\ struct mchp_pit64b_clkevt, clkevt)) =20 -/** +/* * mchp_pit64b_clksrc - PIT64B clocksource data structure * @timer: PIT64B timer * @clksrc: clocksource @@ -244,7 +244,7 @@ static void __init mchp_pit64b_pres_compute(u32 *pres, = u32 clk_rate, *pres =3D MCHP_PIT64B_PRES_MAX - 1; } =20 -/** +/* * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at * runtime; this includes prescaler and SGCLK bit * --=20 2.32.0