From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6664DC433F5 for ; Tue, 1 Mar 2022 04:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231758AbiCAE3B (ORCPT ); Mon, 28 Feb 2022 23:29:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230125AbiCAE26 (ORCPT ); Mon, 28 Feb 2022 23:28:58 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE6744B1F7 for ; Mon, 28 Feb 2022 20:28:17 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id d17so18433336wrc.9 for ; Mon, 28 Feb 2022 20:28:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FXY/vIDKe6DGMfSlwt+/9lV29k2hg5m2ZOntq1vLjB8=; b=YbnXH3Ozn3b9HuBAgiYG8VYMa0eOjwf/1cC77kCVzifGNvBgFVcGkgDMYeYYXRH8KX es6Pci779Tb3Cls9xAqKDX7GugD/Dsd0qxsy1LhmQWF/bbrE8sLledQ46d/t+kJLM2h0 2nmhVFLz2WzopUZldR98pJSf/E8XpEbqU48o35VqiBNyAyxKX2DN3GSu0MMBnvkRciC/ O1IwurKtAWLHLohAVHuabupg3Ft23YKFTT8vUUIwDPmZTFyiRoY6XHjAEbOmT27Df7Bw gFWwGDuJ/qUEX+T6jMQDGDhAN8v10v8UUjwEqgGcdip8k1mxrmdUrLi+barpR2/V09sJ 1Zvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FXY/vIDKe6DGMfSlwt+/9lV29k2hg5m2ZOntq1vLjB8=; b=tvB/e2CSsbCB49v+6byxgkL6jAyV+d9HgMEjHIDnRNfvzR/m4Sk3CyVhT1+o8RRiVF 50ivBXAVtryrTPg82RG9ZKyzVn3mYIjDqg2KXJz0gjgUSk7wdMwCSRnFJmuREDzqKzFj PfcB2JiMEnyp0buxHuZVq7438IogSsjxLx8tXPyB594/RNuQDLEsWAkF3pgJ2g9LXITa 0QALt4nv84mjvK2R4T3U8w+640ib7oKT66kcMfBov5RSheDpCkyv4SkvgyA2vmqdssS+ ySCXfRMD3HaWa+8YwkNzQQ3qnLVvx+FLmyrQddQ0HxQxehxLjHr2Ck7niMj6kjHRgg3E s2IQ== X-Gm-Message-State: AOAM531zlZX3Ib1rQZoW7a3XcIIBGQVMYQS2cWNXVFAQz3z9vY/vWwvF gTakZHdmcF/4uzl/46++5BqaYQ== X-Google-Smtp-Source: ABdhPJyDCf0PIM7Cz+LWsyEXEFiULxZskjWLp/zzvJEeRGlDKz00FVkpH24DcxMgGallV6oJWtBFeQ== X-Received: by 2002:a05:6000:11c8:b0:1f0:d64:fb0c with SMTP id i8-20020a05600011c800b001f00d64fb0cmr908247wrx.279.1646108896435; Mon, 28 Feb 2022 20:28:16 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:16 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Bin Meng Subject: [PATCH v4 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations Date: Tue, 1 Mar 2022 09:57:17 +0530 Message-Id: <20220301042722.401113-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The software interrupt pending (i.e. [M|S]SIP) bit is writeable for S-mode but read-only for M-mode so we clear this bit only when using SBI IPI operations. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/kernel/sbi.c | 8 +++++++- arch/riscv/kernel/smp.c | 2 -- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 775d3322b422..fc614650a2e3 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -643,8 +643,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask = *target) sbi_send_ipi(target); } =20 +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi + .ipi_inject =3D sbi_send_cpumask_ipi, + .ipi_clear =3D sbi_ipi_clear }; =20 void __init sbi_init(void) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..6fd8b3cbec1b 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,8 +89,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); =20 --=20 2.25.1 From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54E67C433EF for ; Tue, 1 Mar 2022 04:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232249AbiCAE3M (ORCPT ); Mon, 28 Feb 2022 23:29:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232234AbiCAE3E (ORCPT ); Mon, 28 Feb 2022 23:29:04 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C66664D603 for ; Mon, 28 Feb 2022 20:28:23 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id r10so18492770wrp.3 for ; Mon, 28 Feb 2022 20:28:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=gICFhfXwhzyyNd8ShrN+bR6Dsqj0G3mNRAF7sZYOqYvRpt1pKzUu2i3kkHbs8EpcOi 302J3CGLqIXfo7y6Y0X3w3TDZo3G47e3xUwdCJ4Uwt7rRpvF0Lbv3xgaBnXQ4W052WYr 8RmP6cqbsgFKqr4uex3kaWuS8vR2aIqIvRdwviUu5OvbI8opqcdmxciqmdPZZY35vj3M 9oqB927UAnmrmmNk96cvwrV0UXS9aBFOMU5Ksx8Ah1QkbzxIkAxbST7HfdwFvYJkTDDq KBg2TLDvzAy+mJ7covd9cwKzIFBu6LISZtDrRqWHrfMs1R+IRcwdvWa/TW2xu1ZVccwY T9eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=kIZgUvPpP4VCyTOeAMBLhLoD04a8N9RcyEu/45dcz/IEHtI8xFinBQ5wVsgOR1uDjM JqJKJtltJw6ni2OB8RUwa1SuWDFkr0jnE6soaKl2YGn50b4GDDneKpdrqt0aRnsSaZPB TQ8/cA1WdyV/pXmzwRGJbmtmCwgk6LnxcyL1F5W6EjQty/xvPioLuCbEMHZjYRuN0PPR CsuHP/ue7JmyoFnZLQT8F+KWzoljGQ104hO2YRjshdkgf9N8oJETMS6BrHIwSo9RG7nB 3KtIRj0PwZJz2UFbPraSrkHP5xoUI4PKgAjsQgIl9yKJxeAsyrp/9ir9SZgWXM9k6Qnf syVQ== X-Gm-Message-State: AOAM530wJ3sBbXYdG7tUMGC47Hkv+DoDeYHrPEP6vMHYzbuZ/Zy5R7Ad NhTv6GbrUNelDDE3p9scPhLPDg== X-Google-Smtp-Source: ABdhPJwikeYsvr36/wo02SUnizlvf5YsP2mjv2VqHzKmNLWhmjMbi7FTYI122m8IP+Ghb1FvKXyNPw== X-Received: by 2002:a05:6000:1cb:b0:1ed:c295:3e3b with SMTP id t11-20020a05600001cb00b001edc2953e3bmr18605303wrx.111.1646108901887; Mon, 28 Feb 2022 20:28:21 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:21 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 2/6] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Tue, 1 Mar 2022 09:57:18 +0530 Message-Id: <20220301042722.401113-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ =20 #include =20 +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node =3D fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index b65bd8878d4f..084793a57af8 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops= =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -125,6 +130,8 @@ static int __init riscv_intc_init(struct device_node *n= ode, return rc; } =20 + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, --=20 2.25.1 From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E15BC433EF for ; Tue, 1 Mar 2022 04:28:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbiCAE3U (ORCPT ); Mon, 28 Feb 2022 23:29:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232280AbiCAE3K (ORCPT ); Mon, 28 Feb 2022 23:29:10 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03C154DF6D for ; Mon, 28 Feb 2022 20:28:29 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id d3so18503283wrf.1 for ; Mon, 28 Feb 2022 20:28:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8F9RQiw9SFGNdqknO7Pbqv6uC/+3poM4SniibT95aP4=; b=U4+BPOS/177h0GFa2zL41uf8c+Q+oMorjDOSyHonAP38l9hSwq9iRVgmN38M6Y+PSz B5s7pbbeyqGBS0RD+VDoHXZdH643Lixolc9xLRjQ16AwKmMjR5njoQKXVVoEpwrTXQwb 03OO3fXf+SmVQG9Xsoz7EACJ1pnfjh7oqxTRR2iXQuAg7bLxmAzqodZPLojsvIju7MVx jXY8JXp526lBOKyFCPXm+a1r+9BTJ9BCDof6P4mJkq2OMN0RbiZr2BGG902jtNpl48Zd JCaIqAxWonblocLnRFHZ1xcM5AjYYpqT8NBdHF/4Tz5GGZM03P/dzYZVz4COoIe1k3r9 TETg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8F9RQiw9SFGNdqknO7Pbqv6uC/+3poM4SniibT95aP4=; b=TeOVPBFTjVesw+rVSoRYsjUsbZ77nwqzkHFREZ0zc0KzuY8f72MNti4Z5cf1qJRNn+ xsBmhddaopgG4y67gJZ26z9JqdwRjJcdBzNw1LX33A7e+QuwfyUNrNE6UlQn9FsD7X1R S9teEDaqnUgnit85aTObIK66C3xbNetshaGtU6d8fxtk8bc52V7/ofiRp/VGAXN8a7es /lo+tFi1U7xrEhk3I348PazKz3v0XRCNtZlqhl7yh/cnBkR/MQWzDBOEPf/+s5LEHOuo FTbUt6WGWTTDrDGqONdAnfeKz+pMPRC5Eo+/j/YhRpPRNQZsKnC1+Xaj/3+SIIlAV05i fhHQ== X-Gm-Message-State: AOAM533Z1XrTQaoj166Zc2i3GRlsC8J5fEABfYcq4U++AUQAj63Q3QwY QC10TlIL1VmGYuXibOi7dhLd5Q== X-Google-Smtp-Source: ABdhPJz5M3W2RA8UZU0TQhrDlcH0Dx7tXSr5vWs25Ue+DBhlE6sPyYBWABtgNkjW+dknZSNMm+PXkw== X-Received: by 2002:adf:c50b:0:b0:1ef:7a8c:bef2 with SMTP id q11-20020adfc50b000000b001ef7a8cbef2mr12521774wrf.177.1646108907425; Mon, 28 Feb 2022 20:28:27 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:27 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 3/6] RISC-V: Treat IPIs as normal Linux IRQs Date: Tue, 1 Mar 2022 09:57:19 +0530 Message-Id: <20220301042722.401113-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the RISC-V kernel provides arch specific hooks (i.e. struct riscv_ipi_ops) to register IPI handling methods. The stats gathering of IPIs is also arch specific in the RISC-V kernel. Other architectures (such as ARM, ARM64, and MIPS) have moved away from custom arch specific IPI handling methods. Currently, these architectures have Linux irqchip drivers providing a range of Linux IRQ numbers to be used as IPIs and IPI triggering is done using generic IPI APIs. This approach allows architectures to treat IPIs as normal Linux IRQs and IPI stats gathering is done by the generic Linux IRQ subsystem. We extend the RISC-V IPI handling as-per above approach so that arch specific IPI handling methods (struct riscv_ipi_ops) can be removed and the IPI handling is done through the Linux IRQ subsystem. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/ipi-mux.h | 43 ++++++ arch/riscv/include/asm/sbi.h | 2 + arch/riscv/include/asm/smp.h | 35 +++-- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/ipi-mux.c | 222 ++++++++++++++++++++++++++++++ arch/riscv/kernel/irq.c | 3 +- arch/riscv/kernel/sbi.c | 13 +- arch/riscv/kernel/smp.c | 153 ++++++++++---------- arch/riscv/kernel/smpboot.c | 5 +- drivers/clocksource/timer-clint.c | 8 +- drivers/irqchip/irq-riscv-intc.c | 55 ++++---- 13 files changed, 405 insertions(+), 139 deletions(-) create mode 100644 arch/riscv/include/asm/ipi-mux.h create mode 100644 arch/riscv/kernel/ipi-mux.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5adcbd9b5e88..167681d6d3f8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -54,6 +54,7 @@ config RISCV select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP if MMU + select GENERIC_IRQ_IPI select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-= mux.h new file mode 100644 index 000000000000..988e2bba372a --- /dev/null +++ b/arch/riscv/include/asm/ipi-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#ifndef _ASM_RISCV_IPI_MUX_H +#define _ASM_RISCV_IPI_MUX_H + +struct cpumask; + +#ifdef CONFIG_SMP + +/* Handle muxed IPIs */ +void riscv_ipi_mux_handle_irq(void); + +/* Create irq_domain for muxed IPIs */ +struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)); + +/* Destroy irq_domain for muxed IPIs */ +void riscv_ipi_mux_destroy(struct irq_domain *d); + +#else + +static inline void riscv_ipi_mux_handle_irq(void) +{ +} + +static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)) +{ + return NULL; +} + +static inline void riscv_ipi_mux_destroy(struct irq_domain *d) +{ +} + +#endif + +#endif /* _ASM_RISCV_IPI_MUX_H */ diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 06133b4f8e20..edd2c3135b4a 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -133,6 +133,7 @@ struct sbiret { }; =20 void sbi_init(void); +void sbi_ipi_init(void); struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, @@ -202,6 +203,7 @@ static inline unsigned long sbi_mk_version(unsigned lon= g major, int sbi_err_map_linux_errno(int err); #else /* CONFIG_RISCV_SBI */ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { ret= urn -1; } +static inline void sbi_ipi_init(void) { } static inline void sbi_init(void) {} #endif /* CONFIG_RISCV_SBI */ #endif /* _ASM_RISCV_SBI_H */ diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..178fe4ada592 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -15,11 +15,6 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 -struct riscv_ipi_ops { - void (*ipi_inject)(const struct cpumask *target); - void (*ipi_clear)(void); -}; - #ifdef CONFIG_SMP /* * Mapping between linux logical cpu index and hartid. @@ -33,9 +28,6 @@ void show_ipi_stats(struct seq_file *p, int prec); /* SMP initialization hook for setup_arch */ void __init setup_smp(void); =20 -/* Called from C code, this handles an IPI. */ -void handle_IPI(struct pt_regs *regs); - /* Hook for the generic smp_call_function_many() routine. */ void arch_send_call_function_ipi_mask(struct cpumask *mask); =20 @@ -44,11 +36,17 @@ void arch_send_call_function_single_ipi(int cpu); =20 int riscv_hartid_to_cpuid(int hartid); =20 -/* Set custom IPI operations */ -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); +/* Enable IPI for CPU hotplug */ +void riscv_ipi_enable(void); + +/* Disable IPI for CPU hotplug */ +void riscv_ipi_disable(void); =20 -/* Clear IPI for current CPU */ -void riscv_clear_ipi(void); +/* Check if IPI interrupt numbers are available */ +bool riscv_ipi_have_virq_range(void); + +/* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ +void riscv_ipi_set_virq_range(int virq, int nr_irqs); =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -82,11 +80,20 @@ static inline unsigned long cpuid_to_hartid_map(int cpu) return boot_cpu_hartid; } =20 -static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) +static inline void riscv_ipi_enable(void) { } =20 -static inline void riscv_clear_ipi(void) +static inline void riscv_ipi_disable(void) +{ +} + +static inline bool riscv_ipi_have_virq_range(void) +{ + return false; +} + +static inline void riscv_ipi_set_virq_range(int virq, int nr) { } =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index ffc87e76b1dd..5047723e5527 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o +obj-$(CONFIG_SMP) +=3D ipi-mux.o obj-$(CONFIG_SMP) +=3D cpu_ops.o =20 obj-$(CONFIG_RISCV_BOOT_SPINWAIT) +=3D cpu_ops_spinwait.o diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplu= g.c index f7a832e3a1d1..39235cf50652 100644 --- a/arch/riscv/kernel/cpu-hotplug.c +++ b/arch/riscv/kernel/cpu-hotplug.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include =20 bool cpu_has_hotplug(unsigned int cpu) { @@ -43,6 +43,7 @@ int __cpu_disable(void) remove_cpu_topology(cpu); numa_remove_cpu(cpu); set_cpu_online(cpu, false); + riscv_ipi_disable(); irq_migrate_all_off_this_cpu(); =20 return ret; diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c new file mode 100644 index 000000000000..3a0405f0e0de --- /dev/null +++ b/arch/riscv/kernel/ipi-mux.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Multiplex several IPIs over a single HW IPI. + * + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-ipi-mux: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ipi_mux { + struct irq_domain *domain; + int parent_virq; + void (*clear_ipi)(void); + void (*send_ipi)(const struct cpumask *mask); +}; + +static struct ipi_mux ipi_mux_priv; +static DEFINE_PER_CPU(unsigned long, ipi_mux_bits); + +static void ipi_mux_dummy(struct irq_data *d) +{ +} + +static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *ma= sk) +{ + int cpu; + + /* Barrier before doing atomic bit update to IPI bits */ + smp_mb__before_atomic(); + + for_each_cpu(cpu, mask) + set_bit(d->hwirq, per_cpu_ptr(&ipi_mux_bits, cpu)); + + /* Barrier after doing atomic bit update to IPI bits */ + smp_mb__after_atomic(); + + if (ipi_mux_priv.send_ipi) + ipi_mux_priv.send_ipi(mask); +} + +static struct irq_chip ipi_mux_chip =3D { + .name =3D "RISC-V IPI Mux", + .irq_mask =3D ipi_mux_dummy, + .irq_unmask =3D ipi_mux_dummy, + .ipi_send_mask =3D ipi_mux_send_mask, +}; + +static int ipi_mux_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_percpu_devid(irq); + irq_domain_set_info(d, irq, hwirq, &ipi_mux_chip, d->host_data, + handle_percpu_devid_irq, NULL, NULL); + + return 0; +} + +static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + + ret =3D irq_domain_translate_onecell(d, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D ipi_mux_domain_map(d, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + +static const struct irq_domain_ops ipi_mux_domain_ops =3D { + .translate =3D irq_domain_translate_onecell, + .alloc =3D ipi_mux_domain_alloc, + .free =3D irq_domain_free_irqs_top, +}; + +void riscv_ipi_mux_handle_irq(void) +{ + int err; + unsigned long irqs, *bits =3D this_cpu_ptr(&ipi_mux_bits); + irq_hw_number_t hwirq; + + while (true) { + if (ipi_mux_priv.clear_ipi) + ipi_mux_priv.clear_ipi(); + + /* Order bit clearing and data access. */ + mb(); + + irqs =3D xchg(bits, 0); + if (!irqs) + break; + + for_each_set_bit(hwirq, &irqs, BITS_PER_LONG) { + err =3D generic_handle_domain_irq(ipi_mux_priv.domain, + hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "can't find mapping for hwirq %lu\n", + hwirq); + } + } +} + +static void ipi_mux_handle_irq(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + riscv_ipi_mux_handle_irq(); + chained_irq_exit(chip, desc); +} + +static int ipi_mux_dying_cpu(unsigned int cpu) +{ + if (ipi_mux_priv.parent_virq) + disable_percpu_irq(ipi_mux_priv.parent_virq); + return 0; +} + +static int ipi_mux_starting_cpu(unsigned int cpu) +{ + if (ipi_mux_priv.parent_virq) + enable_percpu_irq(ipi_mux_priv.parent_virq, + irq_get_trigger_type(ipi_mux_priv.parent_virq)); + return 0; +} + +struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + void (*clear_ipi)(void), + void (*send_ipi)(const struct cpumask *mask)) +{ + int virq, parent_virq =3D 0; + struct irq_domain *domain; + struct irq_fwspec ipi; + + if (ipi_mux_priv.domain || riscv_ipi_have_virq_range()) + return NULL; + + if (use_soft_irq) { + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("unable to find INTC IRQ domain\n"); + return NULL; + } + + parent_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!parent_virq) { + pr_err("unable to create INTC IRQ mapping\n"); + return NULL; + } + } + + domain =3D irq_domain_add_linear(NULL, BITS_PER_LONG, + &ipi_mux_domain_ops, NULL); + if (!domain) { + pr_err("unable to add IPI Mux domain\n"); + goto fail_dispose_mapping; + } + + ipi.fwnode =3D domain->fwnode; + ipi.param_count =3D 1; + ipi.param[0] =3D 0; + virq =3D __irq_domain_alloc_irqs(domain, -1, BITS_PER_LONG, + NUMA_NO_NODE, &ipi, false, NULL); + if (virq <=3D 0) { + pr_err("unable to alloc IRQs from IPI Mux domain\n"); + goto fail_domain_remove; + } + + ipi_mux_priv.domain =3D domain; + ipi_mux_priv.parent_virq =3D parent_virq; + ipi_mux_priv.clear_ipi =3D clear_ipi; + ipi_mux_priv.send_ipi =3D send_ipi; + + if (parent_virq) + irq_set_chained_handler(parent_virq, ipi_mux_handle_irq); + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/ipi-mux:starting", + ipi_mux_starting_cpu, ipi_mux_dying_cpu); + + riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + + return ipi_mux_priv.domain; + +fail_domain_remove: + irq_domain_remove(domain); +fail_dispose_mapping: + if (parent_virq) + irq_dispose_mapping(parent_virq); + return NULL; +} + +void riscv_ipi_mux_destroy(struct irq_domain *d) +{ + if (!d || ipi_mux_priv.domain !=3D d) + return; + + irq_domain_remove(ipi_mux_priv.domain); + if (ipi_mux_priv.parent_virq) + irq_dispose_mapping(ipi_mux_priv.parent_virq); + memset(&ipi_mux_priv, 0, sizeof(ipi_mux_priv)); +} diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 96d3171f0ca1..eb9a68a539e6 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include =20 static struct fwnode_handle *(*__get_intc_node)(void); =20 @@ -39,4 +39,5 @@ void __init init_IRQ(void) irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); + sbi_ipi_init(); } diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index fc614650a2e3..ab38814f1977 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -5,10 +5,12 @@ * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ =20 +#define pr_fmt(fmt) "riscv: " fmt #include #include #include #include +#include #include #include =20 @@ -648,10 +650,11 @@ static void sbi_ipi_clear(void) csr_clear(CSR_IP, IE_SIE); } =20 -static const struct riscv_ipi_ops sbi_ipi_ops =3D { - .ipi_inject =3D sbi_send_cpumask_ipi, - .ipi_clear =3D sbi_ipi_clear -}; +void __init sbi_ipi_init(void) +{ + if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + pr_info("providing IPIs using SBI IPI extension\n"); +} =20 void __init sbi_init(void) { @@ -699,6 +702,4 @@ void __init sbi_init(void) __sbi_send_ipi =3D __sbi_send_ipi_v01; __sbi_rfence =3D __sbi_rfence_v01; } - - riscv_set_ipi_ops(&sbi_ipi_ops); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 6fd8b3cbec1b..a9f1aca38358 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -17,9 +17,9 @@ #include #include #include +#include #include =20 -#include #include #include =20 @@ -41,11 +41,9 @@ void __init smp_setup_processor_id(void) cpuid_to_hartid_map(0) =3D boot_cpu_hartid; } =20 -/* A collection of single bit ipi messages. */ -static struct { - unsigned long stats[IPI_MAX] ____cacheline_aligned; - unsigned long bits ____cacheline_aligned; -} ipi_data[NR_CPUS] __cacheline_aligned; +static int ipi_virq_base __ro_after_init; +static int nr_ipi __ro_after_init =3D IPI_MAX; +static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly; =20 int riscv_hartid_to_cpuid(int hartid) { @@ -77,46 +75,14 @@ static void ipi_stop(void) wait_for_interrupt(); } =20 -static const struct riscv_ipi_ops *ipi_ops __ro_after_init; - -void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) -{ - ipi_ops =3D ops; -} -EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); - -void riscv_clear_ipi(void) -{ - if (ipi_ops && ipi_ops->ipi_clear) - ipi_ops->ipi_clear(); -} -EXPORT_SYMBOL_GPL(riscv_clear_ipi); - static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_typ= e op) { - int cpu; - - smp_mb__before_atomic(); - for_each_cpu(cpu, mask) - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(mask); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], mask); } =20 static void send_ipi_single(int cpu, enum ipi_message_type op) { - smp_mb__before_atomic(); - set_bit(op, &ipi_data[cpu].bits); - smp_mb__after_atomic(); - - if (ipi_ops && ipi_ops->ipi_inject) - ipi_ops->ipi_inject(cpumask_of(cpu)); - else - pr_warn("SMP: IPI inject method not available\n"); + __ipi_send_mask(ipi_desc[op], cpumask_of(cpu)); } =20 #ifdef CONFIG_IRQ_WORK @@ -126,55 +92,88 @@ void arch_irq_work_raise(void) } #endif =20 -void handle_IPI(struct pt_regs *regs) +static irqreturn_t handle_IPI(int irq, void *data) +{ + int ipi =3D irq - ipi_virq_base; + + switch (ipi) { + case IPI_RESCHEDULE: + scheduler_ipi(); + break; + case IPI_CALL_FUNC: + generic_smp_call_function_interrupt(); + break; + case IPI_CPU_STOP: + ipi_stop(); + break; + case IPI_IRQ_WORK: + irq_work_run(); + break; +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + case IPI_TIMER: + tick_receive_broadcast(); + break; +#endif + default: + pr_warn("CPU%d: unhandled IPI%d\n", smp_processor_id(), ipi); + break; + }; + + return IRQ_HANDLED; +} + +void riscv_ipi_enable(void) { - unsigned long *pending_ipis =3D &ipi_data[smp_processor_id()].bits; - unsigned long *stats =3D ipi_data[smp_processor_id()].stats; + int i; =20 - riscv_clear_ipi(); + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - while (true) { - unsigned long ops; + for (i =3D 0; i < nr_ipi; i++) + enable_percpu_irq(ipi_virq_base + i, 0); +} =20 - /* Order bit clearing and data access. */ - mb(); +void riscv_ipi_disable(void) +{ + int i; =20 - ops =3D xchg(pending_ipis, 0); - if (ops =3D=3D 0) - return; + if (WARN_ON_ONCE(!ipi_virq_base)) + return; =20 - if (ops & (1 << IPI_RESCHEDULE)) { - stats[IPI_RESCHEDULE]++; - scheduler_ipi(); - } + for (i =3D 0; i < nr_ipi; i++) + disable_percpu_irq(ipi_virq_base + i); +} =20 - if (ops & (1 << IPI_CALL_FUNC)) { - stats[IPI_CALL_FUNC]++; - generic_smp_call_function_interrupt(); - } +bool riscv_ipi_have_virq_range(void) +{ + return (ipi_virq_base) ? true : false; +} =20 - if (ops & (1 << IPI_CPU_STOP)) { - stats[IPI_CPU_STOP]++; - ipi_stop(); - } +void riscv_ipi_set_virq_range(int virq, int nr) +{ + int i, err; =20 - if (ops & (1 << IPI_IRQ_WORK)) { - stats[IPI_IRQ_WORK]++; - irq_work_run(); - } + if (WARN_ON(ipi_virq_base)) + return; =20 -#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST - if (ops & (1 << IPI_TIMER)) { - stats[IPI_TIMER]++; - tick_receive_broadcast(); - } -#endif - BUG_ON((ops >> IPI_MAX) !=3D 0); + WARN_ON(nr < IPI_MAX); + nr_ipi =3D min(nr, IPI_MAX); + ipi_virq_base =3D virq; + + /* Request IPIs */ + for (i =3D 0; i < nr_ipi; i++) { + err =3D request_percpu_irq(ipi_virq_base + i, handle_IPI, + "IPI", &ipi_virq_base); + WARN_ON(err); =20 - /* Order data access and bit testing. */ - mb(); + ipi_desc[i] =3D irq_to_desc(ipi_virq_base + i); + irq_set_status_flags(ipi_virq_base + i, IRQ_HIDDEN); } + + /* Enabled IPIs for boot CPU immediately */ + riscv_ipi_enable(); } +EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 static const char * const ipi_names[] =3D { [IPI_RESCHEDULE] =3D "Rescheduling interrupts", @@ -192,7 +191,7 @@ void show_ipi_stats(struct seq_file *p, int prec) seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >=3D 4 ? " " : ""); for_each_online_cpu(cpu) - seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); + seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); seq_printf(p, " %s\n", ipi_names[i]); } } diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..e37036e779bb 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include =20 @@ -159,12 +158,12 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 - riscv_clear_ipi(); - /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm =3D mm; =20 + riscv_ipi_enable(); + notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); update_siblings_masks(curr_cpuid); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 6cfe2ab73eb0..b05a9e946633 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #ifndef CONFIG_RISCV_M_MODE #include @@ -54,11 +55,6 @@ static void clint_clear_ipi(void) writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); } =20 -static struct riscv_ipi_ops clint_ipi_ops =3D { - .ipi_inject =3D clint_send_ipi, - .ipi_clear =3D clint_clear_ipi, -}; - #ifdef CONFIG_64BIT #define clint_get_cycles() readq_relaxed(clint_timer_val) #else @@ -228,7 +224,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_free_irq; } =20 - riscv_set_ipi_ops(&clint_ipi_ops); + riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); =20 return 0; diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 084793a57af8..6ab688e54bc1 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,7 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) if (unlikely(cause >=3D BITS_PER_LONG)) panic("unexpected interrupt cause"); =20 - switch (cause) { -#ifdef CONFIG_SMP - case RV_IRQ_SOFT: - /* - * We only use software interrupts to pass IPIs, so if a - * non-SMP system gets one, then we don't know what to do. - */ - handle_IPI(regs); - break; -#endif - default: - generic_handle_domain_irq(intc_domain, cause); - break; - } + generic_handle_domain_irq(intc_domain, cause); } =20 /* @@ -59,18 +46,6 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 -static int riscv_intc_cpu_starting(unsigned int cpu) -{ - csr_set(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - -static int riscv_intc_cpu_dying(unsigned int cpu) -{ - csr_clear(CSR_IE, BIT(RV_IRQ_SOFT)); - return 0; -} - static struct irq_chip riscv_intc_chip =3D { .name =3D "RISC-V INTC", .irq_mask =3D riscv_intc_irq_mask, @@ -87,9 +62,32 @@ static int riscv_intc_domain_map(struct irq_domain *d, u= nsigned int irq, return 0; } =20 +static int riscv_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + + ret =3D irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D riscv_intc_domain_map(domain, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + static const struct irq_domain_ops riscv_intc_domain_ops =3D { .map =3D riscv_intc_domain_map, .xlate =3D irq_domain_xlate_onecell, + .alloc =3D riscv_intc_domain_alloc }; =20 static struct fwnode_handle *riscv_intc_hwnode(void) @@ -132,11 +130,6 @@ static int __init riscv_intc_init(struct device_node *= node, =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, - "irqchip/riscv/intc:starting", - riscv_intc_cpu_starting, - riscv_intc_cpu_dying); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); =20 return 0; --=20 2.25.1 From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F5DC433EF for ; Tue, 1 Mar 2022 04:28:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232270AbiCAE3Y (ORCPT ); Mon, 28 Feb 2022 23:29:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232234AbiCAE3O (ORCPT ); Mon, 28 Feb 2022 23:29:14 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 109084C436 for ; Mon, 28 Feb 2022 20:28:34 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id i8so1394926wrr.8 for ; Mon, 28 Feb 2022 20:28:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1dvQpmktLMIBE5zILdeneM+K/jB6oDBX0KNz7QqesMQ=; b=UWot9+IKQnkBxOtBKqZCFbkzbWwkiSYSfH29Vs+HVQmBV1nMtXjntkuPvnTiu8eSHh MOIIomRS+JqYe4IABr2l85Ba6VB0HNhcMraLbyGKhSieqJnEPIS/U4sfEl8qcl0ulKSr neIYpYd2OLJBT4hb8tDmj2iQfHJHEpzniPxQOuXjEybdumghKw4Kd4rQ0SABJuwUbGY/ FH7lATW7s2OIt6+WaP+DVHKz7GMEpfC0mNu8Iqi5CO+rxu8gNWNXtx24317USXhFpbRl QU3B78v1AwaLevpkKehqtsiYWv59HQWSZY2G2sj0mngemRM00d1XdIr98WAsKSinhdlg SnzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1dvQpmktLMIBE5zILdeneM+K/jB6oDBX0KNz7QqesMQ=; b=v8KKTu1TU8HSJ+QrDB7/j69HXQP99bGAdzHxxAosagMHuBSTilbxWUBW3W6sh/RJT2 2s3N3EZLF5tz5tlTO3A8hbdUAOBpBdlyTYSLmVrE77geTe0nyFHePvagiZoEITm1CWGm NHUCnmWq4zoBWeyJOJNjmBIu+GZTYheNveLivKkxPyC0ZqAgFUhFSD+IdnNT4Am/UwsZ n9cp1S74ykLT+e8GqCXbhkBPNp6C15sWTTegToaE5jkgo7e5lhiFMGx5CFb74FioIted YUlXUL3auf+6TtIxXP6swi+LdYiCf80xmbk8Oj4+8NZimWC2otA6Xr4yaeuFX9NEJETB 5jBw== X-Gm-Message-State: AOAM531NAzsn/gqidLvOh6H9BzwYlgMWdaIWc38JI+QK24+d0SZ+Q8If tb9gPzn67SQq7oGBZxA/9ReRSg== X-Google-Smtp-Source: ABdhPJyPsI1+Nu7GMUXFm/RS4F+v/3R0bi19Km9ReWOA5RisVE1tZPvaeeJkRQA8w9mZHqSeRvMpHQ== X-Received: by 2002:adf:cd0a:0:b0:1ed:e0b3:428 with SMTP id w10-20020adfcd0a000000b001ede0b30428mr17792226wrm.357.1646108912581; Mon, 28 Feb 2022 20:28:32 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:32 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Tue, 1 Mar 2022 09:57:20 +0530 Message-Id: <20220301042722.401113-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/include/asm/ipi-mux.h | 2 ++ arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/ipi-mux.c | 3 ++- arch/riscv/kernel/sbi.c | 3 ++- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-= mux.h index 988e2bba372a..3a5acbf51806 100644 --- a/arch/riscv/include/asm/ipi-mux.h +++ b/arch/riscv/include/asm/ipi-mux.h @@ -15,6 +15,7 @@ void riscv_ipi_mux_handle_irq(void); =20 /* Create irq_domain for muxed IPIs */ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)); =20 @@ -28,6 +29,7 @@ static inline void riscv_ipi_mux_handle_irq(void) } =20 static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 178fe4ada592..ddd3be1c77b6 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; =20 #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); =20 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr_irqs); +void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) =20 /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } =20 -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } =20 +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c index 3a0405f0e0de..544074ea3ead 100644 --- a/arch/riscv/kernel/ipi-mux.c +++ b/arch/riscv/kernel/ipi-mux.c @@ -144,6 +144,7 @@ static int ipi_mux_starting_cpu(unsigned int cpu) } =20 struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { @@ -198,7 +199,7 @@ struct irq_domain *riscv_ipi_mux_create(bool use_soft_i= rq, "irqchip/riscv/ipi-mux:starting", ipi_mux_starting_cpu, ipi_mux_dying_cpu); =20 - riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, use_for_rfence); =20 return ipi_mux_priv.domain; =20 diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index ab38814f1977..909fb36a0910 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -652,7 +652,8 @@ static void sbi_ipi_clear(void) =20 void __init sbi_ipi_init(void) { - if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + if (riscv_ipi_mux_create(true, false, + sbi_ipi_clear, sbi_send_cpumask_ipi)) pr_info("providing IPIs using SBI IPI extension\n"); } =20 diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index a9f1aca38358..b98d9c319f6f 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -149,7 +149,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } =20 -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; =20 @@ -172,6 +175,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) =20 /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); =20 diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index b05a9e946633..607d47dab896 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -224,7 +224,7 @@ static int __init clint_timer_init_dt(struct device_nod= e *np) goto fail_free_irq; } =20 - riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); + riscv_ipi_mux_create(true, true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); =20 return 0; --=20 2.25.1 From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75624C433EF for ; Tue, 1 Mar 2022 04:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbiCAE3b (ORCPT ); Mon, 28 Feb 2022 23:29:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232297AbiCAE3T (ORCPT ); Mon, 28 Feb 2022 23:29:19 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 198F14E395 for ; Mon, 28 Feb 2022 20:28:39 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id d17so18434114wrc.9 for ; Mon, 28 Feb 2022 20:28:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gulBS1a3GDwTjV3gPNI1Ld+RqIL2YPtNwx+Ha/YsDb0=; b=Puv3jS3yxYrmy/Wq1z55hOwBixDPaWB5vIsJA4yUcPkgKDUfxuUneL//cTo6BYz6W0 fjaokoL7mTjnxa3jrd7iXtqi67wMGZSiPLkTZKJpV7987CzhUOxERZ2PvLKxM+gwe8Ku ZGNQrKEySnzIQg+6dqrc06N4+hH2foqVE9RZHs9PK9Ac+Q6AJJxFxextFCypPGvZdDBS EdKnMjOJWJDjS75e1JGInEYgt7uULhpYLx8yS/+Mu4I/QA2A5ss9fhp4VnzxZ2a+nwj5 Yia9Fj0izkecTCaYt+aMGrTQv6pRGUPA1ZTnI9hhr+w3MYX51mBBegLYxDJHyLF4n+Ae 6a3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gulBS1a3GDwTjV3gPNI1Ld+RqIL2YPtNwx+Ha/YsDb0=; b=wmE2HskCEEfZqIWm7/6lfIxNrhc2DzkuAia87Tzax/PvwN4O88Auq+fo0LZ5U5OzAs p6i8py04Jusvz7EMd8z0SRyQzPQFFxA9d4CDDfF+bIN8tw+C2dV9Bua1jYBSAjkPo0XP 134qNlQNld2XFiC5JQR69N3GNeYIH+RoSaCi2rlihj+l+wzZkICl/8VU3fPcz7gFpDZf XvQaZACkSHoISuiHUfasdVV2TFRwSUV3/KOaTe6H0c8/NjjJ/hsMEbeFJQBavsY8PRMd bJcNxx61/bQ1AxZByEZrdQ4ph01rGgVslYkwtvJ/h5vcq8v1PKjcAuIpOKUOpUlT9RTA gd2A== X-Gm-Message-State: AOAM530knm3RslGDrj3HCEDjVC4RJKcIOfdEDtIA9W53IHKx7MIpmwe4 sDOQ1bF7woKmFFjGBl2b4XgCuw== X-Google-Smtp-Source: ABdhPJwI6DiDysV89Auh+g1ZzDOJsVAU15rOTyJCda1Rc/WZjA/Z0U3Frp4Wjlfxki88Csf75xDTrw== X-Received: by 2002:a5d:50c5:0:b0:1f0:2111:8f74 with SMTP id f5-20020a5d50c5000000b001f021118f74mr2051wrt.211.1646108917693; Mon, 28 Feb 2022 20:28:37 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:37 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 5/6] RISC-V: Use IPIs for remote TLB flush when possible Date: Tue, 1 Mar 2022 09:57:21 +0530 Message-Id: <20220301042722.401113-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 37ed760d007c..27a7db8eb2c4 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned l= ong addr, : "memory"); } =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, unsigned long asid =3D atomic_long_read(&mm->context.id); =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.25.1 From nobody Tue Jun 23 18:14:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5DECC4332F for ; Tue, 1 Mar 2022 04:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232237AbiCAE3m (ORCPT ); Mon, 28 Feb 2022 23:29:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232326AbiCAE3i (ORCPT ); Mon, 28 Feb 2022 23:29:38 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 532B34EA0E for ; Mon, 28 Feb 2022 20:28:44 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id ay10so627580wrb.6 for ; Mon, 28 Feb 2022 20:28:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sX9W0jJI3V+TTQxrILZfbGus1iz/Yao2DvXh0KaNAVk=; b=l9W+NGbgxdapkSDh1674O7D8QLnibie0+u3PaStrMsDolQoNXQay/fD6eG7haTMIex 9hjRC1bPjXL+ev46XF0WqEfHSvHTI+AuD2lrFA7vLF1nc+s2uyeXiNlNj2JJec7gGgUn 2JES8wdSB7kl8EW3lDrqR+StUYnr+zca0owdBvyFARzpwItdzw+AfPumhlGKDM3pXQ30 QLa59UPT2zCDE4YnRQ2OACeI3iJFAqeiSAVc6dg9DX2q4W6goTjqVMDCKbvl4mKCSYBH b2givfpcsF2VQPBwZy/zWEwsP0GS9pyXxCiqkO8t7LeOKA2HHjJBnCjucp/WssWGSUI1 dqoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sX9W0jJI3V+TTQxrILZfbGus1iz/Yao2DvXh0KaNAVk=; b=qe3mVotArASa2sRMLhnTLjU8s/RVydAIX3GpEbWX4uMkh2G5fFJDoss0hKrEG6UUKo jINHubk7Pmo9Q5VwbxIaj+bncHublIhX2LFUy59HYpMfN395E++hdVjvBG1WfLIOGJSY 5IzeqRFLlL38TL5E98jSy5QSHge8mzpkYeGt86EHZPlAMB64nAJ9mH3Ln0ReL6tpl6jC x5qFgE4Q20AGdf4WHOkK7VhyDgboRkNIv6V1GDrs5t2QpAIyySHdqtR0adhI/QP941lL oEZwlO0MmrZIIpoPUKJH7xzNNk1zbdj3XfhZ2PGF7KQqTUiBWlxen5ezRquNA++1vif8 eeVw== X-Gm-Message-State: AOAM532qIOHQYeqTYWZLUrGqAzxbWBUADX3Xx5sl8twWTHKzHiPyUPTA rpfe95OijkgQFUokQT3Ph59FdA== X-Google-Smtp-Source: ABdhPJyGhlMwmtEnqXiAm8QiDsDHXaZmhEWG6M8Am41WiNmn6yrzFFympTA20zKYu+3kv7rh5608sg== X-Received: by 2002:a5d:4606:0:b0:1ed:d3c0:19f4 with SMTP id t6-20020a5d4606000000b001edd3c019f4mr18570799wrq.555.1646108922741; Mon, 28 Feb 2022 20:28:42 -0800 (PST) Received: from localhost.localdomain ([122.179.35.69]) by smtp.gmail.com with ESMTPSA id 2-20020a1c1902000000b00380d3873d6asm1209107wmz.43.2022.02.28.20.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 20:28:42 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v4 6/6] RISC-V: Use IPIs for remote icache flush when possible Date: Tue, 1 Mar 2022 09:57:22 +0530 Message-Id: <20220301042722.401113-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220301042722.401113-1-apatel@ventanamicro.com> References: <20220301042722.401113-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote icache flushe directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote icache flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel --- arch/riscv/mm/cacheflush.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..7c7e44aaf791 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -18,7 +18,7 @@ void flush_icache_all(void) { local_flush_icache_all(); =20 - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -66,7 +66,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); --=20 2.25.1