From nobody Tue Jun 23 18:19:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6DCFC4332F for ; Mon, 28 Feb 2022 23:22:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbiB1XW4 (ORCPT ); Mon, 28 Feb 2022 18:22:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229732AbiB1XWx (ORCPT ); Mon, 28 Feb 2022 18:22:53 -0500 Received: from imap3.hz.codethink.co.uk (imap3.hz.codethink.co.uk [176.9.8.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD819A27A2; Mon, 28 Feb 2022 15:22:10 -0800 (PST) Received: from cpc152649-stkp13-2-0-cust121.10-2.cable.virginm.net ([86.15.83.122] helo=rainbowdash) by imap3.hz.codethink.co.uk with esmtpsa (Exim 4.92 #3 (Debian)) id 1nOpLD-000510-L9; Mon, 28 Feb 2022 23:22:07 +0000 Received: from ben by rainbowdash with local (Exim 4.95) (envelope-from ) id 1nOpLD-00CHuf-3I; Mon, 28 Feb 2022 23:22:07 +0000 From: Ben Dooks To: helgaas@kernel.org, linux-pci@vger.kernel.org Cc: paul.walmsley@sifive.com, greentime.hu@sifive.com, lorenzo.pieralisi@arm.com, robh@kernel.org, linux-kernel@vger.kernel.org, Ben Dooks Subject: [RFC] PCI: fu740: Force Gen1 to fix initial device probing on some boards Date: Mon, 28 Feb 2022 23:22:06 +0000 Message-Id: <20220228232206.2928784-1-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The fu740 PCIe core does not probe any devices on the SiFive Unmatched board without this fix (or having U-Boot explicitly start the PCIe via either boot-script or user command). The fix is to start the link at Gen1 speeds and once the link is up then change the speed back. The U-Boot driver claims to set the link-speed to Gen1 to get the probe to work (and U-Boot does print link up at Gen1) in the following code: https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/pci/pcie_dw_sifi= ve.c?id=3Dv2022.01#L271 Signed-off-by: Ben Dooks -- Note, this patch has had significant re-work since the previous 4 sets, including trying to fix style, message, reliance on the U-Boot fix and the comments about usage of LINK_CAP and reserved fields. --- drivers/pci/controller/dwc/pcie-fu740.c | 51 ++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index 842b7202b96e..16ad52f53490 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -181,10 +181,59 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev =3D pci->dev; struct fu740_pcie *afp =3D dev_get_drvdata(dev); + u8 cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + int ret; + u32 orig, tmp; + + /* + * Force Gen1 when starting link, due to some devices not + * probing at higher speeds. This happens with the PCIe switch + * on the Unmatched board. The fix in U-Boot is to force Gen1 + * and hope later resets will clear this capaility. + */ + + dev_dbg(dev, "cap_exp at %x\n", cap_exp); + dw_pcie_dbi_ro_wr_en(pci); + + tmp =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP); + orig =3D tmp & PCI_EXP_LNKCAP_SLS; + tmp &=3D ~PCI_EXP_LNKCAP_SLS; + tmp |=3D PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp); =20 /* Enable LTSSM */ writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); - return 0; + + ret =3D dw_pcie_wait_for_link(pci); + if (ret) { + dev_err(dev, "error: link did not start\n"); + goto err; + } + + tmp =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP); + if ((tmp & PCI_EXP_LNKCAP_SLS) !=3D orig) { + dev_dbg(dev, "changing speed back to original\n"); + + tmp &=3D ~PCI_EXP_LNKCAP_SLS; + tmp |=3D orig; + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp); + + tmp =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + tmp |=3D PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + + ret =3D dw_pcie_wait_for_link(pci); + if (ret) { + dev_err(dev, "error: link did not start at new speed\n"); + goto err; + } + } + + ret =3D 0; +err: + // todo - if we do have an unliekly error, what do we do here? + dw_pcie_dbi_ro_wr_dis(pci); + return ret; } =20 static int fu740_pcie_host_init(struct pcie_port *pp) --=20 2.34.1