From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C008C433F5 for ; Mon, 28 Feb 2022 11:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233206AbiB1LST (ORCPT ); Mon, 28 Feb 2022 06:18:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234966AbiB1LSD (ORCPT ); Mon, 28 Feb 2022 06:18:03 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48C8D2A70F for ; Mon, 28 Feb 2022 03:17:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047043; x=1677583043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BH6EZIu4OsWu2aIV5tde913BHkUKDL7QFYpT5jrDQJg=; b=WpaF0rYa0sOErDh5r96oCBoa/tRQlFAA2N1KL1oJISyqcTLLqQG9otlw C2ESUwOoWpnt9t5ImSzqs2CR4NCA7SSj3Ny/47aHUi2O9CNxyWbztCGSK m2f2KOJ+yJ12rW1/5bFaPEnq/jC5WSBZFkL5oUxRJx+8DC2RnMqLtHXY/ g+otnh58+ZjuGsuMPS+R+n3sJ1aMr791twpG2yKI7VGk4VtbhxhiHj2qn 4GIa+lthtDJy0eSgHXJ0MaWqfomLCCSWgYaTm068HaGXf1AZgPV4wuDaN uKhdTuTjWeCjrmP49RhDj+pJshSq4JPhA0Iuy5YCJlgXwUTCxGWIfqImC Q==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="154614913" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:21 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:18 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 1/8] mtd: spi-nor: Rename method, s/spi_nor_match_id/spi_nor_match_name Date: Mon, 28 Feb 2022 13:17:05 +0200 Message-ID: <20220228111712.111737-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The method is matching a flash_info entry by searching by name. Rename the method for better clarity. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 9014008e60b3..f3c359d03163 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2876,8 +2876,8 @@ void spi_nor_restore(struct spi_nor *nor) } EXPORT_SYMBOL_GPL(spi_nor_restore); =20 -static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, - const char *name) +static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, + const char *name) { unsigned int i, j; =20 @@ -2899,7 +2899,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, const struct flash_info *info =3D NULL; =20 if (name) - info =3D spi_nor_match_id(nor, name); + info =3D spi_nor_match_name(nor, name); /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) info =3D spi_nor_read_id(nor); --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 510A1C433F5 for ; Mon, 28 Feb 2022 11:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234326AbiB1LS3 (ORCPT ); Mon, 28 Feb 2022 06:18:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232894AbiB1LSO (ORCPT ); Mon, 28 Feb 2022 06:18:14 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCD66A1A2 for ; Mon, 28 Feb 2022 03:17:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047055; x=1677583055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+858RdAMNjlEkMUdfziJy7i+wtZ5Om3Lqcya2mdiono=; b=iGwN+7YUtBHP0V8Xm9rmnwNJNdG92mTMWLRnCRSqTF1gnOj0hzL7Jq6R 2FZHCStOimrNUR2VH20hcj+5J4mzBd9RySeu9HIX6lnoPthdX8JHtXLIV 1H1mNQPEbg0w+e1HSyWznob3L4dQGtNYkzVJWDLkw8Gx2tEv3EoypGApB L3Xk5g+Vv6ZV0PhQa8ytzQmhPZYZZEmPrOpVkjbtZrcmt0Hcc7Oz6JVIi J9amJkGormlKXE6Or/y/60Jl+sfXET8PesqQj4dQbbcdo0yNAxvYc7pGm 9guph9RHwWJqYLiRjMJUKhc306UVwNLisdOySJed6PWPmmAX18EXVTl/y w==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="155099347" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:24 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:21 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 2/8] mtd: spi-nor: Introduce spi_nor_match_id() Date: Mon, 28 Feb 2022 13:17:06 +0200 Message-ID: <20220228111712.111737-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Similar to spi_nor_match_name() extend the search of flash_info through all the manufacturers, this time doing the match by ID. There's no reason to limit the search per manufacturer yet, do it globally, search the flash in all the parts of all manufacturers in a single method. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 40 ++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f3c359d03163..f87cb7d3daab 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1629,16 +1629,21 @@ static const struct spi_nor_manufacturer *manufactu= rers[] =3D { &spi_nor_xmc, }; =20 -static const struct flash_info * -spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int npa= rts, - const u8 *id) +static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, + const u8 *id) { - unsigned int i; + const struct flash_info *part; + unsigned int i, j; =20 - for (i =3D 0; i < nparts; i++) { - if (parts[i].id_len && - !memcmp(parts[i].id, id, parts[i].id_len)) - return &parts[i]; + for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { + for (j =3D 0; j < manufacturers[i]->nparts; j++) { + part =3D &manufacturers[i]->parts[j]; + if (part->id_len && + !memcmp(part->id, id, part->id_len)) { + nor->manufacturer =3D manufacturers[i]; + return part; + } + } } =20 return NULL; @@ -1648,7 +1653,6 @@ static const struct flash_info *spi_nor_read_id(struc= t spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; - unsigned int i; int ret; =20 if (nor->spimem) { @@ -1668,19 +1672,13 @@ static const struct flash_info *spi_nor_read_id(str= uct spi_nor *nor) return ERR_PTR(ret); } =20 - for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { - info =3D spi_nor_search_part_by_id(manufacturers[i]->parts, - manufacturers[i]->nparts, - id); - if (info) { - nor->manufacturer =3D manufacturers[i]; - return info; - } + info =3D spi_nor_match_id(nor, id); + if (!info) { + dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", + SPI_NOR_MAX_ID_LEN, id); + return ERR_PTR(-ENODEV); } - - dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", - SPI_NOR_MAX_ID_LEN, id); - return ERR_PTR(-ENODEV); + return info; } =20 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 540F9C433EF for ; Mon, 28 Feb 2022 11:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233592AbiB1LS0 (ORCPT ); Mon, 28 Feb 2022 06:18:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231856AbiB1LSN (ORCPT ); Mon, 28 Feb 2022 06:18:13 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E9F19FEE for ; Mon, 28 Feb 2022 03:17:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047054; x=1677583054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s9N00WUuaR+7M96AS0RHeuJkB2gYdo9QK+uWa+lBy+Q=; b=kHta7B+7f62d297MTEVUe5/qNVMfooBEsFGP3YiscmGYmZMkqP+gpfzZ rnUcM6aXcI0lfUeLkm6FFAQu7G4qX2vayODVfwuIKqRhiCStGaZ04wop6 8DTB70gy815G4kdvoh2ho3GxD47dUXWlmAMZ6aH6MvwbWnrCCfiwDGyFk xnMI1UUsKGk03ObHehUk40X1GcvLrv+85USHuAB3k1HF3KtMA6UI9zlY6 IkE0PREmI9NHOUY3HZux0wRGlFdXAtr0DO0H+3upqqCjpHeEQoZO+K7Iy RP1WhVYmuGY6Nl756Ysob9VnzwA3wNClDWz3JPPUgEaqDNo6P4YzBaw9X w==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="155099351" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:28 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:24 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 3/8] mtd: spi-nor: core: Use auto-detection only once Date: Mon, 28 Feb 2022 13:17:07 +0200 Message-ID: <20220228111712.111737-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In case spi_nor_match_name() returned NULL, the auto detection was issued twice. There's no reason to try to detect the same chip twice, do the auto detection only once. Signed-off-by: Tudor Ambarus Suggested-by tag. --- drivers/mtd/spi-nor/core.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f87cb7d3daab..b1d6fa65417d 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2894,13 +2894,15 @@ static const struct flash_info *spi_nor_match_name(= struct spi_nor *nor, static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { - const struct flash_info *info =3D NULL; + const struct flash_info *info =3D NULL, *detected_info =3D NULL; =20 if (name) info =3D spi_nor_match_name(nor, name); /* Try to auto-detect if chip name wasn't specified or not found */ - if (!info) - info =3D spi_nor_read_id(nor); + if (!info) { + detected_info =3D spi_nor_read_id(nor); + info =3D detected_info; + } if (IS_ERR_OR_NULL(info)) return ERR_PTR(-ENOENT); =20 @@ -2908,7 +2910,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, * If caller has specified name of flash model that can normally be * detected using JEDEC, let's verify it. */ - if (name && info->id_len) { + if (name && !detected_info && info->id_len) { const struct flash_info *jinfo; =20 jinfo =3D spi_nor_read_id(nor); --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32473C433F5 for ; Mon, 28 Feb 2022 11:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233580AbiB1LSW (ORCPT ); Mon, 28 Feb 2022 06:18:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235467AbiB1LSK (ORCPT ); Mon, 28 Feb 2022 06:18:10 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 865D9116C for ; Mon, 28 Feb 2022 03:17:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047052; x=1677583052; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DR2YsqBmdwcOSI3VhJ4E7f+oGievG1RU62MQV0VJZB8=; b=GoW2IzL4Z43aUrf65PHZswbciYTorJWoam9DrjL4dvXMlfQOIOdemOX7 c5Ob0v8hnU95i1j84UNRcKDk7p3MYlViZJXhPAzo/52YDKbuneC0VQ0nQ foeSCdkYeNZ6uJA9+cgI5RmX5nRiuNMgTGvdkUapFR+7h92YTa5EuQ6TY TmsziGQZg1PmiCI+lzMWoJGCe5NOChL6tPPG4bQsLI+IMv9fEYqMy8TTC kDDZ0x3mnl2b5t5xLeosmGZlxuKNySw8a57qksBxw5QZrSMElJMAGyLhx HrRLQoMI/juLBf6DelKxp/xOTqvbav2j+9IGvs/ZYn39DZC2NOTfuDD0a g==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="163859339" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:31 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:28 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 4/8] mtd: spi-nor: core: Introduce method for RDID op Date: Mon, 28 Feb 2022 13:17:08 +0200 Message-ID: <20220228111712.111737-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 58 ++++++++++++++++++++++++++------------ drivers/mtd/spi-nor/core.h | 9 ++++++ 2 files changed, 49 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b1d6fa65417d..281e3d25f74c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -369,6 +369,41 @@ int spi_nor_write_disable(struct spi_nor *nor) return ret; } =20 +/** + * spi_nor_read_id() - Read the JEDEC ID. + * @nor: pointer to 'struct spi_nor'. + * @naddr: number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @ndummy: number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @id: pointer to a DMA-able buffer where the value of the JEDEC ID + * will be written. + * @reg_proto: the SPI protocol for register operation. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN); + + spi_nor_spimem_setup_op(nor, &op, reg_proto); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, + SPI_NOR_MAX_ID_LEN); + } + + if (ret) + dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); + + return ret; +} + /** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. @@ -1649,28 +1684,15 @@ static const struct flash_info *spi_nor_match_id(st= ruct spi_nor *nor, return NULL; } =20 -static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) +static const struct flash_info *spi_nor_detect(struct spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; int ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, - SPI_NOR_MAX_ID_LEN); - } - if (ret) { - dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); + ret =3D spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); + if (ret) return ERR_PTR(ret); - } =20 info =3D spi_nor_match_id(nor, id); if (!info) { @@ -2900,7 +2922,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, info =3D spi_nor_match_name(nor, name); /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) { - detected_info =3D spi_nor_read_id(nor); + detected_info =3D spi_nor_detect(nor); info =3D detected_info; } if (IS_ERR_OR_NULL(info)) @@ -2913,7 +2935,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, if (name && !detected_info && info->id_len) { const struct flash_info *jinfo; =20 - jinfo =3D spi_nor_read_id(nor); + jinfo =3D spi_nor_detect(nor); if (IS_ERR(jinfo)) { return jinfo; } else if (jinfo !=3D info) { diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b7fd760e3b47..f952061d5c24 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -11,6 +11,13 @@ =20 #define SPI_NOR_MAX_ID_LEN 6 =20 +/* Standard SPI NOR flash operations. */ +#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ + SPI_MEM_OP_ADDR(naddr, 0, 0), \ + SPI_MEM_OP_DUMMY(ndummy, 0), \ + SPI_MEM_OP_DATA_IN(len, buf, 0)) + enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(0), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), @@ -534,6 +541,8 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); int spi_nor_sr_ready(struct spi_nor *nor); int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54B83C433F5 for ; Mon, 28 Feb 2022 11:17:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234780AbiB1LSd (ORCPT ); Mon, 28 Feb 2022 06:18:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233024AbiB1LSP (ORCPT ); Mon, 28 Feb 2022 06:18:15 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89A279FEE for ; Mon, 28 Feb 2022 03:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047056; x=1677583056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mKoKfdaQ7sfaHkKYIDfL8XSqEbj7jOZmi0dTb4Ji8IE=; b=Vrw9pEVgjhainkEwBH5PMGE1AUmOoZ/dfVP6QMN06HzQHKpczkIQ/mTT rgPayZxiRPL6c/F5QsaBr5bX3g0/r/aTxPVP5/SNXqfhsRPumGBG6fq6Y X1HkBpPVQ1vTZ5NaeC5Oq0mvMiQbxlZukdMSurqFgMAJkyKYIjSZAFLLC ggrgMfjisei18FGTS2PGj+mGMd8hHfeqA+rd8Z3o7wjNiO+WDE4pKnqLe XPKY7Qp6Ox6aKuwG2xddiVTxH+bvqUMmTtKUkmmPXL88JjIT6Bi+/lxJ4 BEFd9gOKwdTAyD6EYIXlgM3XgOi2vFjoGcBWuzqaJvqi0Oq7Te6jw3vsF g==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="155099358" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:35 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:32 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 5/8] mtd: spi-nor: manufacturers: Use spi_nor_read_id() core method Date: Mon, 28 Feb 2022 13:17:09 +0200 Message-ID: <20220228111712.111737-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use spi_nor_read_id() core method to avoid duplication of code. Now the ID is read on the full SPI_NOR_MAX_ID_LEN instead of round_up(nor->info->id_len, 2), but it doesn't harm to read more ID bytes, so the change comes with no secondary effects. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 13 +++---------- drivers/mtd/spi-nor/spansion.c | 13 +++---------- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 8a20475ce77a..41b87868ecf9 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -91,17 +91,10 @@ static int micron_st_nor_octal_dtr_enable(struct spi_no= r *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_DUMMY(enable ? 8 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index f24e546e04a5..c5988312cc91 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -98,17 +98,10 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor = *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1), - SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77AD2C433FE for ; Mon, 28 Feb 2022 11:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234801AbiB1LSk (ORCPT ); Mon, 28 Feb 2022 06:18:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233455AbiB1LSW (ORCPT ); Mon, 28 Feb 2022 06:18:22 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78BCA9FE5 for ; Mon, 28 Feb 2022 03:17:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047062; x=1677583062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4k8NB06Tt38eO1sMpf6pSXXFWiN02DmgonwSIAOs4U4=; b=x3DXgTmyeyKTU4YTEiGdCIYU2rLcg7/S8M3RxR8Q2H+9ZJrXJyXVkcue LHjmJSoNOKOha8+aguW52DRz1cu3vqAXY5Y5uXg+nOrv30LkAVvGs54te G+4uNah9ihEmBtsRo3viEoDRH59FfUUg95usxbWn2yJq6Ei5r7iVAxDH2 TCSg/WoZt4dqiJ860U69ejP8nSgIlUSw7JWy7nnY4E127J0awTmCR1LT/ eU1sbNLKAxgO0hEnFZmgNPE4Q1+0/Zt6EkjuC8zrF9TsG8J0OHNuYLCK/ YU5Sk6ylMJcbb2+uOt4Xw6cL7w5Y/mj/6GsCRnROI3MkgIM6XOxiMfqzD Q==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="150223243" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:40 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:39 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:36 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus , Takahiro Kuwano Subject: [PATCH v2 6/8] mtd: spi-nor: core: Add helpers to read/write any register Date: Mon, 28 Feb 2022 13:17:10 +0200 Message-ID: <20220228111712.111737-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 41 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 4 ++++ 2 files changed, 45 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 281e3d25f74c..f1aa1e2ea7c9 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t= to, size_t len, return nor->controller_ops->write(nor, to, len, buf); } =20 +/** + * spi_nor_read_reg() - read register to flash memory + * @nor: pointer to 'struct spi_nor'. + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + if (!nor->spimem) + return -EOPNOTSUPP; + + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + +/** + * spi_nor_write_reg() - write register to flash memory + * @nor: pointer to 'struct spi_nor' + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + int ret; + + if (!nor->spimem) + return -EOPNOTSUPP; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + /** * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f952061d5c24..7c704475946d 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -554,6 +554,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t = from, size_t len, u8 *buf); ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf); +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); =20 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8= *buf); --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2701BC433EF for ; Mon, 28 Feb 2022 11:18:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235322AbiB1LSs (ORCPT ); Mon, 28 Feb 2022 06:18:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233756AbiB1LSZ (ORCPT ); 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28 Feb 2022 04:17:44 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:44 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:40 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 7/8] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Mon, 28 Feb 2022 13:17:11 +0200 Message-ID: <20220228111712.111737-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/micron-st.c | 105 +++++++++++++++++--------------- 1 file changed, 55 insertions(+), 50 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 41b87868ecf9..12ec3660fd6f 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -28,73 +28,72 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ =20 -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Micron ST SPI NOR flash operations. */ +#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 20 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - *buf =3D 20; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; + /* Use 20 dummy cycles for memory array reads. */ + *buf =3D 20; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - } + buf[0] =3D SPINOR_MT_OCT_DTR; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_nor_write_enable(nor); + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_MT_OCT_DTR; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. The next register is the dummy - * cycle configuration register. Since the transaction needs to - * be at least 2 bytes wide, set the next register to its - * default value. This also makes sense because the value was - * changed when enabling 8D-8D-8D mode, it should be reset when - * disabling. - */ - buf[0] =3D SPINOR_MT_EXSPI; - buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; - } + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_MT_CFR0V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + return 0; +} =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); +static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. The next register is the dummy cycle configuration + * register. Since the transaction needs to be at least 2 bytes wide, + * set the next register to its default value. This also makes sense + * because the value was changed when enabling 8D-8D-8D mode, it should + * be reset when disabling. + */ + buf[0] =3D SPINOR_MT_EXSPI; + buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 @@ -104,6 +103,12 @@ static int micron_st_nor_octal_dtr_enable(struct spi_n= or *nor, bool enable) return 0; } =20 +static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? micron_st_nor_octal_dtr_en(nor) : + micron_st_nor_octal_dtr_dis(nor); +} + static void mt35xu512aba_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D micron_st_nor_octal_dtr_enable; --=20 2.25.1 From nobody Tue Jun 23 19:24:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 295D1C433F5 for ; Mon, 28 Feb 2022 11:18:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234423AbiB1LSw (ORCPT ); Mon, 28 Feb 2022 06:18:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234103AbiB1LS3 (ORCPT ); Mon, 28 Feb 2022 06:18:29 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDDF413D1D for ; Mon, 28 Feb 2022 03:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646047068; x=1677583068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VQvBDn7lgST9nEDYvtRN+GxLxvX8FlvhBJSvDUXvefk=; b=dVhf/xAnDSe45qA+Urqe1tDA4+0HfJR8LADI4/Yacw7e7CpOY+a8I4aQ H9fx8YKiTD7McGtofbsuOvHOEVyqSlCpJ2XZF3MMg1jniLrKIPkY+ZCYR 0F/x8a0+KHnzKHGx6Fd0Ajqb5/cvd5uFxCqFEd4o+PX/dnNSpMZPYFSYy rbxje0DVmEr8mAIGonNTcfMgjoe/Hvo4zMJo31FYFGvtm7T7Ftl6Adzql hF4FV4XiUfkzkC0JurgPi4kWxyVO9B5CDiab/EtdzA5e27WI+edACPl51 aEgTn7JYNhoWf/zZQdp7+OzGBVj05Wzv3p0ASaajOFze4T9ZyfVb0+15Q g==; X-IronPort-AV: E=Sophos;i="5.90,142,1643698800"; d="scan'208";a="150223261" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Feb 2022 04:17:48 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 28 Feb 2022 04:17:47 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 28 Feb 2022 04:17:44 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v2 8/8] mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable() Date: Mon, 28 Feb 2022 13:17:12 +0200 Message-ID: <20220228111712.111737-9-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228111712.111737-1-tudor.ambarus@microchip.com> References: <20220228111712.111737-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/spansion.c | 124 +++++++++++++++++---------------- 1 file changed, 65 insertions(+), 59 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index c5988312cc91..34ca3538a0f9 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -23,85 +23,75 @@ #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 #define SPINOR_OP_CYPRESS_RD_FAST 0xee =20 -/** - * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. - * @nor: pointer to a 'struct spi_nor' - * @enable: whether to enable or disable Octal DTR - * - * This also sets the memory access latency cycles to 24 to allow the flas= h to - * run at up to 200MHz. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Cypress SPI NOR flash operations. */ +#define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 24 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; + /* Use 24 dummy cycles for memory array reads. */ + *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf); =20 - *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; + nor->read_dummy =3D 24; =20 - nor->read_dummy =3D 24; - } + /* Set the octal and DTR enable bits. */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf); =20 - /* Set/unset the octal and DTR enable bits. */ - ret =3D spi_nor_write_enable(nor); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. Since there is no register at the - * next location, just initialize the value to 0 and let the - * transaction go on. - */ - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; - buf[1] =3D 0; - } + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) + return ret; =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_CYPRESS_CFR5V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + return 0; +} =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. Since there is no register at the next location, + * just initialize the value to 0 and let the transaction go on. + */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[1] =3D 0; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 @@ -111,6 +101,22 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor= *nor, bool enable) return 0; } =20 +/** + * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal DTR + * + * This also sets the memory access latency cycles to 24 to allow the flas= h to + * run at up to 200MHz. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? cypress_nor_octal_dtr_en(nor) : + cypress_nor_octal_dtr_dis(nor); +} + static void s28hs512t_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D cypress_nor_octal_dtr_enable; --=20 2.25.1