From nobody Tue Jun 23 22:30:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19ABFC433F5 for ; Fri, 25 Feb 2022 09:47:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239237AbiBYJsL (ORCPT ); Fri, 25 Feb 2022 04:48:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237986AbiBYJsJ (ORCPT ); Fri, 25 Feb 2022 04:48:09 -0500 Received: from smtpproxy21.qq.com (smtpbg703.qq.com [203.205.195.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E75E219140F for ; Fri, 25 Feb 2022 01:47:36 -0800 (PST) X-QQ-mid: bizesmtp69t1645782450t0kbe8hh Received: from localhost.localdomain (unknown [58.240.82.166]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 25 Feb 2022 17:47:24 +0800 (CST) X-QQ-SSF: 01400000002000C0F000000A0000000 X-QQ-FEAT: vsfsx1ezZ8T9jEj1xNfTc/NNOY+XLDtQ8KYfXZfbFq1OAyvxyybatFq69W8AI mycbPgvMN1QnO8/m3gZ4MXNE0Zk+9eIzUD8kDpcX4/3m0fuYQ1g3dyoYAnSaGiXEl3fj6HF Km8scUlBVEan0JXqC0YQjUEIv+KBhB2DCtPGymk80N91YFlBGLQEvDJrWy39/796K1qPCVo khjMPwmDue14T9tCbafeiSZU4SIUKbVJYPzTUUtsJitFFd2u/qoW0Q/W4Ir/CiC7S1lWgxU hQ3WedHzT9K7OtW/iRZ8aTvg9APS/5NBzkWNrRTQe9cg0PEDaogOItAu/D5uXmJR5xDa+hJ qkd9CQSAwDFbvgrIHt/V9YHcl4/IX7b4dN7hOQoCBap8M7kzcg= X-QQ-GoodBg: 1 From: Meng Tang To: airlied@linux.ie, daniel@ffwll.ch Cc: evan.quan@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Meng Tang Subject: [PATCH] gpu/amd: vega10_hwmgr: fix inappropriate private variable name Date: Fri, 25 Feb 2022 17:47:22 +0800 Message-Id: <20220225094722.4734-1-tangmeng@uniontech.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:uniontech.com:qybgforeign:qybgforeign2 X-QQ-Bgrelay: 1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In file vega10_hwmgr.c, the names of struct vega10_power_state * and struct pp_power_state * are confusingly used, which may lead to some confusion. Status quo is that variables of type struct vega10_power_state * are named "vega10_ps", "ps", "vega10_power_state". A more appropriate usage is that struct are named "ps" is used for variabled of type struct pp_power_state *. So rename struct vega10_power_state * which are named "ps" and "vega10_power_state" to "vega10_ps", I also renamed "psa" to "vega10_psa" and "psb" to "vega10_psb" to make it more clearly. The rows longer than 100 columns are involved. Signed-off-by: Meng Tang --- .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 68 +++++++++++-------- 1 file changed, 38 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/driver= s/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 3f040be0d158..37324f2009ca 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -3095,7 +3095,7 @@ static int vega10_get_pp_table_entry_callback_func(st= ruct pp_hwmgr *hwmgr, void *pp_table, uint32_t classification_flag) { ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; - struct vega10_power_state *vega10_power_state =3D + struct vega10_power_state *vega10_ps =3D cast_phw_vega10_power_state(&(power_state->hardware)); struct vega10_performance_level *performance_level; ATOM_Vega10_State *state_entry =3D (ATOM_Vega10_State *)state; @@ -3145,17 +3145,17 @@ static int vega10_get_pp_table_entry_callback_func(= struct pp_hwmgr *hwmgr, power_state->temperatures.min =3D 0; power_state->temperatures.max =3D 0; =20 - performance_level =3D &(vega10_power_state->performance_levels - [vega10_power_state->performance_level_count++]); + performance_level =3D &(vega10_ps->performance_levels + [vega10_ps->performance_level_count++]); =20 PP_ASSERT_WITH_CODE( - (vega10_power_state->performance_level_count < + (vega10_ps->performance_level_count < NUM_GFXCLK_DPM_LEVELS), "Performance levels exceeds SMC limit!", return -1); =20 PP_ASSERT_WITH_CODE( - (vega10_power_state->performance_level_count <=3D + (vega10_ps->performance_level_count <=3D hwmgr->platform_descriptor. hardwareActivityPerformanceLevels), "Performance levels exceeds Driver limit!", @@ -3169,8 +3169,8 @@ static int vega10_get_pp_table_entry_callback_func(st= ruct pp_hwmgr *hwmgr, performance_level->mem_clock =3D mclk_dep_table->entries [state_entry->ucMemClockIndexLow].ulMemClk; =20 - performance_level =3D &(vega10_power_state->performance_levels - [vega10_power_state->performance_level_count++]); + performance_level =3D &(vega10_ps->performance_levels + [vega10_ps->performance_level_count++]); performance_level->soc_clock =3D socclk_dep_table->entries [state_entry->ucSocClockIndexHigh].ulClk; if (gfxclk_dep_table->ucRevId =3D=3D 0) { @@ -3201,11 +3201,11 @@ static int vega10_get_pp_table_entry(struct pp_hwmg= r *hwmgr, unsigned long entry_index, struct pp_power_state *state) { int result; - struct vega10_power_state *ps; + struct vega10_power_state *vega10_ps; =20 state->hardware.magic =3D PhwVega10_Magic; =20 - ps =3D cast_phw_vega10_power_state(&state->hardware); + vega10_ps =3D cast_phw_vega10_power_state(&state->hardware); =20 result =3D vega10_get_powerplay_table_entry(hwmgr, entry_index, state, vega10_get_pp_table_entry_callback_func); @@ -3218,10 +3218,10 @@ static int vega10_get_pp_table_entry(struct pp_hwmg= r *hwmgr, */ /* set DC compatible flag if this state supports DC */ if (!state->validation.disallowOnDC) - ps->dc_compatible =3D true; + vega10_ps->dc_compatible =3D true; =20 - ps->uvd_clks.vclk =3D state->uvd_clocks.VCLK; - ps->uvd_clks.dclk =3D state->uvd_clocks.DCLK; + vega10_ps->uvd_clks.vclk =3D state->uvd_clocks.VCLK; + vega10_ps->uvd_clks.dclk =3D state->uvd_clocks.DCLK; =20 return 0; } @@ -4823,33 +4823,41 @@ static int vega10_check_states_equal(struct pp_hwmg= r *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) { - const struct vega10_power_state *psa; - const struct vega10_power_state *psb; + const struct vega10_power_state *vega10_psa; + const struct vega10_power_state *vega10_psb; int i; =20 if (pstate1 =3D=3D NULL || pstate2 =3D=3D NULL || equal =3D=3D NULL) return -EINVAL; =20 - psa =3D cast_const_phw_vega10_power_state(pstate1); - psb =3D cast_const_phw_vega10_power_state(pstate2); - /* If the two states don't even have the same number of performance level= s they cannot be the same state. */ - if (psa->performance_level_count !=3D psb->performance_level_count) { + vega10_psa =3D cast_const_phw_vega10_power_state(pstate1); + vega10_psb =3D cast_const_phw_vega10_power_state(pstate2); + + /* If the two states don't even have the same number of performance levels + * they cannot be the same state. + */ + if (vega10_psa->performance_level_count !=3D vega10_psb->performance_leve= l_count) { *equal =3D false; return 0; } =20 - for (i =3D 0; i < psa->performance_level_count; i++) { - if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb-= >performance_levels[i]))) { - /* If we have found even one performance level pair that is different t= he states are different. */ + for (i =3D 0; i < vega10_psa->performance_level_count; i++) { + if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]), + &(vega10_psb->performance_levels[i]))) { + /* If we have found even one performance level pair + * that is different the states are different. + */ *equal =3D false; return 0; } } =20 /* If all performance levels are the same try to use the UVD clocks to br= eak the tie.*/ - *equal =3D ((psa->uvd_clks.vclk =3D=3D psb->uvd_clks.vclk) && (psa->uvd_c= lks.dclk =3D=3D psb->uvd_clks.dclk)); - *equal &=3D ((psa->vce_clks.evclk =3D=3D psb->vce_clks.evclk) && (psa->vc= e_clks.ecclk =3D=3D psb->vce_clks.ecclk)); - *equal &=3D (psa->sclk_threshold =3D=3D psb->sclk_threshold); + *equal =3D ((vega10_psa->uvd_clks.vclk =3D=3D vega10_psb->uvd_clks.vclk) = && + (vega10_psa->uvd_clks.dclk =3D=3D vega10_psb->uvd_clks.dclk)); + *equal &=3D ((vega10_psa->vce_clks.evclk =3D=3D vega10_psb->vce_clks.evcl= k) && + (vega10_psa->vce_clks.ecclk =3D=3D vega10_psb->vce_clks.ecclk)); + *equal &=3D (vega10_psa->sclk_threshold =3D=3D vega10_psb->sclk_threshold= ); =20 return 0; } @@ -5444,19 +5452,19 @@ static int vega10_get_performance_level(struct pp_h= wmgr *hwmgr, const struct pp_ PHM_PerformanceLevelDesignation designation, uint32_t index, PHM_PerformanceLevel *level) { - const struct vega10_power_state *ps; + const struct vega10_power_state *vega10_ps; uint32_t i; =20 if (level =3D=3D NULL || hwmgr =3D=3D NULL || state =3D=3D NULL) return -EINVAL; =20 - ps =3D cast_const_phw_vega10_power_state(state); + vega10_ps =3D cast_const_phw_vega10_power_state(state); =20 - i =3D index > ps->performance_level_count - 1 ? - ps->performance_level_count - 1 : index; + i =3D index > vega10_ps->performance_level_count - 1 ? + vega10_ps->performance_level_count - 1 : index; =20 - level->coreClock =3D ps->performance_levels[i].gfx_clock; - level->memory_clock =3D ps->performance_levels[i].mem_clock; + level->coreClock =3D vega10_ps->performance_levels[i].gfx_clock; + level->memory_clock =3D vega10_ps->performance_levels[i].mem_clock; =20 return 0; } --=20 2.20.1