From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20396C4332F for ; Thu, 24 Feb 2022 17:26:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231454AbiBXR0r (ORCPT ); Thu, 24 Feb 2022 12:26:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229549AbiBXR0k (ORCPT ); Thu, 24 Feb 2022 12:26:40 -0500 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DD0A2782AE for ; Thu, 24 Feb 2022 09:26:09 -0800 (PST) Received: by mail-yb1-xb49.google.com with SMTP id w1-20020a05690204e100b006244315a721so499609ybs.0 for ; Thu, 24 Feb 2022 09:26:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=OHhLpLvB3qKnaPMcJXUCZPNXxBBzMdDsCYySjLei9Uc=; b=GrmGz3NFqhQz8C/BrDEZksYrGBoDx3ClpAKEtXxgXUijApRe7oeu30tFdFBHip9AWl Nm6e1k1lIxlvIAfX08PiYuv8PCbtfyDqxffFlH4RKyuTMB4riC/yYSkRj+FLEsN9tvC/ mhqysm/alXSR4TLGQM59yOML8RnlMBm9tGksFVxG8JnpeHsf8NiNarDAu5c8uCmEX978 RkCAbpWeiBfRFyv2/VQPgdVhcxb04YI01QrBv/d9KsshovlAl8RjOPNBIxEIuIB1gxFb 7W63DZ3+AO+oV6ebv1/i9aGIKwEjpuowb4zR39gQ0sdfPZv3Z0/cOyTDoSpFU7NghcXl d3vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=OHhLpLvB3qKnaPMcJXUCZPNXxBBzMdDsCYySjLei9Uc=; b=rieEjm3UPmTkCskp8ZXaJqQ/XCrMBvrd5zrIJ+XCG73+pKYNfey7+ovd/CzDAFW2mN YDW1Z729+F4BWjDEyuu92o6keGokf1WFqiO3XBLIGOWuHYcIXQc0wnvNpImszonWq5OW 2vQoMr94MWluaEzPYXBk9VwFKWuSXwed+IVAUpZ4UYpby6b/0IhnxhsszkeoLjTe+bh2 B/9MJCsWhBCr8Dd8DKrvcE9A+STgMtDassd6WxCdoH782tscsKfuxDV7qv0/fwpwHdIi VeOd+OTCmD7uPT2tX+4HVfXK8GsSIeVIvRnJnHQ8TtHROb4lrrg38OQtksMLRAp+Qmuj GFjg== X-Gm-Message-State: AOAM530Hgm3nAgJorIa/pt5P0nH4acH/vHYy1f6raWjeTV1cGTAKtwXQ lgmNGPVDR60ULyTecPqx3sSG1X2QNIPY X-Google-Smtp-Source: ABdhPJwBPy85gowI0srCVbE8O6AG99yJGSXUDaBo2gPb6bw41u0maONws+UInNcfiuwA6dqmu/fn+HbxZMHI X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a05:6902:693:b0:613:7f4f:2e63 with SMTP id i19-20020a056902069300b006137f4f2e63mr3364017ybt.271.1645723568558; Thu, 24 Feb 2022 09:26:08 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:47 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-2-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 01/13] KVM: arm64: Factor out firmware register handling from psci.c From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Common hypercall firmware register handing is currently employed by psci.c. Since the upcoming patches add more of these registers, it's better to move the generic handling to hypercall.c for a cleaner presentation. While we are at it, collect all the firmware registers under fw_reg_ids[] to help implement kvm_arm_get_fw_num_regs() and kvm_arm_copy_fw_reg_indices() in a generic way. No functional change intended. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Oliver Upton --- arch/arm64/kvm/guest.c | 2 +- arch/arm64/kvm/hypercalls.c | 170 +++++++++++++++++++++++++++++++++++ arch/arm64/kvm/psci.c | 166 ---------------------------------- include/kvm/arm_hypercalls.h | 7 ++ include/kvm/arm_psci.h | 7 -- 5 files changed, 178 insertions(+), 174 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index e116c7767730..8238e52d890d 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 30da78f72b3b..3c2fcf31ad3d 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -146,3 +146,173 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) smccc_set_retval(vcpu, val[0], val[1], val[2], val[3]); return 1; } + +static const u64 kvm_arm_fw_reg_ids[] =3D { + KVM_REG_ARM_PSCI_VERSION, + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, +}; + +int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) +{ + return ARRAY_SIZE(kvm_arm_fw_reg_ids); +} + +int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { + if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) + return -EFAULT; + } + + return 0; +} + +#define KVM_REG_FEATURE_LEVEL_WIDTH 4 +#define KVM_REG_FEATURE_LEVEL_MASK (BIT(KVM_REG_FEATURE_LEVEL_WIDTH) - 1) + +/* + * Convert the workaround level into an easy-to-compare number, where high= er + * values mean better protection. + */ +static int get_kernel_wa_level(u64 regid) +{ + switch (regid) { + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + switch (arm64_get_spectre_v2_state()) { + case SPECTRE_VULNERABLE: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; + case SPECTRE_MITIGATED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL; + case SPECTRE_UNAFFECTED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED; + } + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + switch (arm64_get_spectre_v4_state()) { + case SPECTRE_MITIGATED: + /* + * As for the hypercall discovery, we pretend we + * don't have any FW mitigation if SSBS is there at + * all times. + */ + if (cpus_have_final_cap(ARM64_SSBS)) + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + fallthrough; + case SPECTRE_UNAFFECTED: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; + case SPECTRE_VULNERABLE: + return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + } + } + + return -EINVAL; +} + +int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + void __user *uaddr =3D (void __user *)(long)reg->addr; + u64 val; + + switch (reg->id) { + case KVM_REG_ARM_PSCI_VERSION: + val =3D kvm_psci_version(vcpu, vcpu->kvm); + break; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; + break; + default: + return -ENOENT; + } + + if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + void __user *uaddr =3D (void __user *)(long)reg->addr; + u64 val; + int wa_level; + + if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + switch (reg->id) { + case KVM_REG_ARM_PSCI_VERSION: + { + bool wants_02; + + wants_02 =3D test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features); + + switch (val) { + case KVM_ARM_PSCI_0_1: + if (wants_02) + return -EINVAL; + vcpu->kvm->arch.psci_version =3D val; + return 0; + case KVM_ARM_PSCI_0_2: + case KVM_ARM_PSCI_1_0: + if (!wants_02) + return -EINVAL; + vcpu->kvm->arch.psci_version =3D val; + return 0; + } + break; + } + + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: + if (val & ~KVM_REG_FEATURE_LEVEL_MASK) + return -EINVAL; + + if (get_kernel_wa_level(reg->id) < val) + return -EINVAL; + + return 0; + + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: + if (val & ~(KVM_REG_FEATURE_LEVEL_MASK | + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED)) + return -EINVAL; + + /* The enabled bit must not be set unless the level is AVAIL. */ + if ((val & KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED) && + (val & KVM_REG_FEATURE_LEVEL_MASK) !=3D KVM_REG_ARM_SMCCC_ARCH_WORKA= ROUND_2_AVAIL) + return -EINVAL; + + /* + * Map all the possible incoming states to the only two we + * really want to deal with. + */ + switch (val & KVM_REG_FEATURE_LEVEL_MASK) { + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN: + wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; + break; + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL: + case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: + wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; + break; + default: + return -EINVAL; + } + + /* + * We can deal with NOT_AVAIL on NOT_REQUIRED, but not the + * other way around. + */ + if (get_kernel_wa_level(reg->id) < wa_level) + return -EINVAL; + + return 0; + default: + return -ENOENT; + } + + return -EINVAL; +} diff --git a/arch/arm64/kvm/psci.c b/arch/arm64/kvm/psci.c index 3eae32876897..d5bc663a8629 100644 --- a/arch/arm64/kvm/psci.c +++ b/arch/arm64/kvm/psci.c @@ -403,169 +403,3 @@ int kvm_psci_call(struct kvm_vcpu *vcpu) return -EINVAL; }; } - -int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) -{ - return 3; /* PSCI version and two workaround registers */ -} - -int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) -{ - if (put_user(KVM_REG_ARM_PSCI_VERSION, uindices++)) - return -EFAULT; - - if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, uindices++)) - return -EFAULT; - - if (put_user(KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, uindices++)) - return -EFAULT; - - return 0; -} - -#define KVM_REG_FEATURE_LEVEL_WIDTH 4 -#define KVM_REG_FEATURE_LEVEL_MASK (BIT(KVM_REG_FEATURE_LEVEL_WIDTH) - 1) - -/* - * Convert the workaround level into an easy-to-compare number, where high= er - * values mean better protection. - */ -static int get_kernel_wa_level(u64 regid) -{ - switch (regid) { - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - switch (arm64_get_spectre_v2_state()) { - case SPECTRE_VULNERABLE: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; - case SPECTRE_MITIGATED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL; - case SPECTRE_UNAFFECTED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED; - } - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - switch (arm64_get_spectre_v4_state()) { - case SPECTRE_MITIGATED: - /* - * As for the hypercall discovery, we pretend we - * don't have any FW mitigation if SSBS is there at - * all times. - */ - if (cpus_have_final_cap(ARM64_SSBS)) - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - fallthrough; - case SPECTRE_UNAFFECTED: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; - case SPECTRE_VULNERABLE: - return KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - } - } - - return -EINVAL; -} - -int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) -{ - void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; - - switch (reg->id) { - case KVM_REG_ARM_PSCI_VERSION: - val =3D kvm_psci_version(vcpu, vcpu->kvm); - break; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; - break; - default: - return -ENOENT; - } - - if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) - return -EFAULT; - - return 0; -} - -int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) -{ - void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; - int wa_level; - - if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) - return -EFAULT; - - switch (reg->id) { - case KVM_REG_ARM_PSCI_VERSION: - { - bool wants_02; - - wants_02 =3D test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features); - - switch (val) { - case KVM_ARM_PSCI_0_1: - if (wants_02) - return -EINVAL; - vcpu->kvm->arch.psci_version =3D val; - return 0; - case KVM_ARM_PSCI_0_2: - case KVM_ARM_PSCI_1_0: - if (!wants_02) - return -EINVAL; - vcpu->kvm->arch.psci_version =3D val; - return 0; - } - break; - } - - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: - if (val & ~KVM_REG_FEATURE_LEVEL_MASK) - return -EINVAL; - - if (get_kernel_wa_level(reg->id) < val) - return -EINVAL; - - return 0; - - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - if (val & ~(KVM_REG_FEATURE_LEVEL_MASK | - KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED)) - return -EINVAL; - - /* The enabled bit must not be set unless the level is AVAIL. */ - if ((val & KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED) && - (val & KVM_REG_FEATURE_LEVEL_MASK) !=3D KVM_REG_ARM_SMCCC_ARCH_WORKA= ROUND_2_AVAIL) - return -EINVAL; - - /* - * Map all the possible incoming states to the only two we - * really want to deal with. - */ - switch (val & KVM_REG_FEATURE_LEVEL_MASK) { - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN: - wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL; - break; - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL: - case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: - wa_level =3D KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED; - break; - default: - return -EINVAL; - } - - /* - * We can deal with NOT_AVAIL on NOT_REQUIRED, but not the - * other way around. - */ - if (get_kernel_wa_level(reg->id) < wa_level) - return -EINVAL; - - return 0; - default: - return -ENOENT; - } - - return -EINVAL; -} diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 0e2509d27910..5d38628a8d04 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -40,4 +40,11 @@ static inline void smccc_set_retval(struct kvm_vcpu *vcp= u, vcpu_set_reg(vcpu, 3, a3); } =20 +struct kvm_one_reg; + +int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); +int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); +int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); +int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); + #endif diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index 5b58bd2fe088..080c2d0bd6e7 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -42,11 +42,4 @@ static inline int kvm_psci_version(struct kvm_vcpu *vcpu= , struct kvm *kvm) =20 int kvm_psci_call(struct kvm_vcpu *vcpu); =20 -struct kvm_one_reg; - -int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); -int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); -int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); -int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); - #endif /* __KVM_ARM_PSCI_H__ */ --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C07C2C433EF for ; Thu, 24 Feb 2022 17:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231651AbiBXR05 (ORCPT ); Thu, 24 Feb 2022 12:26:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbiBXR0m (ORCPT ); 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charset="utf-8" KVM_[GET|SET]_ONE_REG act on per-vCPU basis. Currently certain ARM64 registers, such as KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_[1|2], are accessed via this interface even though the effect that they have are really per-VM. As a result, userspace could just waste cycles to read/write the same information for every vCPU that it spawns, only to realize that there's absolutely no change in the VM's state. The problem gets worse in proportion to the number of vCPUs created. As a result, to avoid this redundancy, introduce the capability KVM_CAP_ARM_REG_SCOPE. If enabled, KVM_GET_REG_LIST will advertise the registers that are VM-scoped by dynamically modifying the register encoding. KVM_REG_ARM_SCOPE_* helper macros are introduced to decode the same. By learning this, userspace can access such registers only once. Signed-off-by: Raghavendra Rao Ananta --- Documentation/virt/kvm/api.rst | 16 ++++++++++++++++ arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/include/uapi/asm/kvm.h | 6 ++++++ arch/arm64/kvm/arm.c | 13 +++++++------ include/uapi/linux/kvm.h | 1 + 5 files changed, 33 insertions(+), 6 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index a4267104db50..7e7b3439f540 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7561,3 +7561,19 @@ The argument to KVM_ENABLE_CAP is also a bitmask, an= d must be a subset of the result of KVM_CHECK_EXTENSION. KVM will forward to userspace the hypercalls whose corresponding bit is in the argument, and return ENOSYS for the others. + +8.34 KVM_CAP_ARM_REG_SCOPE +-------------------------- + +:Architectures: arm64 + +The capability, if enabled, amends the existing register encoding +with additional information to the userspace if a particular register +is scoped per-vCPU or per-VM via KVM_GET_REG_LIST. KVM provides +KVM_REG_ARM_SCOPE_* helper macros to decode the same. Userspace can +use this information from the register encoding to access a VM-scopped +regiser only once, as opposed to accessing it for every vCPU for the +same effect. + +On the other hand, if the capability is disabled, all the registers +remain vCPU-scopped by default, retaining backward compatibility. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 5bc01e62c08a..8132de6bd718 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -136,6 +136,9 @@ struct kvm_arch { =20 /* Memory Tagging Extension enabled for the guest */ bool mte_enabled; + + /* Register scoping enabled for KVM registers */ + bool reg_scope_enabled; }; =20 struct kvm_vcpu_fault_info { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index b3edde68bc3e..c35447cc0e0c 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -199,6 +199,12 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 #define KVM_REG_ARM_COPROC_SHIFT 16 =20 +/* Defines if a KVM register is one per-vCPU or one per-VM */ +#define KVM_REG_ARM_SCOPE_MASK 0x0000000010000000 +#define KVM_REG_ARM_SCOPE_SHIFT 28 +#define KVM_REG_ARM_SCOPE_VCPU 0 +#define KVM_REG_ARM_SCOPE_VM 1 + /* Normal registers are mapped as coprocessor 16. */ #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / size= of(__u32)) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index ecc5958e27fe..107977c82c6c 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -81,26 +81,26 @@ int kvm_arch_check_processor_compat(void *opaque) int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { - int r; + int r =3D 0; =20 if (cap->flags) return -EINVAL; =20 switch (cap->cap) { case KVM_CAP_ARM_NISV_TO_USER: - r =3D 0; kvm->arch.return_nisv_io_abort_to_user =3D true; break; case KVM_CAP_ARM_MTE: mutex_lock(&kvm->lock); - if (!system_supports_mte() || kvm->created_vcpus) { + if (!system_supports_mte() || kvm->created_vcpus) r =3D -EINVAL; - } else { - r =3D 0; + else kvm->arch.mte_enabled =3D true; - } mutex_unlock(&kvm->lock); break; + case KVM_CAP_ARM_REG_SCOPE: + WRITE_ONCE(kvm->arch.reg_scope_enabled, true); + break; default: r =3D -EINVAL; break; @@ -209,6 +209,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) case KVM_CAP_SET_GUEST_DEBUG: case KVM_CAP_VCPU_ATTRIBUTES: case KVM_CAP_PTP_KVM: + case KVM_CAP_ARM_REG_SCOPE: r =3D 1; break; case KVM_CAP_SET_GUEST_DEBUG2: diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 5191b57e1562..c4fe81ed9ee6 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1134,6 +1134,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_VM_GPA_BITS 207 #define KVM_CAP_XSAVE2 208 #define KVM_CAP_SYS_ATTRIBUTES 209 +#define KVM_CAP_ARM_REG_SCOPE 210 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D85DDC433EF for ; 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charset="utf-8" The psuedo-firmware registers, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 and KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, can be scopped as per-VM registers. Hence, during the KVM_GET_REG_LIST call, encode KVM_REG_ARM_SCOPE_VM into the registers, but during KVM_[GET|SET]_ONE_REG calls, clear the scope information such that they can be processed like before. For future expansion, helper functions such as kvm_arm_reg_id_encode_scope() and kvm_arm_reg_id_clear_scope() are introduced. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/guest.c | 77 +++++++++++++++++++++++++++++++ arch/arm64/kvm/hypercalls.c | 31 +++++++++---- 3 files changed, 100 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8132de6bd718..657733554d98 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -794,6 +794,8 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features)) =20 int kvm_trng_call(struct kvm_vcpu *vcpu); +int kvm_arm_reg_id_encode_scope(struct kvm_vcpu *vcpu, u64 *reg_id); +void kvm_arm_reg_id_clear_scope(struct kvm_vcpu *vcpu, u64 *reg_id); #ifdef CONFIG_KVM extern phys_addr_t hyp_mem_base; extern phys_addr_t hyp_mem_size; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 8238e52d890d..eb061e64a7a5 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -61,6 +61,83 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D { sizeof(kvm_vcpu_stats_desc), }; =20 +/* Registers that are VM scopped */ +static const u64 kvm_arm_vm_scope_fw_regs[] =3D { + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, + KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, +}; + +/** + * kvm_arm_reg_id_encode_scope - Encode the KVM_REG_ARM_SCOPE info into the + * register-id + * @vcpu: The vcpu pointer + * @reg_id: Pointer to the register + * + * The function adds the register's scoping information into its encoding. + * If it's explicitly marked as a per-VM register, it's encoded with + * KVM_REG_ARM_SCOPE_VM. Else, it's marked as KVM_REG_ARM_SCOPE_VCPU, which + * is also the default if KVM_CAP_ARM_REG_SCOPE is disabled. + * + * For any error cases, the function returns an error code, else it returns + * the integer value of the encoding. + */ +int kvm_arm_reg_id_encode_scope(struct kvm_vcpu *vcpu, u64 *reg_id) +{ + const u64 *vm_scope_reg_arr; + unsigned int arr_size, idx; + + if (!READ_ONCE(vcpu->kvm->arch.reg_scope_enabled)) + return KVM_REG_ARM_SCOPE_VCPU; + + if (!reg_id) + return -EINVAL; + + switch (*reg_id & KVM_REG_ARM_COPROC_MASK) { + case KVM_REG_ARM_FW: + vm_scope_reg_arr =3D kvm_arm_vm_scope_fw_regs; + arr_size =3D ARRAY_SIZE(kvm_arm_vm_scope_fw_regs); + break; + default: + /* All the other register classes are currently + * treated as per-vCPU registers. + */ + return KVM_REG_ARM_SCOPE_VCPU; + } + + /* By default, all the registers encodings are scoped as vCPU. + * Modify the scope only if a register is marked as per-VM. + */ + for (idx =3D 0; idx < arr_size; idx++) { + if (vm_scope_reg_arr[idx] =3D=3D *reg_id) { + *reg_id |=3D + KVM_REG_ARM_SCOPE_VM << KVM_REG_ARM_SCOPE_SHIFT; + return KVM_REG_ARM_SCOPE_VM; + } + } + + return KVM_REG_ARM_SCOPE_VCPU; +} + +/** + * kvm_arm_reg_id_clear_scope - Clear the KVM_REG_ARM_SCOPE info from the + * register-id + * @vcpu: The vcpu pointer + * @reg_id: Pointer to the register + * + * The function clears the register's scoping information, which ultimately + * is the raw encoding of the register. Note that the result is same as th= at + * of re-encoding the register as KVM_REG_ARM_SCOPE_VCPU. + * The function can be helpful to the existing code that uses the original + * register encoding to operate on the register. + */ +void kvm_arm_reg_id_clear_scope(struct kvm_vcpu *vcpu, u64 *reg_id) +{ + if (!READ_ONCE(vcpu->kvm->arch.reg_scope_enabled) || !reg_id) + return; + + *reg_id &=3D ~(1 << KVM_REG_ARM_SCOPE_SHIFT); +} + static bool core_reg_offset_is_vreg(u64 off) { return off >=3D KVM_REG_ARM_CORE_REG(fp_regs.vregs) && diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 3c2fcf31ad3d..8624e6964940 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -160,10 +160,17 @@ int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) =20 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) { - int i; + int i, ret; + u64 reg_id; =20 for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { - if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) + reg_id =3D kvm_arm_fw_reg_ids[i]; + + ret =3D kvm_arm_reg_id_encode_scope(vcpu, ®_id); + if (ret < 0) + return ret; + + if (put_user(reg_id, uindices++)) return -EFAULT; } =20 @@ -214,21 +221,23 @@ static int get_kernel_wa_level(u64 regid) int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; + u64 val, reg_id =3D reg->id; =20 - switch (reg->id) { + kvm_arm_reg_id_clear_scope(vcpu, ®_id); + + switch (reg_id) { case KVM_REG_ARM_PSCI_VERSION: val =3D kvm_psci_version(vcpu, vcpu->kvm); break; case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1: case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: - val =3D get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; + val =3D get_kernel_wa_level(reg_id) & KVM_REG_FEATURE_LEVEL_MASK; break; default: return -ENOENT; } =20 - if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) + if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg_id))) return -EFAULT; =20 return 0; @@ -237,13 +246,15 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const s= truct kvm_one_reg *reg) int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { void __user *uaddr =3D (void __user *)(long)reg->addr; - u64 val; + u64 val, reg_id =3D reg->id; int wa_level; =20 if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 - switch (reg->id) { + kvm_arm_reg_id_clear_scope(vcpu, ®_id); + + switch (reg_id) { case KVM_REG_ARM_PSCI_VERSION: { bool wants_02; @@ -270,7 +281,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (val & ~KVM_REG_FEATURE_LEVEL_MASK) return -EINVAL; =20 - if (get_kernel_wa_level(reg->id) < val) + if (get_kernel_wa_level(reg_id) < val) return -EINVAL; =20 return 0; @@ -306,7 +317,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) * We can deal with NOT_AVAIL on NOT_REQUIRED, but not the * other way around. */ - if (get_kernel_wa_level(reg->id) < wa_level) + if (get_kernel_wa_level(reg_id) < wa_level) return -EINVAL; =20 return 0; --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B854C433EF for ; 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Thu, 24 Feb 2022 09:26:15 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:50 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-5-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 04/13] KVM: arm64: Capture VM's first run From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Capture the first run of the KVM VM, which is basically the first KVM_RUN issued for any vCPU. This state of the VM is helpful in the upcoming patches to prevent user-space from configuring certain VM features, such as the feature bitmap exposed by the psuedo-firmware registers, after the VM has started running. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 9 +++++++++ arch/arm64/kvm/arm.c | 2 ++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 657733554d98..e823571e50cc 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -139,6 +139,9 @@ struct kvm_arch { =20 /* Register scoping enabled for KVM registers */ bool reg_scope_enabled; + + /* Capture first run of the VM */ + bool has_run_once; }; =20 struct kvm_vcpu_fault_info { @@ -796,6 +799,12 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); int kvm_trng_call(struct kvm_vcpu *vcpu); int kvm_arm_reg_id_encode_scope(struct kvm_vcpu *vcpu, u64 *reg_id); void kvm_arm_reg_id_clear_scope(struct kvm_vcpu *vcpu, u64 *reg_id); + +static inline bool kvm_arm_vm_has_run_once(struct kvm_arch *kvm_arch) +{ + return kvm_arch->has_run_once; +} + #ifdef CONFIG_KVM extern phys_addr_t hyp_mem_base; extern phys_addr_t hyp_mem_size; diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 107977c82c6c..f61cd8d57eae 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -635,6 +635,8 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) if (kvm_vm_is_protected(kvm)) kvm_call_hyp_nvhe(__pkvm_vcpu_init_traps, vcpu); =20 + kvm->arch.has_run_once =3D true; + return ret; } =20 --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34CB8C433EF for ; Thu, 24 Feb 2022 17:26:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231214AbiBXR1R (ORCPT ); Thu, 24 Feb 2022 12:27:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231527AbiBXR0s (ORCPT ); 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charset="utf-8" KVM regularly introduces new hypercall services to the guests without any consent from the userspace. This means, the guests can observe hypercall services in and out as they migrate across various host kernel versions. This could be a major problem if the guest discovered a hypercall, started using it, and after getting migrated to an older kernel realizes that it's no longer available. Depending on how the guest handles the change, there's a potential chance that the guest would just panic. As a result, there's a need for the userspace to elect the services that it wishes the guest to discover. It can elect these services based on the kernels spread across its (migration) fleet. To remedy this, extend the existing firmware psuedo-registers, such as KVM_REG_ARM_PSCI_VERSION, for all the hypercall services available. These firmware registers are categorized based on the service call owners, and unlike the existing firmware psuedo-registers, they hold the features supported in the form of a bitmap. During the VM initialization, the registers holds an upper-limit of the features supported by the corresponding registers. It's expected that the VMMs discover the features provided by each register via GET_ONE_REG, and writeback the desired values using SET_ONE_REG. KVM allows this modification only until the VM has started. Older userspace code can simply ignore the capability and the hypercall services will be exposed unconditionally to the guests, thus ensuring backward compatibility. In this patch, the framework adds the register only for ARM's standard secure services (owner value 4). Currently, this includes support only for ARM True Random Number Generator (TRNG) service, with bit-0 of the register representing mandatory features of v1.0. The register is also added to the kvm_arm_vm_scope_fw_regs[] list as it maintains its state per-VM. Other services are momentarily added in the upcoming patches. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 12 +++++ arch/arm64/include/uapi/asm/kvm.h | 8 ++++ arch/arm64/kvm/arm.c | 8 ++++ arch/arm64/kvm/guest.c | 1 + arch/arm64/kvm/hypercalls.c | 78 +++++++++++++++++++++++++++++++ include/kvm/arm_hypercalls.h | 4 ++ 6 files changed, 111 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index e823571e50cc..1909ced3208f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -101,6 +101,15 @@ struct kvm_s2_mmu { struct kvm_arch_memory_slot { }; =20 +/** + * struct kvm_hvc_desc: KVM ARM64 hypercall descriptor + * + * @hvc_std_bmap: Bitmap of standard secure service calls + */ +struct kvm_hvc_desc { + u64 hvc_std_bmap; +}; + struct kvm_arch { struct kvm_s2_mmu mmu; =20 @@ -142,6 +151,9 @@ struct kvm_arch { =20 /* Capture first run of the VM */ bool has_run_once; + + /* Hypercall firmware register' descriptor */ + struct kvm_hvc_desc hvc_desc; }; =20 struct kvm_vcpu_fault_info { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index c35447cc0e0c..2decc30d6b84 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -287,6 +287,14 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) =20 +/* Bitmap firmware registers, extension to the existing psuedo-register sp= ace */ +#define KVM_REG_ARM_FW_BMAP KVM_REG_ARM_FW_REG(0xff00) +#define KVM_REG_ARM_FW_BMAP_REG(r) (KVM_REG_ARM_FW_BMAP | (r)) + +#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_BMAP_REG(0) +#define KVM_REG_ARM_STD_BIT_TRNG_V1_0 BIT(0) +#define KVM_REG_ARM_STD_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index f61cd8d57eae..e9f9edb1cf55 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -156,6 +156,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long typ= e) kvm->arch.max_vcpus =3D kvm_arm_default_max_vcpus(); =20 set_default_spectre(kvm); + kvm_arm_init_hypercalls(kvm); =20 return ret; out_free_stage2_pgd: @@ -635,7 +636,14 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) if (kvm_vm_is_protected(kvm)) kvm_call_hyp_nvhe(__pkvm_vcpu_init_traps, vcpu); =20 + /* + * Grab kvm->lock such that the reader of has_run_once can finish + * the necessary operation atomically, such as deciding whether to + * block the writes to the firmware registers if the VM has run once. + */ + mutex_lock(&kvm->lock); kvm->arch.has_run_once =3D true; + mutex_unlock(&kvm->lock); =20 return ret; } diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index eb061e64a7a5..d66e6c742bbe 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -65,6 +65,7 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D { static const u64 kvm_arm_vm_scope_fw_regs[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, + KVM_REG_ARM_STD_BMAP, }; =20 /** diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 8624e6964940..48c126c3da72 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -58,6 +58,29 @@ static void kvm_ptp_get_time(struct kvm_vcpu *vcpu, u64 = *val) val[3] =3D lower_32_bits(cycles); } =20 +static bool kvm_arm_fw_reg_feat_enabled(u64 reg_bmap, u64 feat_bit) +{ + return reg_bmap & feat_bit; +} + +static bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu, u32 func_id) +{ + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; + + switch (func_id) { + case ARM_SMCCC_TRNG_VERSION: + case ARM_SMCCC_TRNG_FEATURES: + case ARM_SMCCC_TRNG_GET_UUID: + case ARM_SMCCC_TRNG_RND32: + case ARM_SMCCC_TRNG_RND64: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_bmap, + KVM_REG_ARM_STD_BIT_TRNG_V1_0); + default: + /* By default, allow the services that aren't listed here */ + return true; + } +} + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { u32 func_id =3D smccc_get_function(vcpu); @@ -65,6 +88,9 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) u32 feature; gpa_t gpa; =20 + if (!kvm_hvc_call_supported(vcpu, func_id)) + goto out; + switch (func_id) { case ARM_SMCCC_VERSION_FUNC_ID: val[0] =3D ARM_SMCCC_VERSION_1_1; @@ -143,6 +169,7 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) return kvm_psci_call(vcpu); } =20 +out: smccc_set_retval(vcpu, val[0], val[1], val[2], val[3]); return 1; } @@ -151,8 +178,16 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { KVM_REG_ARM_PSCI_VERSION, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, + KVM_REG_ARM_STD_BMAP, }; =20 +void kvm_arm_init_hypercalls(struct kvm *kvm) +{ + struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; + + hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; +} + int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) { return ARRAY_SIZE(kvm_arm_fw_reg_ids); @@ -220,6 +255,7 @@ static int get_kernel_wa_level(u64 regid) =20 int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; void __user *uaddr =3D (void __user *)(long)reg->addr; u64 val, reg_id =3D reg->id; =20 @@ -233,6 +269,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2: val =3D get_kernel_wa_level(reg_id) & KVM_REG_FEATURE_LEVEL_MASK; break; + case KVM_REG_ARM_STD_BMAP: + val =3D READ_ONCE(hvc_desc->hvc_std_bmap); + break; default: return -ENOENT; } @@ -243,6 +282,43 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const st= ruct kvm_one_reg *reg) return 0; } =20 +static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vcpu, u64 reg_id, u64 = val) +{ + int ret =3D 0; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; + u64 *fw_reg_bmap, fw_reg_features; + + switch (reg_id) { + case KVM_REG_ARM_STD_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_std_bmap; + fw_reg_features =3D ARM_SMCCC_STD_FEATURES; + break; + default: + return -ENOENT; + } + + /* Check for unsupported bit */ + if (val & ~fw_reg_features) + return -EINVAL; + + mutex_lock(&kvm->lock); + + /* + * If the VM (any vCPU) has already started running, return success + * if there's no change in the value. Else, return -EBUSY. + */ + if (kvm_arm_vm_has_run_once(&kvm->arch)) { + ret =3D *fw_reg_bmap !=3D val ? -EBUSY : 0; + goto out; + } + + WRITE_ONCE(*fw_reg_bmap, val); +out: + mutex_unlock(&kvm->lock); + return ret; +} + int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { void __user *uaddr =3D (void __user *)(long)reg->addr; @@ -321,6 +397,8 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return -EINVAL; =20 return 0; + case KVM_REG_ARM_STD_BMAP: + return kvm_arm_set_fw_reg_bmap(vcpu, reg_id, val); default: return -ENOENT; } diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 5d38628a8d04..64d30b452809 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -6,6 +6,9 @@ =20 #include =20 +#define ARM_SMCCC_STD_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_STD_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) @@ -42,6 +45,7 @@ static inline void smccc_set_retval(struct kvm_vcpu *vcpu, =20 struct kvm_one_reg; =20 +void kvm_arm_init_hypercalls(struct kvm *kvm); int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu); int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s); int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g); --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41BA0C433EF for ; Thu, 24 Feb 2022 17:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231801AbiBXR1Z (ORCPT ); Thu, 24 Feb 2022 12:27:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231570AbiBXR0v (ORCPT ); Thu, 24 Feb 2022 12:26:51 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 259CC278C8B for ; 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Thu, 24 Feb 2022 09:26:20 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:52 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-7-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 06/13] KVM: arm64: Add standard hypervisor firmware register From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the firmware register to hold the standard hypervisor service calls (owner value 5) as a bitmap. The bitmap represents the features that'll be enabled for the guest, as configured by the user-space. Currently, this includes support only for Paravirtualized time, represented by bit-0. The register is also added to the kvm_arm_vm_scope_fw_regs[] list as it maintains its state per-VM. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/uapi/asm/kvm.h | 4 ++++ arch/arm64/kvm/guest.c | 1 + arch/arm64/kvm/hypercalls.c | 20 +++++++++++++++++++- include/kvm/arm_hypercalls.h | 3 +++ 5 files changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 1909ced3208f..318148b69279 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -105,9 +105,11 @@ struct kvm_arch_memory_slot { * struct kvm_hvc_desc: KVM ARM64 hypercall descriptor * * @hvc_std_bmap: Bitmap of standard secure service calls + * @hvc_std_hyp_bmap: Bitmap of standard hypervisor service calls */ struct kvm_hvc_desc { u64 hvc_std_bmap; + u64 hvc_std_hyp_bmap; }; =20 struct kvm_arch { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 2decc30d6b84..9a2caead7359 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -295,6 +295,10 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_STD_BIT_TRNG_V1_0 BIT(0) #define KVM_REG_ARM_STD_BMAP_BIT_MAX 0 /* Last valid bit */ =20 +#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_BMAP_REG(1) +#define KVM_REG_ARM_STD_HYP_BIT_PV_TIME BIT(0) +#define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index d66e6c742bbe..c42426d6137e 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -66,6 +66,7 @@ static const u64 kvm_arm_vm_scope_fw_regs[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, KVM_REG_ARM_STD_BMAP, + KVM_REG_ARM_STD_HYP_BMAP, }; =20 /** diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index 48c126c3da72..ebc0cc26cf2e 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -75,6 +75,10 @@ static bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu= , u32 func_id) case ARM_SMCCC_TRNG_RND64: return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_bmap, KVM_REG_ARM_STD_BIT_TRNG_V1_0); + case ARM_SMCCC_HV_PV_TIME_FEATURES: + case ARM_SMCCC_HV_PV_TIME_ST: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_hyp_bmap, + KVM_REG_ARM_STD_HYP_BIT_PV_TIME); default: /* By default, allow the services that aren't listed here */ return true; @@ -83,6 +87,7 @@ static bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu,= u32 func_id) =20 int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) { + struct kvm_hvc_desc *hvc_desc =3D &vcpu->kvm->arch.hvc_desc; u32 func_id =3D smccc_get_function(vcpu); u64 val[4] =3D {SMCCC_RET_NOT_SUPPORTED}; u32 feature; @@ -134,7 +139,10 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) } break; case ARM_SMCCC_HV_PV_TIME_FEATURES: - val[0] =3D SMCCC_RET_SUCCESS; + if (kvm_arm_fw_reg_feat_enabled( + hvc_desc->hvc_std_hyp_bmap, + KVM_REG_ARM_STD_HYP_BIT_PV_TIME)) + val[0] =3D SMCCC_RET_SUCCESS; break; } break; @@ -179,6 +187,7 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1, KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, KVM_REG_ARM_STD_BMAP, + KVM_REG_ARM_STD_HYP_BMAP, }; =20 void kvm_arm_init_hypercalls(struct kvm *kvm) @@ -186,6 +195,7 @@ void kvm_arm_init_hypercalls(struct kvm *kvm) struct kvm_hvc_desc *hvc_desc =3D &kvm->arch.hvc_desc; =20 hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; + hvc_desc->hvc_std_hyp_bmap =3D ARM_SMCCC_STD_HYP_FEATURES; } =20 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) @@ -272,6 +282,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_STD_BMAP: val =3D READ_ONCE(hvc_desc->hvc_std_bmap); break; + case KVM_REG_ARM_STD_HYP_BMAP: + val =3D READ_ONCE(hvc_desc->hvc_std_hyp_bmap); + break; default: return -ENOENT; } @@ -294,6 +307,10 @@ static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vc= pu, u64 reg_id, u64 val) fw_reg_bmap =3D &hvc_desc->hvc_std_bmap; fw_reg_features =3D ARM_SMCCC_STD_FEATURES; break; + case KVM_REG_ARM_STD_HYP_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_std_hyp_bmap; + fw_reg_features =3D ARM_SMCCC_STD_HYP_FEATURES; + break; default: return -ENOENT; } @@ -398,6 +415,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) =20 return 0; case KVM_REG_ARM_STD_BMAP: + case KVM_REG_ARM_STD_HYP_BMAP: return kvm_arm_set_fw_reg_bmap(vcpu, reg_id, val); default: return -ENOENT; diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index 64d30b452809..a1cb6e839c74 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -9,6 +9,9 @@ #define ARM_SMCCC_STD_FEATURES \ GENMASK_ULL(KVM_REG_ARM_STD_BMAP_BIT_MAX, 0) =20 +#define ARM_SMCCC_STD_HYP_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D673C433EF for ; Thu, 24 Feb 2022 17:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231911AbiBXR2R (ORCPT ); Thu, 24 Feb 2022 12:28:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231754AbiBXR1L (ORCPT ); Thu, 24 Feb 2022 12:27:11 -0500 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70AE9278CB7 for ; Thu, 24 Feb 2022 09:26:24 -0800 (PST) Received: by mail-pj1-x1049.google.com with SMTP id y1-20020a17090a644100b001bc901aba0dso1607246pjm.8 for ; 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Thu, 24 Feb 2022 09:26:23 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:53 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-8-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 07/13] KVM: arm64: Add vendor hypervisor firmware register From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the firmware register to hold the vendor specific hypervisor service calls (owner value 6) as a bitmap. The bitmap represents the features that'll be enabled for the guest, as configured by the user-space. Currently, this includes support only for Precision Time Protocol (PTP), represented by bit-0. The register is also added to the kvm_arm_vm_scope_fw_regs[] list as it maintains its state per-VM. Signed-off-by: Raghavendra Rao Ananta --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/uapi/asm/kvm.h | 4 ++++ arch/arm64/kvm/guest.c | 1 + arch/arm64/kvm/hypercalls.c | 22 +++++++++++++++++++++- include/kvm/arm_hypercalls.h | 3 +++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 318148b69279..d999456c4604 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -106,10 +106,12 @@ struct kvm_arch_memory_slot { * * @hvc_std_bmap: Bitmap of standard secure service calls * @hvc_std_hyp_bmap: Bitmap of standard hypervisor service calls + * @hvc_vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls */ struct kvm_hvc_desc { u64 hvc_std_bmap; u64 hvc_std_hyp_bmap; + u64 hvc_vendor_hyp_bmap; }; =20 struct kvm_arch { diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 9a2caead7359..ed470bde13d8 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -299,6 +299,10 @@ struct kvm_arm_copy_mte_tags { #define KVM_REG_ARM_STD_HYP_BIT_PV_TIME BIT(0) #define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ =20 +#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_BMAP_REG(2) +#define KVM_REG_ARM_VENDOR_HYP_BIT_PTP BIT(0) +#define KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX 0 /* Last valid bit */ + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) =20 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index c42426d6137e..fc3656f91aed 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -67,6 +67,7 @@ static const u64 kvm_arm_vm_scope_fw_regs[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, + KVM_REG_ARM_VENDOR_HYP_BMAP, }; =20 /** diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index ebc0cc26cf2e..5c5098c8f1f9 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -79,6 +79,9 @@ static bool kvm_hvc_call_supported(struct kvm_vcpu *vcpu,= u32 func_id) case ARM_SMCCC_HV_PV_TIME_ST: return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_std_hyp_bmap, KVM_REG_ARM_STD_HYP_BIT_PV_TIME); + case ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID: + return kvm_arm_fw_reg_feat_enabled(hvc_desc->hvc_vendor_hyp_bmap, + KVM_REG_ARM_VENDOR_HYP_BIT_PTP); default: /* By default, allow the services that aren't listed here */ return true; @@ -162,7 +165,14 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) break; case ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID: val[0] =3D BIT(ARM_SMCCC_KVM_FUNC_FEATURES); - val[0] |=3D BIT(ARM_SMCCC_KVM_FUNC_PTP); + + /* + * The feature bits exposed to user-space doesn't include + * ARM_SMCCC_KVM_FUNC_FEATURES. However, we expose this to + * the guest as bit-0. Hence, left-shift the user-space + * exposed bitmap by 1 to accommodate this. + */ + val[0] |=3D hvc_desc->hvc_vendor_hyp_bmap << 1; break; case ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID: kvm_ptp_get_time(vcpu, val); @@ -188,6 +198,7 @@ static const u64 kvm_arm_fw_reg_ids[] =3D { KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2, KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, + KVM_REG_ARM_VENDOR_HYP_BMAP, }; =20 void kvm_arm_init_hypercalls(struct kvm *kvm) @@ -196,6 +207,7 @@ void kvm_arm_init_hypercalls(struct kvm *kvm) =20 hvc_desc->hvc_std_bmap =3D ARM_SMCCC_STD_FEATURES; hvc_desc->hvc_std_hyp_bmap =3D ARM_SMCCC_STD_HYP_FEATURES; + hvc_desc->hvc_vendor_hyp_bmap =3D ARM_SMCCC_VENDOR_HYP_FEATURES; } =20 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) @@ -285,6 +297,9 @@ int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) case KVM_REG_ARM_STD_HYP_BMAP: val =3D READ_ONCE(hvc_desc->hvc_std_hyp_bmap); break; + case KVM_REG_ARM_VENDOR_HYP_BMAP: + val =3D READ_ONCE(hvc_desc->hvc_vendor_hyp_bmap); + break; default: return -ENOENT; } @@ -311,6 +326,10 @@ static int kvm_arm_set_fw_reg_bmap(struct kvm_vcpu *vc= pu, u64 reg_id, u64 val) fw_reg_bmap =3D &hvc_desc->hvc_std_hyp_bmap; fw_reg_features =3D ARM_SMCCC_STD_HYP_FEATURES; break; + case KVM_REG_ARM_VENDOR_HYP_BMAP: + fw_reg_bmap =3D &hvc_desc->hvc_vendor_hyp_bmap; + fw_reg_features =3D ARM_SMCCC_VENDOR_HYP_FEATURES; + break; default: return -ENOENT; } @@ -416,6 +435,7 @@ int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return 0; case KVM_REG_ARM_STD_BMAP: case KVM_REG_ARM_STD_HYP_BMAP: + case KVM_REG_ARM_VENDOR_HYP_BMAP: return kvm_arm_set_fw_reg_bmap(vcpu, reg_id, val); default: return -ENOENT; diff --git a/include/kvm/arm_hypercalls.h b/include/kvm/arm_hypercalls.h index a1cb6e839c74..91be758ca58e 100644 --- a/include/kvm/arm_hypercalls.h +++ b/include/kvm/arm_hypercalls.h @@ -12,6 +12,9 @@ #define ARM_SMCCC_STD_HYP_FEATURES \ GENMASK_ULL(KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX, 0) =20 +#define ARM_SMCCC_VENDOR_HYP_FEATURES \ + GENMASK_ULL(KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX, 0) + int kvm_hvc_call_handler(struct kvm_vcpu *vcpu); =20 static inline u32 smccc_get_function(struct kvm_vcpu *vcpu) --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6544AC433F5 for ; Thu, 24 Feb 2022 17:27:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231905AbiBXR1c (ORCPT ); Thu, 24 Feb 2022 12:27:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231768AbiBXR1L (ORCPT ); Thu, 24 Feb 2022 12:27:11 -0500 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC139278CBF for ; Thu, 24 Feb 2022 09:26:26 -0800 (PST) Received: by mail-pl1-x64a.google.com with SMTP id x18-20020a170902b41200b0014fc2665bddso1423532plr.0 for ; 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Thu, 24 Feb 2022 09:26:26 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:54 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-9-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 08/13] Docs: KVM: Add doc for the bitmap firmware registers From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the documentation for the bitmap firmware registers in psci.rst. This includes the details for KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, and KVM_REG_ARM_VENDOR_HYP_BMAP registers. Since the document is growing to carry other hypercall related information, make necessary adjustments to present the document in a generic sense, rather than being PSCI focused. Signed-off-by: Raghavendra Rao Ananta --- Documentation/virt/kvm/arm/psci.rst | 83 ++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 18 deletions(-) diff --git a/Documentation/virt/kvm/arm/psci.rst b/Documentation/virt/kvm/a= rm/psci.rst index d52c2e83b5b8..bc5c2886ca23 100644 --- a/Documentation/virt/kvm/arm/psci.rst +++ b/Documentation/virt/kvm/arm/psci.rst @@ -1,32 +1,32 @@ .. SPDX-License-Identifier: GPL-2.0 =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Power State Coordination Interface (PSCI) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +ARM Hypercall Interface +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -KVM implements the PSCI (Power State Coordination Interface) -specification in order to provide services such as CPU on/off, reset -and power-off to the guest. +KVM handles the hypercall services as requested by the guests. New hyperca= ll +services are regularly made available by the ARM specification or by KVM (= as +vendor services) if they make sense from a virtualization point of view. =20 -The PSCI specification is regularly updated to provide new features, -and KVM implements these updates if they make sense from a virtualization -point of view. - -This means that a guest booted on two different versions of KVM can -observe two different "firmware" revisions. This could cause issues if -a given guest is tied to a particular PSCI revision (unlikely), or if -a migration causes a different PSCI version to be exposed out of the -blue to an unsuspecting guest. +This means that a guest booted on two different versions of KVM can observe +two different "firmware" revisions. This could cause issues if a given gue= st +is tied to a particular version of a hypercall service, or if a migration +causes a different version to be exposed out of the blue to an unsuspecting +guest. =20 In order to remedy this situation, KVM exposes a set of "firmware pseudo-registers" that can be manipulated using the GET/SET_ONE_REG interface. These registers can be saved/restored by userspace, and set -to a convenient value if required. +to a convenient value as required. =20 -The following register is defined: +The following registers are defined: =20 * KVM_REG_ARM_PSCI_VERSION: =20 + KVM implements the PSCI (Power State Coordination Interface) + specification in order to provide services such as CPU on/off, reset + and power-off to the guest. + - Only valid if the vcpu has the KVM_ARM_VCPU_PSCI_0_2 feature set (and thus has already been initialized) - Returns the current PSCI version on GET_ONE_REG (defaulting to the @@ -74,4 +74,51 @@ The following register is defined: KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED: The workaround is always active on this vCPU or it is not needed. =20 -.. [1] https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmw= are_interfaces_for_mitigating_CVE-2017-5715.pdf +Contrary to the above registers, the following registers exposes the hyper= call +services in the form of a feature-bitmap. This bitmap is translated to the +services that are exposed to the guest. There is a register defined per se= rvice +call owner and can be accessed via GET/SET_ONE_REG interface. + +By default, these registers are set with the upper limit of the features t= hat +are supported. User-space can discover this configuration via GET_ONE_REG.= If +unsatisfied, the user-space can write back the desired bitmap back via +SET_ONE_REG. The features for the registers that are untouched, probably b= ecause +userspace isn't aware of them, will be exposed as is to the guest. + +The psuedo-firmware bitmap register are as follows: + +* KVM_REG_ARM_STD_BMAP: + Controls the bitmap of the ARM Standard Secure Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_STD_BIT_TRNG_V1_0: + The bit represents the services offered under v1.0 of ARM True Random + Number Generator (TRNG) specification, ARM DEN0098. + +* KVM_REG_ARM_STD_HYP_BMAP: + Controls the bitmap of the ARM Standard Hypervisor Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_STD_HYP_BIT_PV_TIME: + The bit represents the Paravirtualized Time service as represented by + ARM DEN0057A. + +* KVM_REG_ARM_VENDOR_HYP_BMAP: + Controls the bitmap of the Vendor specific Hypervisor Service Calls. + + The following bits are accepted: + + KVM_REG_ARM_VENDOR_HYP_BIT_PTP: + The bit represents the Precision Time Protocol KVM service. + +Errors: + + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + -ENOENT Unknown register accessed. + -EBUSY Attempt a 'write' to the register after the VM has started. + -EINVAL Invalid bitmap written to the register. + =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. [1] https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmw= are_interfaces_for_mitigating_CVE-2017-5715.pdf \ No newline at end of file --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0602C433EF for ; Thu, 24 Feb 2022 17:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiBXR1g (ORCPT ); Thu, 24 Feb 2022 12:27:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbiBXR1M (ORCPT ); Thu, 24 Feb 2022 12:27:12 -0500 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30116279447 for ; Thu, 24 Feb 2022 09:26:29 -0800 (PST) Received: by mail-pf1-x449.google.com with SMTP id b6-20020a621b06000000b004e1453487efso1605523pfb.22 for ; Thu, 24 Feb 2022 09:26:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=/yI+1iHLFKapqIM71Fi477KtJQIbrAd1wE7m0DoVTrg=; b=BX44DBoUoT7DxSh0J1USD87fHZhHxbcIv+UIN+p9yTigBQ9rkC70b9lUdxzXby4YQD KMd52RGWYjaaW1mHhmPX5yT+JeYaFygpZY0qhfH1XvQg4NW+V/3WQmadTFO0LuyUmjqI Lf4X1oVugf+w+6UILacWvqCQD699Y1sZ4jHxPCht5kQp0Z7gmZzjkNCEjNdcP+9Z/PgR xKtXomjP+kvoY2+igh5Qgl1oXuX44weeSxLg17woXyG242n2H2rrMhMI9uPz0uyVFxom j9u76QtEXmUQj2ImKEWLR1zsNdb+nKTskysG+XXZFqOdlVy/AMw05nrczKv2DjXofDpL i+ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=/yI+1iHLFKapqIM71Fi477KtJQIbrAd1wE7m0DoVTrg=; b=1+6w7TVLAmnrcFgQQthcHZ2qY0p5wOUC9hllb5DD8PrIgbnPM+Hx0rJLSPFsFxImFG 1FzHttJg+tsEtZT8ljNbbwY11d2ZuG92PLhHHrz7HpnKViZsTJEuki2qvCjgFEbyjlto Ism4DsZFMJlPk7JerqEXadyk+W5SySSk/8dF1WJNFqLV2CQ9YMTgTJBJoNwzd0TXMOqJ ezUNoFbIVLfCF/oPcBM7wPloo6F3DOOmaABLJF9XaM0scH7ltGNCfU4A3OpVWMaI2VfL oGjLy55xCQoG5h5SRptNZqFXDN1ElYye6+LnVjseie1x46G/qY4JKhl/doK7l/JyU6YB 6Btw== X-Gm-Message-State: AOAM5310GhFCTSib+TiHuRL/9zNZGayJj59IVVpnQwfPKXsx8whB/TKE P6+UMogT3ZxD0OXleIlMffPENzGZMW9I X-Google-Smtp-Source: ABdhPJyekDaVQfujrpGwc51nGDLUID+Ox5wvRHROwF3BH9GvfkusWzxxeNEpolKSk+8ZEG7ImKIZOKSGzN1P X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:700b:b0:148:ee33:70fe with SMTP id y11-20020a170902700b00b00148ee3370femr3741547plk.38.1645723588637; Thu, 24 Feb 2022 09:26:28 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:55 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-10-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 09/13] Docs: KVM: Rename psci.rst to hypercalls.rst From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the doc now covers more of general hypercalls' details, rather than just PSCI, rename the file to a more appropriate name- hypercalls.rst. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Oliver Upton --- Documentation/virt/kvm/arm/{psci.rst =3D> hypercalls.rst} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/virt/kvm/arm/{psci.rst =3D> hypercalls.rst} (100%) diff --git a/Documentation/virt/kvm/arm/psci.rst b/Documentation/virt/kvm/a= rm/hypercalls.rst similarity index 100% rename from Documentation/virt/kvm/arm/psci.rst rename to Documentation/virt/kvm/arm/hypercalls.rst --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50A32C433EF for ; Thu, 24 Feb 2022 17:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231560AbiBXR2O (ORCPT ); Thu, 24 Feb 2022 12:28:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231790AbiBXR1M (ORCPT ); Thu, 24 Feb 2022 12:27:12 -0500 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AD2BE90 for ; Thu, 24 Feb 2022 09:26:31 -0800 (PST) Received: by mail-pl1-x64a.google.com with SMTP id p5-20020a170902bd0500b00148cb2d29ecso1419383pls.4 for ; Thu, 24 Feb 2022 09:26:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=QgbZvK2OelZR+0slSn0oup5LSIqRFfP5HH0xakkbQ6w=; b=Lp9S001wVZKumLnKiYdg5/2/uqFBt8Q08r4iWj4R52Lln+D6Uv3QDcDGCzRCLJ/Zz5 4mRMpYYJ143XdWGhmIQq/sMsanQQxpkHbgcTEjzYz0LArNd2914JkTg9haSVbRQKOWvj SPfKcZ9cdqDDS9hkaAYmkoTPTi+R/bxI7+XO6T38ukpTXlvjMbX9Ht9gMR1NgxezI7nq luV7w7eiImB1E3qBilLWKb5GrWvl5x7HuQIXy3oLGwXQ/XR9vgRZteqEuqlHtJU9NNza rl8lhTtJgU241kVvdAMWAT2NrjO1iwjwjwnM+OnWMVi/vuNgc1+mcIwNQ3SvoNZcuJDy wHjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=QgbZvK2OelZR+0slSn0oup5LSIqRFfP5HH0xakkbQ6w=; b=mZvKS1Oj012Q+tdhDiYjGAelUTfsLoR0Ot4y3CxdI1NbZ5uyji4XVdFfLhvMeeYYM0 miyjVdUk7FOLetdMW5/WxJFMw7g5EQQmuTk9FKH26rbrhhbRKIhpWWSzH2X4CEwS6FYR yVACUFdomBOTEXzTiDSvgNSSo+90nQt/TAOG51RTrZODpcLMkxeldvg661WpdsI3WfGa x4VnZrgcmdEuCDRxfBCa3G7+nQK2lgWeg11pyoVnhsBbuZ/2iN5BAZ7PncgQOrzH1gYP 5H+1CNQeTy1jhSMDSZBx/tgFi7ej5xYU590e92aJaVBJh519HN5+9sMFwkpsu+fLSxwd 4v8A== X-Gm-Message-State: AOAM530anPXevX5hiMIgmsZ7iQ8ZKGcsbYD7futL2NH+czMrTzAfYKTM J+uY1138/aAkMo0EhQ2r4yPFxZo6DTIo X-Google-Smtp-Source: ABdhPJxW0ZC3y6jO1H/YjjkgEZ96qgNVN6qZHewqJNTPXXTh2+qkgZzrfvIUvtDka7Ycif5aizVS9DjWhAWE X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:ce05:b0:14f:8ba2:2339 with SMTP id k5-20020a170902ce0500b0014f8ba22339mr3560434plg.152.1645723590707; Thu, 24 Feb 2022 09:26:30 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:56 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-11-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 10/13] tools: Import ARM SMCCC definitions From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Import the standard SMCCC definitions from include/linux/arm-smccc.h. Signed-off-by: Raghavendra Rao Ananta --- tools/include/linux/arm-smccc.h | 188 ++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 tools/include/linux/arm-smccc.h diff --git a/tools/include/linux/arm-smccc.h b/tools/include/linux/arm-smcc= c.h new file mode 100644 index 000000000000..a11c0bbabd5b --- /dev/null +++ b/tools/include/linux/arm-smccc.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, Linaro Limited + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * https://developer.arm.com/docs/den0028/latest + * + * This code is up-to-date with version DEN 0028 C + */ + +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_STANDARD_HYP 5 +#define ARM_SMCCC_OWNER_VENDOR_HYP 6 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01 + +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ + +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 +#define ARM_SMCCC_VERSION_1_2 0x10002 +#define ARM_SMCCC_VERSION_1_3 0x10003 + +#define ARM_SMCCC_1_3_SVE_HINT 0x10000 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + +#define ARM_SMCCC_ARCH_SOC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 2) + +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + +#define ARM_SMCCC_ARCH_WORKAROUND_2 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x7fff) + +#define ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_FUNC_QUERY_CALL_UID) + +/* KVM UID value: 28b46fb6-2ec5-11e9-a9ca-4b564d003a74 */ +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 0xb66fb428U +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 0xe911c52eU +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 0x564bcaa9U +#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3 0x743a004dU + +/* KVM "vendor specific" services */ +#define ARM_SMCCC_KVM_FUNC_FEATURES 0 +#define ARM_SMCCC_KVM_FUNC_PTP 1 +#define ARM_SMCCC_KVM_FUNC_FEATURES_2 127 +#define ARM_SMCCC_KVM_NUM_FUNCS 128 + +#define ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_KVM_FUNC_FEATURES) + +#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED 1 + +/* + * ptp_kvm is a feature used for time sync between vm and host. + * ptp_kvm module in guest kernel will get service from host using + * this hypercall ID. + */ +#define ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + ARM_SMCCC_KVM_FUNC_PTP) + +/* ptp_kvm counter type ID */ +#define KVM_PTP_VIRT_COUNTER 0 +#define KVM_PTP_PHYS_COUNTER 1 + +/* Paravirtualised time calls (defined by ARM DEN0057A) */ +#define ARM_SMCCC_HV_PV_TIME_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD_HYP, \ + 0x20) + +#define ARM_SMCCC_HV_PV_TIME_ST \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD_HYP, \ + 0x21) + +/* TRNG entropy source calls (defined by ARM DEN0098) */ +#define ARM_SMCCC_TRNG_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x50) + +#define ARM_SMCCC_TRNG_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x51) + +#define ARM_SMCCC_TRNG_GET_UUID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x52) + +#define ARM_SMCCC_TRNG_RND32 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + +#define ARM_SMCCC_TRNG_RND64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0x53) + +/* + * Return codes defined in ARM DEN 0070A + * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C + */ +#define SMCCC_RET_SUCCESS 0 +#define SMCCC_RET_NOT_SUPPORTED -1 +#define SMCCC_RET_NOT_REQUIRED -2 +#define SMCCC_RET_INVALID_PARAMETER -3 + +#endif /*__LINUX_ARM_SMCCC_H*/ --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=KxLF7qzKbc8UFtk7tO6zSgT4pjqe2yY92U69kuJWElE=; b=Ibq2L/kDegT2ECNcaQXPAs7djEODMNl6Odaya6jgnPWZwo8ddlFwZQf5S2DV1lDKXh KvqDVlQRjlXs0r+9hv5s4YACXuw+mZH8LtJ9PjnUl+m/ZKgOJhNu5UTG/sW92wXtuJ53 uTA70vfKFeeqKKcz3kmCuUJDCYC2jsj1x3VKD3fMxhwpYqXFxkE6Ryi/kYomzSshDYFb zaCFurXQqXvGlWD9SuSkzApAxF7z4m7vGgt6OanmwFR3UcAlwoV4m/vf2Dl/KySQsaX/ ID6OoI+rC9i9ZACeBS2AWlYwc3JMYgiMB0VLfj+e4bNJ3K/2wDtWal25WRCbJUUBRdW1 09hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=KxLF7qzKbc8UFtk7tO6zSgT4pjqe2yY92U69kuJWElE=; b=SOPfht0Sk5NXx8EaozPUIUeIF1EqQZF4s2xvAy5C0HsrQPRSfUR1hC9nEaIqaRsX5B 6TgiPL4YnSkodR2wQd7gf9HpWsiifi4pWbQfOP6J5ERERRbNGZViSkcCGng9D/1KkYp1 Lih3i3GkpKCX2WgVpWd+XPRjmEydbUj/4fFbzPTDbKNKKe7F4GNUKgAkxK1GFj/iFK/Y MVCOsbBgVNW1KllneqBh33QwOwmgib2Qetc4CE9/i8wHqP+E/vUzYs8n74NYr4f7Svdh wPeRshOFAbKzzRB/uygEW/UEMPF2sV96dheOG/ZJn3J3RM2r1RGr4mF3TkhfoY4SOivM Xxig== X-Gm-Message-State: AOAM531gGX6+zeX/QDkxjoesSEjlez3c2h691wJ3xsuyQHNipdR4dCcN XbzKDdPd2tEFNNLK19yEUu9zARUPWYFZ X-Google-Smtp-Source: ABdhPJyrVMqrzObbtdrqsKfy7PVH706+lroyD/W5B1nltv6iTYOALVQlwfiPpkDn123mnsFrgGkxxJ5C3gkx X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:902:d345:b0:14f:ee29:5ee6 with SMTP id l5-20020a170902d34500b0014fee295ee6mr3440637plk.102.1645723593017; Thu, 24 Feb 2022 09:26:33 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:57 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-12-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 11/13] selftests: KVM: aarch64: Introduce hypercall ABI test From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a KVM selftest to check the hypercall interface for arm64 platforms. The test validates the user-space's IOCTL interface to read/write the psuedo-firmware registers as well as its effects on the guest upon certain configurations. Signed-off-by: Raghavendra Rao Ananta --- tools/testing/selftests/kvm/.gitignore | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/hypercalls.c | 376 ++++++++++++++++++ 3 files changed, 378 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/hypercalls.c diff --git a/tools/testing/selftests/kvm/.gitignore b/tools/testing/selftes= ts/kvm/.gitignore index ac69108d9ffd..f13c33fcd733 100644 --- a/tools/testing/selftests/kvm/.gitignore +++ b/tools/testing/selftests/kvm/.gitignore @@ -2,6 +2,7 @@ /aarch64/arch_timer /aarch64/debug-exceptions /aarch64/get-reg-list +/aarch64/hypercalls /aarch64/psci_test /aarch64/vgic_init /aarch64/vgic_irq diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 2a27c09b22ae..2181bdd5b09c 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -102,6 +102,7 @@ TEST_GEN_PROGS_x86_64 +=3D system_counter_offset_test TEST_GEN_PROGS_aarch64 +=3D aarch64/arch_timer TEST_GEN_PROGS_aarch64 +=3D aarch64/debug-exceptions TEST_GEN_PROGS_aarch64 +=3D aarch64/get-reg-list +TEST_GEN_PROGS_aarch64 +=3D aarch64/hypercalls TEST_GEN_PROGS_aarch64 +=3D aarch64/psci_test TEST_GEN_PROGS_aarch64 +=3D aarch64/vgic_init TEST_GEN_PROGS_aarch64 +=3D aarch64/vgic_irq diff --git a/tools/testing/selftests/kvm/aarch64/hypercalls.c b/tools/testi= ng/selftests/kvm/aarch64/hypercalls.c new file mode 100644 index 000000000000..e4e3a286ff3e --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/hypercalls.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* hypercalls: Check the ARM64's psuedo-firmware bitmap register interface. + * + * The test validates the basic hypercall functionalities that are exposed + * via the psuedo-firmware bitmap register. This includes the registers' + * read/write behavior before and after the VM has started, and if the + * hypercalls are properly masked or unmasked to the guest when disabled or + * enabled from the KVM userspace, respectively. + */ + +#include +#include +#include +#include + +#include "processor.h" + +#define FW_REG_ULIMIT_VAL(max_feat_bit) (GENMASK_ULL(max_feat_bit, 0)) + +struct kvm_fw_reg_info { + uint64_t reg; /* Register definition */ + uint64_t max_feat_bit; /* Bit that represents the upper limit of the feat= ure-map */ +}; + +#define FW_REG_INFO(r, bit_max) \ + { \ + .reg =3D r, \ + .max_feat_bit =3D bit_max, \ + } + +static const struct kvm_fw_reg_info fw_reg_info[] =3D { + FW_REG_INFO(KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_BMAP_BIT_MAX), + FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP, KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX), + FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP, KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_= MAX), +}; + +enum test_stage { + TEST_STAGE_REG_IFACE, + TEST_STAGE_HVC_IFACE_FEAT_DISABLED, + TEST_STAGE_HVC_IFACE_FEAT_ENABLED, + TEST_STAGE_HVC_IFACE_FALSE_INFO, + TEST_STAGE_END, +}; + +static int stage; + +struct test_hvc_info { + uint32_t func_id; + int64_t arg0; + + void (*test_hvc_disabled)(const struct test_hvc_info *hc_info, + struct arm_smccc_res *res); + void (*test_hvc_enabled)(const struct test_hvc_info *hc_info, + struct arm_smccc_res *res); +}; + +#define TEST_HVC_INFO(f, a0, test_disabled, test_enabled) \ + { \ + .func_id =3D f, \ + .arg0 =3D a0, \ + .test_hvc_disabled =3D test_disabled, \ + .test_hvc_enabled =3D test_enabled, \ + } + +static void +test_ptp_feat_hvc_disabled(const struct test_hvc_info *hc_info, struct arm= _smccc_res *res) +{ + GUEST_ASSERT_3((res->a0 & BIT(ARM_SMCCC_KVM_FUNC_PTP)) =3D=3D 0, + res->a0, hc_info->func_id, hc_info->arg0); +} + +static void +test_ptp_feat_hvc_enabled(const struct test_hvc_info *hc_info, struct arm_= smccc_res *res) +{ + GUEST_ASSERT_3((res->a0 & BIT(ARM_SMCCC_KVM_FUNC_PTP)) !=3D 0, + res->a0, hc_info->func_id, hc_info->arg0); +} + +static const struct test_hvc_info hvc_info[] =3D { + /* KVM_REG_ARM_STD_BMAP: KVM_REG_ARM_STD_BIT_TRNG_V1_0 */ + TEST_HVC_INFO(ARM_SMCCC_TRNG_VERSION, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND64, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_GET_UUID, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_RND32, 0, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_TRNG_RND64, 0, NULL, NULL), + + /* KVM_REG_ARM_STD_HYP_BMAP: KVM_REG_ARM_STD_HYP_BIT_PV_TIME */ + TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_HV_PV_TIME_FEATURES, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, + ARM_SMCCC_HV_PV_TIME_ST, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_ST, 0, NULL, NULL), + + /* KVM_REG_ARM_VENDOR_HYP_BMAP: KVM_REG_ARM_VENDOR_HYP_BIT_PTP */ + TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID, + ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, + test_ptp_feat_hvc_disabled, test_ptp_feat_hvc_enabled), + TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, + KVM_PTP_VIRT_COUNTER, NULL, NULL), +}; + +/* Feed false hypercall info to test the KVM behavior */ +static const struct test_hvc_info false_hvc_info[] =3D { + /* Feature support check against a different family of hypercalls */ + TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, + ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_TRNG_RND64, NULL, NULL), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, + ARM_SMCCC_TRNG_RND64, NULL, NULL), +}; + +static void guest_test_hvc(const struct test_hvc_info *hc_info) +{ + unsigned int i; + struct arm_smccc_res res; + unsigned int hvc_info_arr_sz; + + hvc_info_arr_sz =3D + hc_info =3D=3D hvc_info ? ARRAY_SIZE(hvc_info) : ARRAY_SIZE(false_hvc_inf= o); + + for (i =3D 0; i < hvc_info_arr_sz; i++, hc_info++) { + + memset(&res, 0, sizeof(res)); + smccc_hvc(hc_info->func_id, hc_info->arg0, 0, 0, 0, 0, 0, 0, &res); + + switch (stage) { + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + if (hc_info->test_hvc_disabled) + hc_info->test_hvc_disabled(hc_info, &res); + else + GUEST_ASSERT_3(res.a0 =3D=3D SMCCC_RET_NOT_SUPPORTED, + res.a0, hc_info->func_id, hc_info->arg0); + break; + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + if (hc_info->test_hvc_enabled) + hc_info->test_hvc_enabled(hc_info, &res); + else + GUEST_ASSERT_3(res.a0 !=3D SMCCC_RET_NOT_SUPPORTED, + res.a0, hc_info->func_id, hc_info->arg0); + break; + case TEST_STAGE_HVC_IFACE_FALSE_INFO: + GUEST_ASSERT_3(res.a0 =3D=3D SMCCC_RET_NOT_SUPPORTED, + res.a0, hc_info->func_id, hc_info->arg0); + break; + default: + GUEST_ASSERT_1(0, stage); + } + } +} + +static void guest_code(void) +{ + while (stage !=3D TEST_STAGE_END) { + switch (stage) { + case TEST_STAGE_REG_IFACE: + break; + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + guest_test_hvc(hvc_info); + break; + case TEST_STAGE_HVC_IFACE_FALSE_INFO: + guest_test_hvc(false_hvc_info); + break; + default: + GUEST_ASSERT_1(0, stage); + } + + GUEST_SYNC(stage); + } + + GUEST_DONE(); +} + +static int set_fw_reg(struct kvm_vm *vm, uint64_t id, uint64_t val) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_FW_REG(id), + .addr =3D (uint64_t)&val, + }; + + return _vcpu_ioctl(vm, 0, KVM_SET_ONE_REG, ®); +} + +static void get_fw_reg(struct kvm_vm *vm, uint64_t id, uint64_t *addr) +{ + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM_FW_REG(id), + .addr =3D (uint64_t)addr, + }; + + return vcpu_ioctl(vm, 0, KVM_GET_ONE_REG, ®); +} + +struct st_time { + uint32_t rev; + uint32_t attr; + uint64_t st_time; +}; + +#define STEAL_TIME_SIZE ((sizeof(struct st_time) + 63) & ~63) +#define ST_GPA_BASE (1 << 30) + +static void steal_time_init(struct kvm_vm *vm) +{ + uint64_t st_ipa =3D (ulong)ST_GPA_BASE; + unsigned int gpages; + struct kvm_device_attr dev =3D { + .group =3D KVM_ARM_VCPU_PVTIME_CTRL, + .attr =3D KVM_ARM_VCPU_PVTIME_IPA, + .addr =3D (uint64_t)&st_ipa, + }; + + gpages =3D vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE); + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, ST_GPA_BASE, 1, gpa= ges, 0); + + vcpu_ioctl(vm, 0, KVM_SET_DEVICE_ATTR, &dev); +} + +static void test_fw_regs_before_vm_start(struct kvm_vm *vm) +{ + uint64_t val; + unsigned int i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(fw_reg_info); i++) { + const struct kvm_fw_reg_info *reg_info =3D &fw_reg_info[i]; + + /* First read should be an upper limit of the features supported */ + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), + "Expected all the features to be set for reg: 0x%lx; expected: 0x%llx; = read: 0x%lx\n", + reg_info->reg, GENMASK_ULL(reg_info->max_feat_bit, 0), val); + + /* Test 'write' by disabling all the features of the register map */ + ret =3D set_fw_reg(vm, reg_info->reg, 0); + TEST_ASSERT(ret =3D=3D 0, + "Failed to clear all the features of reg: 0x%lx; ret: %d\n", + reg_info->reg, errno); + + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D 0, + "Expected all the features to be cleared for reg: 0x%lx\n", reg_info->r= eg); + + /* + * Test enabling a feature that's not supported. + * Avoid this check if all the bits are occupied. + */ + if (reg_info->max_feat_bit < 63) { + ret =3D set_fw_reg(vm, reg_info->reg, BIT(reg_info->max_feat_bit + 1)); + TEST_ASSERT(ret !=3D 0 && errno =3D=3D EINVAL, + "Unexpected behavior or return value (%d) while setting an unsupported = feature for reg: 0x%lx\n", + errno, reg_info->reg); + } + } +} + +static void test_fw_regs_after_vm_start(struct kvm_vm *vm) +{ + uint64_t val; + unsigned int i; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(fw_reg_info); i++) { + const struct kvm_fw_reg_info *reg_info =3D &fw_reg_info[i]; + + /* + * Before starting the VM, the test clears all the bits. + * Check if that's still the case. + */ + get_fw_reg(vm, reg_info->reg, &val); + TEST_ASSERT(val =3D=3D 0, + "Expected all the features to be cleared for reg: 0x%lx\n", + reg_info->reg); + + /* + * Test setting the last read value. KVM should allow this + * even if VM has started running. + */ + ret =3D set_fw_reg(vm, reg_info->reg, val); + TEST_ASSERT(ret =3D=3D 0, + "Failed to set the register with previously read value after Vm start f= or reg: 0x%lx; ret: %d\n", + reg_info->reg, errno); + + /* + * Set all the features for this register again. KVM shouldn't + * allow this as the VM is running. + */ + ret =3D set_fw_reg(vm, reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_fe= at_bit)); + TEST_ASSERT(ret !=3D 0 && errno =3D=3D EBUSY, + "Unexpected behavior or return value (%d) while setting a feature while = VM is running for reg: 0x%lx\n", + errno, reg_info->reg); + } +} + +static struct kvm_vm *test_vm_create(void) +{ + struct kvm_vm *vm; + + vm =3D vm_create_default(0, 0, guest_code); + + ucall_init(vm, NULL); + steal_time_init(vm); + + return vm; +} + +static struct kvm_vm *test_guest_stage(struct kvm_vm *vm) +{ + struct kvm_vm *ret_vm =3D vm; + + pr_debug("Stage: %d\n", stage); + + switch (stage) { + case TEST_STAGE_REG_IFACE: + test_fw_regs_after_vm_start(vm); + break; + case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: + /* Start a new VM so that all the features are now enabled by default */ + kvm_vm_free(vm); + ret_vm =3D test_vm_create(); + break; + case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: + case TEST_STAGE_HVC_IFACE_FALSE_INFO: + break; + default: + TEST_FAIL("Unknown test stage: %d\n", stage); + } + + stage++; + sync_global_to_guest(vm, stage); + + return ret_vm; +} + +static void test_run(void) +{ + struct kvm_vm *vm; + struct ucall uc; + bool guest_done =3D false; + + vm =3D test_vm_create(); + + test_fw_regs_before_vm_start(vm); + + while (!guest_done) { + vcpu_run(vm, 0); + + switch (get_ucall(vm, 0, &uc)) { + case UCALL_SYNC: + vm =3D test_guest_stage(vm); + break; + case UCALL_DONE: + guest_done =3D true; + break; + case UCALL_ABORT: + TEST_FAIL("%s at %s:%ld\n\tvalues: 0x%lx, 0x%lx; 0x%lx, stage: %u", + (const char *)uc.args[0], __FILE__, uc.args[1], + uc.args[2], uc.args[3], uc.args[4], stage); + break; + default: + TEST_FAIL("Unexpected guest exit\n"); + } + } + + kvm_vm_free(vm); +} + +int main(void) +{ + setbuf(stdout, NULL); + + test_run(); + return 0; +} --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07FDAC433EF for ; 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Thu, 24 Feb 2022 09:26:35 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:58 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-13-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 12/13] selftests: KVM: aarch64: hypercalls: Test with KVM_CAP_ARM_REG_SCOPE From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Upgrade the aarch64/hypercalls test to also consider the firmware register's scope information. Thus, run the test with the capability KVM_CAP_ARM_REG_SCOPE disabled and enabled. Signed-off-by: Raghavendra Rao Ananta --- .../selftests/kvm/aarch64/hypercalls.c | 83 +++++++++++++++++-- 1 file changed, 75 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/hypercalls.c b/tools/testi= ng/selftests/kvm/aarch64/hypercalls.c index e4e3a286ff3e..85818b91b4fb 100644 --- a/tools/testing/selftests/kvm/aarch64/hypercalls.c +++ b/tools/testing/selftests/kvm/aarch64/hypercalls.c @@ -29,7 +29,7 @@ struct kvm_fw_reg_info { .max_feat_bit =3D bit_max, \ } =20 -static const struct kvm_fw_reg_info fw_reg_info[] =3D { +static struct kvm_fw_reg_info fw_reg_info[] =3D { FW_REG_INFO(KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_BMAP_BIT_MAX), FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP, KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX), FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP, KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_= MAX), @@ -294,19 +294,78 @@ static void test_fw_regs_after_vm_start(struct kvm_vm= *vm) } } =20 -static struct kvm_vm *test_vm_create(void) +static bool test_reg_is_bmap_fw_reg(uint64_t reg) +{ + if ((reg & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_FW && + (reg & 0xffff) >=3D 0xff00) /* Bitmap firmware register space */ + return true; + + return false; +} + +static void test_fw_regs_encode_vm_scope(void) +{ + int i; + + /* + * Encode the scope as KVM_REG_ARM_SCOPE_VM for further use + * in KVM_SET_ONE_REG and KVM_GET_ONE_REG operations. + */ + for (i =3D 0; i < ARRAY_SIZE(fw_reg_info); i++) + fw_reg_info[i].reg |=3D (KVM_REG_ARM_SCOPE_VM << KVM_REG_ARM_SCOPE_SHIFT= ); +} + +static void test_validate_fw_regs(struct kvm_vm *vm, int scope) +{ + uint64_t i, reg; + int obtained_scope; + struct kvm_reg_list *reg_list; + + reg_list =3D vcpu_get_reg_list(vm, 0); + + for (i =3D 0; i < reg_list->n; i++) { + reg =3D reg_list->reg[i]; + if (!test_reg_is_bmap_fw_reg(reg)) + continue; + + /* + * Depending on KVM_CAP_ARM_REG_SCOPE, currently all the firmware + * bitmap registers are either completely VM-scoped or vCPU scoped. + */ + obtained_scope =3D (reg & KVM_REG_ARM_SCOPE_MASK) >> KVM_REG_ARM_SCOPE_S= HIFT; + TEST_ASSERT(obtained_scope =3D=3D scope, + "Incorrect scope detected for reg: %lx. Expected: %d; Obtained: %d\n", + reg, scope, obtained_scope); + } +} + +static struct kvm_vm *test_vm_create(int scope) { struct kvm_vm *vm; + struct kvm_enable_cap reg_scope_cap =3D { + .cap =3D KVM_CAP_ARM_REG_SCOPE, + }; + + if (scope =3D=3D KVM_REG_ARM_SCOPE_VM && !kvm_check_cap(KVM_CAP_ARM_REG_S= COPE)) { + print_skip("Capability KVM_CAP_ARM_REG_SCOPE unavailable\n"); + return NULL; + } =20 vm =3D vm_create_default(0, 0, guest_code); =20 ucall_init(vm, NULL); steal_time_init(vm); =20 + if (scope =3D=3D KVM_REG_ARM_SCOPE_VM) { + vm_enable_cap(vm, ®_scope_cap); + test_fw_regs_encode_vm_scope(); + } + return vm; } =20 -static struct kvm_vm *test_guest_stage(struct kvm_vm *vm) +static struct kvm_vm * +test_guest_stage(struct kvm_vm *vm, int scope) { struct kvm_vm *ret_vm =3D vm; =20 @@ -319,7 +378,7 @@ static struct kvm_vm *test_guest_stage(struct kvm_vm *v= m) case TEST_STAGE_HVC_IFACE_FEAT_DISABLED: /* Start a new VM so that all the features are now enabled by default */ kvm_vm_free(vm); - ret_vm =3D test_vm_create(); + ret_vm =3D test_vm_create(scope); break; case TEST_STAGE_HVC_IFACE_FEAT_ENABLED: case TEST_STAGE_HVC_IFACE_FALSE_INFO: @@ -334,14 +393,20 @@ static struct kvm_vm *test_guest_stage(struct kvm_vm = *vm) return ret_vm; } =20 -static void test_run(void) +static void test_run(int scope) { struct kvm_vm *vm; struct ucall uc; bool guest_done =3D false; =20 - vm =3D test_vm_create(); + vm =3D test_vm_create(scope); + if (!vm) + return; =20 + stage =3D TEST_STAGE_REG_IFACE; + sync_global_to_guest(vm, stage); + + test_validate_fw_regs(vm, scope); test_fw_regs_before_vm_start(vm); =20 while (!guest_done) { @@ -349,7 +414,7 @@ static void test_run(void) =20 switch (get_ucall(vm, 0, &uc)) { case UCALL_SYNC: - vm =3D test_guest_stage(vm); + vm =3D test_guest_stage(vm, scope); break; case UCALL_DONE: guest_done =3D true; @@ -371,6 +436,8 @@ int main(void) { setbuf(stdout, NULL); =20 - test_run(); + test_run(KVM_REG_ARM_SCOPE_VCPU); + test_run(KVM_REG_ARM_SCOPE_VM); + return 0; } --=20 2.35.1.473.g83b2b277ed-goog From nobody Tue Jun 23 22:11:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B70C8C433F5 for ; Thu, 24 Feb 2022 17:27:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232100AbiBXR2U (ORCPT ); Thu, 24 Feb 2022 12:28:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231846AbiBXR1O (ORCPT ); Thu, 24 Feb 2022 12:27:14 -0500 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C5D711C01 for ; Thu, 24 Feb 2022 09:26:38 -0800 (PST) Received: by mail-pg1-x549.google.com with SMTP id 145-20020a630397000000b00373b72d65f5so1413485pgd.12 for ; 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Thu, 24 Feb 2022 09:26:37 -0800 (PST) Date: Thu, 24 Feb 2022 17:25:59 +0000 In-Reply-To: <20220224172559.4170192-1-rananta@google.com> Message-Id: <20220224172559.4170192-14-rananta@google.com> Mime-Version: 1.0 References: <20220224172559.4170192-1-rananta@google.com> X-Mailer: git-send-email 2.35.1.574.g5d30c73bfb-goog Subject: [PATCH v4 13/13] selftests: KVM: aarch64: Add the bitmap firmware registers to get-reg-list From: Raghavendra Rao Ananta To: Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Paolo Bonzini , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the psuedo-firmware registers KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, and KVM_REG_ARM_VENDOR_HYP_BMAP to the base_regs[] list. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Oliver Upton --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/tes= ting/selftests/kvm/aarch64/get-reg-list.c index f769fc6cd927..42e613a7bb6a 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -686,6 +686,9 @@ static __u64 base_regs[] =3D { KVM_REG_ARM_FW_REG(0), KVM_REG_ARM_FW_REG(1), KVM_REG_ARM_FW_REG(2), + KVM_REG_ARM_FW_BMAP_REG(0), /* KVM_REG_ARM_STD_BMAP */ + KVM_REG_ARM_FW_BMAP_REG(1), /* KVM_REG_ARM_STD_HYP_BMAP */ + KVM_REG_ARM_FW_BMAP_REG(2), /* KVM_REG_ARM_VENDOR_HYP_BMAP */ ARM64_SYS_REG(3, 3, 14, 3, 1), /* CNTV_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 3, 2), /* CNTV_CVAL_EL0 */ ARM64_SYS_REG(3, 3, 14, 0, 2), --=20 2.35.1.473.g83b2b277ed-goog