From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7947DC433F5 for ; Thu, 24 Feb 2022 15:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236733AbiBXP5O (ORCPT ); Thu, 24 Feb 2022 10:57:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236720AbiBXP4z (ORCPT ); Thu, 24 Feb 2022 10:56:55 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B251C254544 for ; Thu, 24 Feb 2022 07:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718184; x=1677254184; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o7VDf0nJv0XlRbUzs4IaCYJuN/W3ueBazitrj9bCGEQ=; b=Liwmh+CzWUlYNhtmog678dN2iuYjPW9ovD6aW1AD/SWF3wB7AWVUlwBq TYR8DmOfCs2oCNRgwXrEEvp1aC3Pyo2Gve9+hFz5IYzXaVs/Kq/B+8yO5 E+ysIXAgH1l1Exzd8auMCHUbhjDjXOqyXMOTFGlfNqYMXcYah8FifeX37 4RZwxKuGaKdcB73UcgqC5lxZytUItxnwkp09/8uxBZod9pZwOh28bRCH/ zSoYRCdv2MSrvBHPp1kH0X30mz/1nh0YUtOvt0/sjW2vp3ncOgkIaPOVC 4X8jGYQ0L6wDYIUfUzBNbbbpfOQzaLLNXeLzVr9oqW4+QU/cpb5h5tNTN w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="252186709" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="252186709" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="574253915" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 24 Feb 2022 07:56:17 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 3A30993; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , David Rientjes Subject: [PATCHv4 01/30] x86/mm: Fix warning on build with X86_MEM_ENCRYPT=y Date: Thu, 24 Feb 2022 18:56:01 +0300 Message-Id: <20220224155630.52734-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" So far, AMD_MEM_ENCRYPT is the only user of X86_MEM_ENCRYPT. TDX will be the second. It will make mem_encrypt.c build without AMD_MEM_ENCRYPT, which triggers a warning: arch/x86/mm/mem_encrypt.c:69:13: warning: no previous prototype for function 'mem_encrypt_init' [-Wmissing-prototypes] Fix it by moving mem_encrypt_init() declaration outside of #ifdef CONFIG_AMD_MEM_ENCRYPT. Signed-off-by: Kirill A. Shutemov Fixes: 20f07a044a76 ("x86/sev: Move common memory encryption code to mem_en= crypt.c") Acked-by: David Rientjes Acked-by: Dave Hansen --- arch/x86/include/asm/mem_encrypt.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_= encrypt.h index e2c6f433ed10..88ceaf3648b3 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -49,9 +49,6 @@ void __init early_set_mem_enc_dec_hypercall(unsigned long= vaddr, int npages, =20 void __init mem_encrypt_free_decrypted_mem(void); =20 -/* Architecture __weak replacement functions */ -void __init mem_encrypt_init(void); - void __init sev_es_init_vc_handling(void); =20 #define __bss_decrypted __section(".bss..decrypted") @@ -89,6 +86,9 @@ static inline void mem_encrypt_free_decrypted_mem(void) {= } =20 #endif /* CONFIG_AMD_MEM_ENCRYPT */ =20 +/* Architecture __weak replacement functions */ +void __init mem_encrypt_init(void); + /* * The __sme_pa() and __sme_pa_nodebug() macros are meant for use when * writing to or comparing values from the cr3 register. Having the --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD0FAC433EF for ; Thu, 24 Feb 2022 15:58:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235116AbiBXP6e (ORCPT ); Thu, 24 Feb 2022 10:58:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236768AbiBXP5V (ORCPT ); Thu, 24 Feb 2022 10:57:21 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95F9431369 for ; Thu, 24 Feb 2022 07:56:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718204; x=1677254204; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3ill6r3APRtdoR5+XQpSN1Lih2FBgTexytUcOMygEBQ=; b=ORS3Ei98NEp2N88Dag2ZyHmcqMjUzDJjQJGNmArnh3eVzjS3QQGVvYef iZuIADEK7ue2Y9mM/C61PuxvWS+LuU25sttf1WOGz5XSerxeMJFB9pxrx BjSEoUc7IYCKsncPufDt5u+7CNEnxS1fSI1Z7UeZC9PGHEjrE0GipN7S/ 0ykhBf16JRGwEtyjSyOrBVodn5I+Pf5oAYHuIsxTUzNr2t287Ttsu7cZU t2tvCUpNzFB34A3iprk+Nit1yuUEhNN0Y/vgd9fTEDeX5GBc8Sg/+CcKe WZXMm+W5O5SLiUT/TZId722h52zffrU/BPXeubz0o+9xJVqloFf+Q9Q3q w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="239666506" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="239666506" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="607458032" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 24 Feb 2022 07:56:17 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 455F3439; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 02/30] x86/tdx: Detect running as a TDX guest in early boot Date: Thu, 24 Feb 2022 18:56:02 +0300 Message-Id: <20220224155630.52734-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan In preparation of extending cc_platform_has() API to support TDX guest, use CPUID instruction to detect support for TDX guests in the early boot code (via tdx_early_init()). Since copy_bootdata() is the first user of cc_platform_has() API, detect the TDX guest status before it. Define a synthetic feature flag (X86_FEATURE_TDX_GUEST) and set this bit in a valid TDX guest platform. Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/Kconfig | 12 ++++++++++++ arch/x86/coco/Makefile | 2 ++ arch/x86/coco/tdx.c | 23 +++++++++++++++++++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- arch/x86/include/asm/tdx.h | 21 +++++++++++++++++++++ arch/x86/kernel/head64.c | 4 ++++ 7 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 arch/x86/coco/tdx.c create mode 100644 arch/x86/include/asm/tdx.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 57a4e0285a80..c346d66b51fc 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -880,6 +880,18 @@ config ACRN_GUEST IOT with small footprint and real-time features. More details can be found in https://projectacrn.org/. =20 +config INTEL_TDX_GUEST + bool "Intel TDX (Trust Domain Extensions) - Guest Support" + depends on X86_64 && CPU_SUP_INTEL + depends on X86_X2APIC + help + Support running as a guest under Intel TDX. Without this support, + the guest kernel can not boot or run under TDX. + TDX includes memory encryption and integrity capabilities + which protect the confidentiality and integrity of guest + memory contents and CPU state. TDX guests are protected from + some attacks from the VMM. + endif #HYPERVISOR_GUEST =20 source "arch/x86/Kconfig.cpu" diff --git a/arch/x86/coco/Makefile b/arch/x86/coco/Makefile index c1ead00017a7..32f4c6e6f199 100644 --- a/arch/x86/coco/Makefile +++ b/arch/x86/coco/Makefile @@ -4,3 +4,5 @@ KASAN_SANITIZE_core.o :=3D n CFLAGS_core.o +=3D -fno-stack-protector =20 obj-y +=3D core.o + +obj-$(CONFIG_INTEL_TDX_GUEST) +=3D tdx.o diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c new file mode 100644 index 000000000000..00898e3eb77f --- /dev/null +++ b/arch/x86/coco/tdx.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2021-2022 Intel Corporation */ + +#undef pr_fmt +#define pr_fmt(fmt) "tdx: " fmt + +#include +#include + +void __init tdx_early_init(void) +{ + u32 eax, sig[3]; + + cpuid_count(TDX_CPUID_LEAF_ID, 0, &eax, &sig[0], &sig[2], &sig[1]); + + BUILD_BUG_ON(sizeof(sig) !=3D sizeof(TDX_IDENT) - 1); + if (memcmp(TDX_IDENT, sig, sizeof(sig))) + return; + + setup_force_cpu_cap(X86_FEATURE_TDX_GUEST); + + pr_info("Guest detected\n"); +} diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 5cd22090e53d..cacc8dde854b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -238,6 +238,7 @@ #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL h= ypercall instruction */ #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */ #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempted fun= ction */ +#define X86_FEATURE_TDX_GUEST ( 8*32+22) /* Intel Trust Domain Extensions= Guest */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, = WRGSBASE instructions*/ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/as= m/disabled-features.h index 1231d63f836d..b37de8268c9a 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -68,6 +68,12 @@ # define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) #endif =20 +#ifdef CONFIG_INTEL_TDX_GUEST +# define DISABLE_TDX_GUEST 0 +#else +# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -79,7 +85,7 @@ #define DISABLED_MASK5 0 #define DISABLED_MASK6 0 #define DISABLED_MASK7 (DISABLE_PTI) -#define DISABLED_MASK8 0 +#define DISABLED_MASK8 (DISABLE_TDX_GUEST) #define DISABLED_MASK9 (DISABLE_SMAP|DISABLE_SGX) #define DISABLED_MASK10 0 #define DISABLED_MASK11 0 diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h new file mode 100644 index 000000000000..ba8042ce61c2 --- /dev/null +++ b/arch/x86/include/asm/tdx.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2021-2022 Intel Corporation */ +#ifndef _ASM_X86_TDX_H +#define _ASM_X86_TDX_H + +#include + +#define TDX_CPUID_LEAF_ID 0x21 +#define TDX_IDENT "IntelTDX " + +#ifdef CONFIG_INTEL_TDX_GUEST + +void __init tdx_early_init(void); + +#else + +static inline void tdx_early_init(void) { }; + +#endif /* CONFIG_INTEL_TDX_GUEST */ + +#endif /* _ASM_X86_TDX_H */ diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 4f5ecbbaae77..6dff50c3edd6 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -40,6 +40,7 @@ #include #include #include +#include =20 /* * Manage page tables very early on. @@ -514,6 +515,9 @@ asmlinkage __visible void __init x86_64_start_kernel(ch= ar * real_mode_data) =20 idt_setup_early_handler(); =20 + /* Needed before cc_platform_has() can be used for TDX */ + tdx_early_init(); + copy_bootdata(__va(real_mode_data)); =20 /* --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0B3CC433F5 for ; Thu, 24 Feb 2022 15:56:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236450AbiBXP5E (ORCPT ); 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X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="312982973" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="312982973" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="508914383" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 24 Feb 2022 07:56:17 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 4F5B650E; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 03/30] x86/tdx: Provide common base for SEAMCALL and TDCALL C wrappers Date: Thu, 24 Feb 2022 18:56:03 +0300 Message-Id: <20220224155630.52734-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Secure Arbitration Mode (SEAM) is an extension of VMX architecture. It defines a new VMX root operation (SEAM VMX root) and a new VMX non-root operation (SEAM VMX non-root) which are both isolated from the legacy VMX operation where the host kernel runs. A CPU-attested software module (called 'TDX module') runs in SEAM VMX root to manage and protect VMs running in SEAM VMX non-root. SEAM VMX root is also used to host another CPU-attested software module (called 'P-SEAMLDR') to load and update the TDX module. Host kernel transits to either P-SEAMLDR or TDX module via the new SEAMCALL instruction, which is essentially a VMExit from VMX root mode to SEAM VMX root mode. SEAMCALLs are leaf functions defined by P-SEAMLDR and TDX module around the new SEAMCALL instruction. A guest kernel can also communicate with TDX module via TDCALL instruction. TDCALLs and SEAMCALLs use an ABI different from the x86-64 system-v ABI. RAX is used to carry both the SEAMCALL leaf function number (input) and the completion status (output). Additional GPRs (RCX, RDX, R8-R11) may be further used as both input and output operands in individual leaf. TDCALL and SEAMCALL share the same ABI and require the largely same code to pass down arguments and retrieve results. Define an assembly macro that can be used to implement C wrapper for both TDCALL and SEAMCALL. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/tdx.h | 20 ++++++++ arch/x86/kernel/asm-offsets.c | 9 ++++ arch/x86/virt/tdxcall.S | 91 +++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 arch/x86/virt/tdxcall.S diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index ba8042ce61c2..2f8cb1e53e77 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -8,6 +8,25 @@ #define TDX_CPUID_LEAF_ID 0x21 #define TDX_IDENT "IntelTDX " =20 +#define TDX_SEAMCALL_VMFAILINVALID 0x8000FF00FFFF0000ULL + +#ifndef __ASSEMBLY__ + +/* + * Used to gather the output registers values of the TDCALL and SEAMCALL + * instructions when requesting services from the TDX module. + * + * This is a software only structure and not part of the TDX module/VMM AB= I. + */ +struct tdx_module_output { + u64 rcx; + u64 rdx; + u64 r8; + u64 r9; + u64 r10; + u64 r11; +}; + #ifdef CONFIG_INTEL_TDX_GUEST =20 void __init tdx_early_init(void); @@ -18,4 +37,5 @@ static inline void tdx_early_init(void) { }; =20 #endif /* CONFIG_INTEL_TDX_GUEST */ =20 +#endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_TDX_H */ diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 9fb0a2f8b62a..7dca52f5cfc6 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #ifdef CONFIG_XEN #include @@ -65,6 +66,14 @@ static void __used common(void) OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2); #endif =20 + BLANK(); + OFFSET(TDX_MODULE_rcx, tdx_module_output, rcx); + OFFSET(TDX_MODULE_rdx, tdx_module_output, rdx); + OFFSET(TDX_MODULE_r8, tdx_module_output, r8); + OFFSET(TDX_MODULE_r9, tdx_module_output, r9); + OFFSET(TDX_MODULE_r10, tdx_module_output, r10); + OFFSET(TDX_MODULE_r11, tdx_module_output, r11); + BLANK(); OFFSET(BP_scratch, boot_params, scratch); OFFSET(BP_secure_boot, boot_params, secure_boot); diff --git a/arch/x86/virt/tdxcall.S b/arch/x86/virt/tdxcall.S new file mode 100644 index 000000000000..90569faedacc --- /dev/null +++ b/arch/x86/virt/tdxcall.S @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include + +/* + * TDX guests use the TDCALL instruction to make requests to the + * TDX module and hypercalls to the VMM. + * + * TDX host user SEAMCALL instruction to make requests to TDX module. + * + * They are supported in Binutils >=3D 2.36. + */ +#define tdcall .byte 0x66,0x0f,0x01,0xcc +#define seamcall .byte 0x66,0x0f,0x01,0xcf + +.macro TDX_MODULE_CALL host:req + /* + * R12 will be used as temporary storage for struct tdx_module_output + * pointer. Since R12-R15 registers are not used by TDCALL/SEAMCALL + * services supported by this function, it can be reused. + */ + + /* Callee saved, so preserve it */ + push %r12 + + /* + * Push output pointer to stack. + * After the operation, it will be fetched into R12 register. + */ + push %r9 + + /* Mangle function call ABI into TDCALL/SEAMCALL ABI: */ + /* Move Leaf ID to RAX */ + mov %rdi, %rax + /* Move input 4 to R9 */ + mov %r8, %r9 + /* Move input 3 to R8 */ + mov %rcx, %r8 + /* Move input 1 to RCX */ + mov %rsi, %rcx + /* Leave input param 2 in RDX */ + + .if \host + seamcall + /* + * SEAMCALL instruction is essentially a VMExit from VMX root + * mode to SEAM VMX root mode. VMfailInvalid (CF=3D1) indicates + * that the targeted SEAM firmware is not loaded or disabled, + * or P-SEAMLDR is busy with another SEAMCALL. %rax is not + * changed in this case. + * + * Set %rax to TDX_SEAMCALL_VMFAILINVALID for VMfailInvalid. + * This value will never be used as actual SEAMCALL error code. + */ + jnc .Lno_vmfailinvalid + mov $TDX_SEAMCALL_VMFAILINVALID, %rax +.Lno_vmfailinvalid: + .else + tdcall + .endif + + /* + * Fetch output pointer from stack to R12 (It is used + * as temporary storage) + */ + pop %r12 + + /* Check for success: 0 - Successful, otherwise failed */ + test %rax, %rax + jnz .Lno_output_struct + + /* + * Since this function can be initiated without an output pointer, + * check if caller provided an output struct before storing + * output registers. + */ + test %r12, %r12 + jz .Lno_output_struct + + /* Copy result registers to output struct: */ + movq %rcx, TDX_MODULE_rcx(%r12) + movq %rdx, TDX_MODULE_rdx(%r12) + movq %r8, TDX_MODULE_r8(%r12) + movq %r9, TDX_MODULE_r9(%r12) + movq %r10, TDX_MODULE_r10(%r12) + movq %r11, TDX_MODULE_r11(%r12) + +.Lno_output_struct: + /* Restore the state of R12 register */ + pop %r12 +.endm --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58AFFC433F5 for ; Thu, 24 Feb 2022 15:56:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234692AbiBXP5U (ORCPT ); Thu, 24 Feb 2022 10:57:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236674AbiBXP5C (ORCPT ); Thu, 24 Feb 2022 10:57:02 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1897EE8 for ; Thu, 24 Feb 2022 07:56:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718191; x=1677254191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5cVg21mzcsncW4tobTrGrNulYpa7nGwvruAOnuSGOso=; b=VvjHQZMMM3UH09P+pg4vF0CdIXblRqDn5cWvqRIEjHO2Yul112ailg9B kC5KWPIuK1u5VsLo1jEIPZI4LSTZUwrGh2hwnQ0JalgvZxf4DQQG9t0Rg sOshjnScJ2O5HbU1kuvsvY7Mxz22eRgO6SpsRthy/nlYabtbH3JQBJcyE n4x2xXMXaXAd2Kj0vsrhNrWbYafAL//LK5sYFYhJoXIzHe687uLSFkeM6 V33oDLnsmUd764jM3eMC3BUPIw3Z2+Qs12gv4ICQdOa1d6OotWOb/YfLj sS2i9jtwQSU/uH/kmUkiQoUdJ5ygB9WAUw4icT6MHaDkudlPUQ1fZVrpa A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="251094317" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="251094317" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="639761253" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 24 Feb 2022 07:56:17 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 5E3E564B; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 04/30] x86/tdx: Add __tdx_module_call() and __tdx_hypercall() helper functions Date: Thu, 24 Feb 2022 18:56:04 +0300 Message-Id: <20220224155630.52734-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan Guests communicate with VMMs with hypercalls. Historically, these are implemented using instructions that are known to cause VMEXITs like VMCALL, VMLAUNCH, etc. However, with TDX, VMEXITs no longer expose the guest state to the host. This prevents the old hypercall mechanisms from working. So, to communicate with VMM, TDX specification defines a new instruction called TDCALL. In a TDX based VM, since the VMM is an untrusted entity, an intermediary layer -- TDX module -- facilitates secure communication between the host and the guest. TDX module is loaded like a firmware into a special CPU mode called SEAM. TDX guests communicate with the TDX module using the TDCALL instruction. A guest uses TDCALL to communicate with both the TDX module and VMM. The value of the RAX register when executing the TDCALL instruction is used to determine the TDCALL type. A variant of TDCALL used to communicate with the VMM is called TDVMCALL. Add generic interfaces to communicate with the TDX module and VMM (using the TDCALL instruction). __tdx_hypercall() - Used by the guest to request services from the VMM (via TDVMCALL). __tdx_module_call() - Used to communicate with the TDX module (via TDCALL). Also define an additional wrapper _tdx_hypercall(), which adds error handling support for the TDCALL failure. The __tdx_module_call() and __tdx_hypercall() helper functions are implemented in assembly in a .S file. The TDCALL ABI requires shuffling arguments in and out of registers, which proved to be awkward with inline assembly. Just like syscalls, not all TDVMCALL use cases need to use the same number of argument registers. The implementation here picks the current worst-case scenario for TDCALL (4 registers). For TDCALLs with fewer than 4 arguments, there will end up being a few superfluous (cheap) instructions. But, this approach maximizes code reuse. For registers used by the TDCALL instruction, please check TDX GHCI specification, the section titled "TDCALL instruction" and "TDG.VP.VMCALL Interface". Based on previous patch by Sean Christopherson. Reviewed-by: Tony Luck Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/Makefile | 2 +- arch/x86/coco/tdcall.S | 184 ++++++++++++++++++++++++++++++++++ arch/x86/coco/tdx.c | 18 ++++ arch/x86/include/asm/tdx.h | 27 +++++ arch/x86/kernel/asm-offsets.c | 10 ++ 5 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 arch/x86/coco/tdcall.S diff --git a/arch/x86/coco/Makefile b/arch/x86/coco/Makefile index 32f4c6e6f199..14af5412e3cd 100644 --- a/arch/x86/coco/Makefile +++ b/arch/x86/coco/Makefile @@ -5,4 +5,4 @@ CFLAGS_core.o +=3D -fno-stack-protector =20 obj-y +=3D core.o =20 -obj-$(CONFIG_INTEL_TDX_GUEST) +=3D tdx.o +obj-$(CONFIG_INTEL_TDX_GUEST) +=3D tdx.o tdcall.o diff --git a/arch/x86/coco/tdcall.S b/arch/x86/coco/tdcall.S new file mode 100644 index 000000000000..c4dd9468e7d9 --- /dev/null +++ b/arch/x86/coco/tdcall.S @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include + +#include +#include +#include + +#include "../virt/tdxcall.S" + +/* + * Bitmasks of exposed registers (with VMM). + */ +#define TDX_R10 BIT(10) +#define TDX_R11 BIT(11) +#define TDX_R12 BIT(12) +#define TDX_R13 BIT(13) +#define TDX_R14 BIT(14) +#define TDX_R15 BIT(15) + +/* + * These registers are clobbered to hold arguments for each + * TDVMCALL. They are safe to expose to the VMM. + * Each bit in this mask represents a register ID. Bit field + * details can be found in TDX GHCI specification, section + * titled "TDCALL [TDG.VP.VMCALL] leaf". + */ +#define TDVMCALL_EXPOSE_REGS_MASK ( TDX_R10 | TDX_R11 | \ + TDX_R12 | TDX_R13 | \ + TDX_R14 | TDX_R15 ) + +/* + * __tdx_module_call() - Used by TDX guests to request services from + * the TDX module (does not include VMM services). + * + * Transforms function call register arguments into the TDCALL + * register ABI. After TDCALL operation, TDX module output is saved + * in @out (if it is provided by the user) + * + *------------------------------------------------------------------------- + * TDCALL ABI: + *------------------------------------------------------------------------- + * Input Registers: + * + * RAX - TDCALL Leaf number. + * RCX,RDX,R8-R9 - TDCALL Leaf specific input registers. + * + * Output Registers: + * + * RAX - TDCALL instruction error code. + * RCX,RDX,R8-R11 - TDCALL Leaf specific output registers. + * + *------------------------------------------------------------------------- + * + * __tdx_module_call() function ABI: + * + * @fn (RDI) - TDCALL Leaf ID, moved to RAX + * @rcx (RSI) - Input parameter 1, moved to RCX + * @rdx (RDX) - Input parameter 2, moved to RDX + * @r8 (RCX) - Input parameter 3, moved to R8 + * @r9 (R8) - Input parameter 4, moved to R9 + * + * @out (R9) - struct tdx_module_output pointer + * stored temporarily in R12 (not + * shared with the TDX module). It + * can be NULL. + * + * Return status of TDCALL via RAX. + */ +SYM_FUNC_START(__tdx_module_call) + FRAME_BEGIN + TDX_MODULE_CALL host=3D0 + FRAME_END + ret +SYM_FUNC_END(__tdx_module_call) + +/* + * __tdx_hypercall() - Make hypercalls to a TDX VMM. + * + * Transforms values in function call argument struct tdx_hypercall_args = @args + * into the TDCALL register ABI. After TDCALL operation, VMM output is sav= ed + * back in @args. + * + *------------------------------------------------------------------------- + * TD VMCALL ABI: + *------------------------------------------------------------------------- + * + * Input Registers: + * + * RAX - TDCALL instruction leaf number (0 - TDG.VP.VMCALL) + * RCX - BITMAP which controls which part of TD Guest GPR + * is passed as-is to the VMM and back. + * R10 - Set 0 to indicate TDCALL follows standard TDX ABI + * specification. Non zero value indicates vendor + * specific ABI. + * R11 - VMCALL sub function number + * RBX, RBP, RDI, RSI - Used to pass VMCALL sub function specific argumen= ts. + * R8-R9, R12-R15 - Same as above. + * + * Output Registers: + * + * RAX - TDCALL instruction status (Not related to hyperca= ll + * output). + * R10 - Hypercall output error code. + * R11-R15 - Hypercall sub function specific output values. + * + *------------------------------------------------------------------------- + * + * __tdx_hypercall() function ABI: + * + * @args (RDI) - struct tdx_hypercall_args for input and output + * @flags (RSI) - TDX_HCALL_* flags + * + * On successful completion, return the hypercall error code. + */ +SYM_FUNC_START(__tdx_hypercall) + FRAME_BEGIN + + /* Save callee-saved GPRs as mandated by the x86_64 ABI */ + push %r15 + push %r14 + push %r13 + push %r12 + + /* Mangle function call ABI into TDCALL ABI: */ + /* Set TDCALL leaf ID (TDVMCALL (0)) in RAX */ + xor %eax, %eax + + /* Copy hypercall registers from arg struct: */ + movq TDX_HYPERCALL_r10(%rdi), %r10 + movq TDX_HYPERCALL_r11(%rdi), %r11 + movq TDX_HYPERCALL_r12(%rdi), %r12 + movq TDX_HYPERCALL_r13(%rdi), %r13 + movq TDX_HYPERCALL_r14(%rdi), %r14 + movq TDX_HYPERCALL_r15(%rdi), %r15 + + movl $TDVMCALL_EXPOSE_REGS_MASK, %ecx + + tdcall + + /* + * TDVMCALL leaf does not suppose to fail. If it fails something + * is horribly wrong with TDX module. Stop the world. + */ + testq %rax, %rax + jne .Lpanic + + /* TDVMCALL leaf return code is in R10 */ + movq %r10, %rax + + /* Copy hypercall result registers to arg struct if needed */ + testq $TDX_HCALL_HAS_OUTPUT, %rsi + jz .Lout + + movq %r10, TDX_HYPERCALL_r10(%rdi) + movq %r11, TDX_HYPERCALL_r11(%rdi) + movq %r12, TDX_HYPERCALL_r12(%rdi) + movq %r13, TDX_HYPERCALL_r13(%rdi) + movq %r14, TDX_HYPERCALL_r14(%rdi) + movq %r15, TDX_HYPERCALL_r15(%rdi) +.Lout: + /* + * Zero out registers exposed to the VMM to avoid speculative execution + * with VMM-controlled values. This needs to include all registers + * present in TDVMCALL_EXPOSE_REGS_MASK (except R12-R15). R12-R15 + * context will be restored. + */ + xor %r10d, %r10d + xor %r11d, %r11d + + /* Restore callee-saved GPRs as mandated by the x86_64 ABI */ + pop %r12 + pop %r13 + pop %r14 + pop %r15 + + FRAME_END + + retq +.Lpanic: + ud2 +SYM_FUNC_END(__tdx_hypercall) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 00898e3eb77f..17365fd40ba2 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -7,6 +7,24 @@ #include #include =20 +/* + * Wrapper for standard use of __tdx_hypercall with no output aside from + * return code. + */ +static inline u64 _tdx_hypercall(u64 fn, u64 r12, u64 r13, u64 r14, u64 r1= 5) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D fn, + .r12 =3D r12, + .r13 =3D r13, + .r14 =3D r14, + .r15 =3D r15, + }; + + return __tdx_hypercall(&args, 0); +} + void __init tdx_early_init(void) { u32 eax, sig[3]; diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 2f8cb1e53e77..557227e40da9 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -3,11 +3,16 @@ #ifndef _ASM_X86_TDX_H #define _ASM_X86_TDX_H =20 +#include #include =20 #define TDX_CPUID_LEAF_ID 0x21 #define TDX_IDENT "IntelTDX " =20 +#define TDX_HYPERCALL_STANDARD 0 + +#define TDX_HCALL_HAS_OUTPUT BIT(0) + #define TDX_SEAMCALL_VMFAILINVALID 0x8000FF00FFFF0000ULL =20 #ifndef __ASSEMBLY__ @@ -27,10 +32,32 @@ struct tdx_module_output { u64 r11; }; =20 +/* + * Used in __tdx_hypercall() to pass down and get back registers' values of + * the TDCALL instruction when requesting services from the VMM. + * + * This is a software only structure and not part of the TDX module/VMM AB= I. + */ +struct tdx_hypercall_args { + u64 r10; + u64 r11; + u64 r12; + u64 r13; + u64 r14; + u64 r15; +}; + #ifdef CONFIG_INTEL_TDX_GUEST =20 void __init tdx_early_init(void); =20 +/* Used to communicate with the TDX module */ +u64 __tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, + struct tdx_module_output *out); + +/* Used to request services from the VMM */ +u64 __tdx_hypercall(struct tdx_hypercall_args *args, unsigned long flags); + #else =20 static inline void tdx_early_init(void) { }; diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 7dca52f5cfc6..0b465e7d0a2f 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -74,6 +74,16 @@ static void __used common(void) OFFSET(TDX_MODULE_r10, tdx_module_output, r10); OFFSET(TDX_MODULE_r11, tdx_module_output, r11); =20 +#ifdef CONFIG_INTEL_TDX_GUEST + BLANK(); + OFFSET(TDX_HYPERCALL_r10, tdx_hypercall_args, r10); + OFFSET(TDX_HYPERCALL_r11, tdx_hypercall_args, r11); + OFFSET(TDX_HYPERCALL_r12, tdx_hypercall_args, r12); + OFFSET(TDX_HYPERCALL_r13, tdx_hypercall_args, r13); + OFFSET(TDX_HYPERCALL_r14, tdx_hypercall_args, r14); + OFFSET(TDX_HYPERCALL_r15, tdx_hypercall_args, r15); +#endif + BLANK(); OFFSET(BP_scratch, boot_params, scratch); OFFSET(BP_secure_boot, boot_params, secure_boot); --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1AC8C433F5 for ; Thu, 24 Feb 2022 15:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbiBXP6p (ORCPT ); Thu, 24 Feb 2022 10:58:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236858AbiBXP5t (ORCPT ); Thu, 24 Feb 2022 10:57:49 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E3A2DE2EE for ; Thu, 24 Feb 2022 07:57:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718222; x=1677254222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sqplZ36NTUAxVKTVx8J9Prykr0H/GFG/xm0iD1t8jgc=; b=L2+R/oxfKnpqWHhYafWYN6DhXfvYV4hfNGyQ6OkUWjv/eyPpChaKhXJ0 tRX/a75cN6OVOWc3j775LT2Uw1i4ntQ56yIBtCbyd2Y54nqWVhUjeUZe7 kX6S0HiYdlaCkRQc6GhCUhrk55biWLQ4Qyj6DK/YwPyDApORQf3ZKMDIq SqWOL18jrQ3pdL1MXWnDHEq+T/PeLlPMv3rRdF+x5TXJz//lYj6QT5NDR IfwUB7hqSDLCrQpUg+NWY22bju/KnXoyo/2c33ExS7/9CSUhCytAoUa+k byLy56G5fz928mlDq8dk8O9+2cpSOuYnRQIx6ltGKI/59Qi/QfsBbPICx w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487666" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487666" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="607458056" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 24 Feb 2022 07:56:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 68B3D763; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 05/30] x86/tdx: Extend the confidential computing API to support TDX guests Date: Thu, 24 Feb 2022 18:56:05 +0300 Message-Id: <20220224155630.52734-6-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Confidential Computing (CC) features (like string I/O unroll support, memory encryption/decryption support, etc) are conditionally enabled in the kernel using cc_platform_has() API. Since TDX guests also need to use these CC features, extend cc_platform_has() API and add TDX guest-specific CC attributes support. Like AMD SME/SEV, TDX uses a bit in the page table entry to indicate encryption status of the page, but the polarity of the mask is opposite to AMD: if the bit is set the page is accessible to VMM. Details about which bit in the page table entry to be used to indicate shared/private state can be determined by using the TDINFO TDCALL. Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 1 + arch/x86/coco/core.c | 4 ++++ arch/x86/coco/tdx.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c346d66b51fc..93e67842e369 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -884,6 +884,7 @@ config INTEL_TDX_GUEST bool "Intel TDX (Trust Domain Extensions) - Guest Support" depends on X86_64 && CPU_SUP_INTEL depends on X86_X2APIC + select ARCH_HAS_CC_PLATFORM help Support running as a guest under Intel TDX. Without this support, the guest kernel can not boot or run under TDX. diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index fc1365dd927e..9113baebbfd2 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -90,6 +90,8 @@ u64 cc_mkenc(u64 val) switch (vendor) { case CC_VENDOR_AMD: return val | cc_mask; + case CC_VENDOR_INTEL: + return val & ~cc_mask; default: return val; } @@ -100,6 +102,8 @@ u64 cc_mkdec(u64 val) switch (vendor) { case CC_VENDOR_AMD: return val & ~cc_mask; + case CC_VENDOR_INTEL: + return val | cc_mask; default: return val; } diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 17365fd40ba2..74c6e68dd1b3 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -5,8 +5,17 @@ #define pr_fmt(fmt) "tdx: " fmt =20 #include +#include #include =20 +/* TDX module Call Leaf IDs */ +#define TDX_GET_INFO 1 + +static struct { + unsigned int gpa_width; + unsigned long attributes; +} td_info __ro_after_init; + /* * Wrapper for standard use of __tdx_hypercall with no output aside from * return code. @@ -25,6 +34,30 @@ static inline u64 _tdx_hypercall(u64 fn, u64 r12, u64 r1= 3, u64 r14, u64 r15) return __tdx_hypercall(&args, 0); } =20 +static inline void tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r= 9, + struct tdx_module_output *out) +{ + if (__tdx_module_call(fn, rcx, rdx, r8, r9, out)) + panic("TDCALL %lld failed (Buggy TDX module!)\n", fn); +} + +static void get_info(void) +{ + struct tdx_module_output out; + + /* + * TDINFO TDX module call is used to get the TD execution environment + * information like GPA width, number of available vcpus, debug mode + * information, etc. More details about the ABI can be found in TDX + * Guest-Host-Communication Interface (GHCI), section 2.4.2 TDCALL + * [TDG.VP.INFO]. + */ + tdx_module_call(TDX_GET_INFO, 0, 0, 0, 0, &out); + + td_info.gpa_width =3D out.rcx & GENMASK(5, 0); + td_info.attributes =3D out.rdx; +} + void __init tdx_early_init(void) { u32 eax, sig[3]; @@ -37,5 +70,15 @@ void __init tdx_early_init(void) =20 setup_force_cpu_cap(X86_FEATURE_TDX_GUEST); =20 + get_info(); + + cc_set_vendor(CC_VENDOR_INTEL); + + /* + * The highest bit of a guest physical address is the "sharing" bit. + * Set it for shared pages and clear it for private pages. + */ + cc_set_mask(BIT_ULL(td_info.gpa_width - 1)); + pr_info("Guest detected\n"); } --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B48FC433F5 for ; Thu, 24 Feb 2022 15:58:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234677AbiBXP6w (ORCPT ); Thu, 24 Feb 2022 10:58:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236866AbiBXP5t (ORCPT ); Thu, 24 Feb 2022 10:57:49 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 715DCFABD6 for ; Thu, 24 Feb 2022 07:57:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718224; x=1677254224; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Roqm3vxXsDrqlJjxy74QcX0NceV5nOJOiJIuEZDgIS0=; b=CNVf3jf0OIXrvGyzejs9weXuO5ZYwvNdYFywIqloLO1K4AJpgjb3iOhU jB2ylgFp4ShienMUmpGmekaZlGiQmjs+FVjy0huNcG1k/8x47IZnltf2e qFnVgjjqrHbg2NeGdkgKqYAvqrOkaJdk7M8XRwYbQqxW7bwjyUDakV/le l9froTGTVsiBkpbzdsrqvt1zFmCIedcVVAxS+5K8kzkRlfctmaAgQous+ KTaYKr5TTcj+jDwhuZf1VlhyotqhySBKvAsyk0Mx6PynCzERzbTegQa1c 8E3NAx1W0zrXul6Vz7JLIrkgKSyTEp8gD2vaTIl+5Txinq/dZlOedsbuB g==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487662" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487662" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="707500677" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 24 Feb 2022 07:56:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 761CC772; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 06/30] x86/tdx: Exclude shared bit from __PHYSICAL_MASK Date: Thu, 24 Feb 2022 18:56:06 +0300 Message-Id: <20220224155630.52734-7-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In TDX guests, by default memory is protected from host access. If a guest needs to communicate with the VMM (like the I/O use case), it uses a single bit in the physical address to communicate the protected/shared attribute of the given page. In the x86 ARCH code, __PHYSICAL_MASK macro represents the width of the physical address in the given architecture. It is used in creating physical PAGE_MASK for address bits in the kernel. Since in TDX guest, a single bit is used as metadata, it needs to be excluded from valid physical address bits to avoid using incorrect addresses bits in the kernel. Enable DYNAMIC_PHYSICAL_MASK to support updating the __PHYSICAL_MASK. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner --- arch/x86/Kconfig | 1 + arch/x86/coco/tdx.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 93e67842e369..d2f45e58e846 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -885,6 +885,7 @@ config INTEL_TDX_GUEST depends on X86_64 && CPU_SUP_INTEL depends on X86_X2APIC select ARCH_HAS_CC_PLATFORM + select DYNAMIC_PHYSICAL_MASK help Support running as a guest under Intel TDX. Without this support, the guest kernel can not boot or run under TDX. diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 74c6e68dd1b3..14c085930b5f 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -74,6 +74,14 @@ void __init tdx_early_init(void) =20 cc_set_vendor(CC_VENDOR_INTEL); =20 + /* + * All bits above GPA width are reserved and kernel treats shared bit + * as flag, not as part of physical address. + * + * Adjust physical mask to only cover valid GPA bits. + */ + physical_mask &=3D GENMASK_ULL(td_info.gpa_width - 2, 0); + /* * The highest bit of a guest physical address is the "sharing" bit. * Set it for shared pages and clear it for private pages. --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F070C433F5 for ; Thu, 24 Feb 2022 15:57:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232210AbiBXP5g (ORCPT ); Thu, 24 Feb 2022 10:57:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236683AbiBXP5G (ORCPT ); Thu, 24 Feb 2022 10:57:06 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A852BC04 for ; Thu, 24 Feb 2022 07:56:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718196; x=1677254196; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/KKX+UUKQMQQ0UnrsFVZUxGjimE8kYKykrfKYuZi9iQ=; b=l02jKlKS7PS4fMHmlHZQVGPmEv1AM8xPFxZKs6HXxioHW20jW8Qg3aTJ fm8uD4u0Kmb/nNVHxCD25we0oq27n7r6/gadsdNl3vdmtx//xbnFgo+Bk /X9M5COd4wFRqRkL26fEiBjmqV6ekxK2wvHXYPcmdfbW2ZoGbpE4txrsG DFygnYRN4Lo0OtouXu3FzHND2+AkQ9NQff65xvtK38TZBwa6/qphGWxNC JQOMMhnTy6noRLadN787NB4mjrDfxKKad5I1+zK0okKB9WK2J37HcZWS2 XKUz+dfEmcNFKlUp/ihxa27A8Q86UDOLooCHPVGwFNuSlop0IgqBMh5qV w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="251094349" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="251094349" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628512995" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 7F6387F2; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Sean Christopherson Subject: [PATCHv4 07/30] x86/traps: Add #VE support for TDX guest Date: Thu, 24 Feb 2022 18:56:07 +0300 Message-Id: <20220224155630.52734-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Virtualization Exceptions (#VE) are delivered to TDX guests due to specific guest actions which may happen in either user space or the kernel: * Specific instructions (WBINVD, for example) * Specific MSR accesses * Specific CPUID leaf accesses * Access to unmapped pages (EPT violation) In the settings that Linux will run in, virtualization exceptions are never generated on accesses to normal, TD-private memory that has been accepted. Syscall entry code has a critical window where the kernel stack is not yet set up. Any exception in this window leads to hard to debug issues and can be exploited for privilege escalation. Exceptions in the NMI entry code also cause issues. Returning from the exception handler with IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. For these reasons, the kernel avoids #VEs during the syscall gap and the NMI entry code. Entry code paths do not access TD-shared memory, MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves that might generate #VE. VMM can remove memory from TD at any point, but access to unaccepted (or missing) private memory leads to VM termination, not to #VE. Similarly to page faults and breakpoints, #VEs are allowed in NMI handlers once the kernel is ready to deal with nested NMIs. During #VE delivery, all interrupts, including NMIs, are blocked until TDGETVEINFO is called. It prevents #VE nesting until the kernel reads the VE info. If a guest kernel action which would normally cause a #VE occurs in the interrupt-disabled region before TDGETVEINFO, a #DF (fault exception) is delivered to the guest which will result in an oops. Add basic infrastructure to handle any #VE which occurs in the kernel or userspace. Later patches will add handling for specific #VE scenarios. For now, convert unhandled #VE's (everything, until later in this series) so that they appear just like a #GP by calling the ve_raise_fault() directly. The ve_raise_fault() function is similar to #GP handler and is responsible for sending SIGSEGV to userspace and CPU die and notifying debuggers and other die chain users. Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx.c | 60 ++++++++++++++ arch/x86/include/asm/idtentry.h | 4 + arch/x86/include/asm/tdx.h | 21 +++++ arch/x86/kernel/idt.c | 3 + arch/x86/kernel/traps.c | 138 ++++++++++++++++++++++++++------ 5 files changed, 203 insertions(+), 23 deletions(-) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 14c085930b5f..86a2f35e7308 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -10,6 +10,7 @@ =20 /* TDX module Call Leaf IDs */ #define TDX_GET_INFO 1 +#define TDX_GET_VEINFO 3 =20 static struct { unsigned int gpa_width; @@ -58,6 +59,65 @@ static void get_info(void) td_info.attributes =3D out.rdx; } =20 +void tdx_get_ve_info(struct ve_info *ve) +{ + struct tdx_module_output out; + + /* + * Retrieve the #VE info from the TDX module, which also clears the "#VE + * valid" flag. This must be done before anything else as any #VE that + * occurs while the valid flag is set, i.e. before the previous #VE info + * was consumed, is morphed to a #DF by the TDX module. Note, the TDX + * module also treats virtual NMIs as inhibited if the #VE valid flag is + * set, e.g. so that NMI=3D>#VE will not result in a #DF. + */ + tdx_module_call(TDX_GET_VEINFO, 0, 0, 0, 0, &out); + + ve->exit_reason =3D out.rcx; + ve->exit_qual =3D out.rdx; + ve->gla =3D out.r8; + ve->gpa =3D out.r9; + ve->instr_len =3D lower_32_bits(out.r10); + ve->instr_info =3D upper_32_bits(out.r10); +} + +/* + * Handle the user initiated #VE. + * + * For example, executing the CPUID instruction from user space + * is a valid case and hence the resulting #VE has to be handled. + * + * For dis-allowed or invalid #VE just return failure. + */ +static bool virt_exception_user(struct pt_regs *regs, struct ve_info *ve) +{ + pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); + return false; +} + +/* Handle the kernel #VE */ +static bool virt_exception_kernel(struct pt_regs *regs, struct ve_info *ve) +{ + pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); + return false; +} + +bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve) +{ + bool ret; + + if (user_mode(regs)) + ret =3D virt_exception_user(regs, ve); + else + ret =3D virt_exception_kernel(regs, ve); + + /* After successful #VE handling, move the IP */ + if (ret) + regs->ip +=3D ve->instr_len; + + return ret; +} + void __init tdx_early_init(void) { u32 eax, sig[3]; diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentr= y.h index 1345088e9902..8ccc81d653b3 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -625,6 +625,10 @@ DECLARE_IDTENTRY_XENCB(X86_TRAP_OTHER, exc_xen_hypervi= sor_callback); DECLARE_IDTENTRY_RAW(X86_TRAP_OTHER, exc_xen_unknown_trap); #endif =20 +#ifdef CONFIG_INTEL_TDX_GUEST +DECLARE_IDTENTRY(X86_TRAP_VE, exc_virtualization_exception); +#endif + /* Device interrupts common/spurious */ DECLARE_IDTENTRY_IRQ(X86_TRAP_OTHER, common_interrupt); #ifdef CONFIG_X86_LOCAL_APIC diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 557227e40da9..34cf998ad534 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -5,6 +5,7 @@ =20 #include #include +#include =20 #define TDX_CPUID_LEAF_ID 0x21 #define TDX_IDENT "IntelTDX " @@ -47,6 +48,22 @@ struct tdx_hypercall_args { u64 r15; }; =20 +/* + * Used by the #VE exception handler to gather the #VE exception + * info from the TDX module. This is a software only structure + * and not part of the TDX module/VMM ABI. + */ +struct ve_info { + u64 exit_reason; + u64 exit_qual; + /* Guest Linear (virtual) Address */ + u64 gla; + /* Guest Physical (virtual) Address */ + u64 gpa; + u32 instr_len; + u32 instr_info; +}; + #ifdef CONFIG_INTEL_TDX_GUEST =20 void __init tdx_early_init(void); @@ -58,6 +75,10 @@ u64 __tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, = u64 r9, /* Used to request services from the VMM */ u64 __tdx_hypercall(struct tdx_hypercall_args *args, unsigned long flags); =20 +void tdx_get_ve_info(struct ve_info *ve); + +bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve); + #else =20 static inline void tdx_early_init(void) { }; diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index df0fa695bb09..1da074123c16 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -68,6 +68,9 @@ static const __initconst struct idt_data early_idts[] =3D= { */ INTG(X86_TRAP_PF, asm_exc_page_fault), #endif +#ifdef CONFIG_INTEL_TDX_GUEST + INTG(X86_TRAP_VE, asm_exc_virtualization_exception), +#endif }; =20 /* diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 7ef00dee35be..b2510af38158 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -62,6 +62,7 @@ #include #include #include +#include =20 #ifdef CONFIG_X86_64 #include @@ -611,13 +612,43 @@ static bool try_fixup_enqcmd_gp(void) #endif } =20 +static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, + unsigned long error_code, const char *str) +{ + int ret; + + if (fixup_exception(regs, trapnr, error_code, 0)) + return true; + + current->thread.error_code =3D error_code; + current->thread.trap_nr =3D trapnr; + + /* + * To be potentially processing a kprobe fault and to trust the result + * from kprobe_running(), we have to be non-preemptible. + */ + if (!preemptible() && kprobe_running() && + kprobe_fault_handler(regs, trapnr)) + return true; + + ret =3D notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV); + return ret =3D=3D NOTIFY_STOP; +} + +static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr, + unsigned long error_code, const char *str) +{ + current->thread.error_code =3D error_code; + current->thread.trap_nr =3D trapnr; + show_signal(current, SIGSEGV, "", str, regs, error_code); + force_sig(SIGSEGV); +} + DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) { char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] =3D GPFSTR; enum kernel_gp_hint hint =3D GP_NO_HINT; - struct task_struct *tsk; unsigned long gp_addr; - int ret; =20 if (user_mode(regs) && try_fixup_enqcmd_gp()) return; @@ -636,40 +667,21 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) return; } =20 - tsk =3D current; - if (user_mode(regs)) { if (fixup_iopl_exception(regs)) goto exit; =20 - tsk->thread.error_code =3D error_code; - tsk->thread.trap_nr =3D X86_TRAP_GP; - if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) goto exit; =20 - show_signal(tsk, SIGSEGV, "", desc, regs, error_code); - force_sig(SIGSEGV); + gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc); goto exit; } =20 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0)) goto exit; =20 - tsk->thread.error_code =3D error_code; - tsk->thread.trap_nr =3D X86_TRAP_GP; - - /* - * To be potentially processing a kprobe fault and to trust the result - * from kprobe_running(), we have to be non-preemptible. - */ - if (!preemptible() && - kprobe_running() && - kprobe_fault_handler(regs, X86_TRAP_GP)) - goto exit; - - ret =3D notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV); - if (ret =3D=3D NOTIFY_STOP) + if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc)) goto exit; =20 if (error_code) @@ -1267,6 +1279,86 @@ DEFINE_IDTENTRY(exc_device_not_available) } } =20 +#ifdef CONFIG_INTEL_TDX_GUEST + +#define VE_FAULT_STR "VE fault" + +static void ve_raise_fault(struct pt_regs *regs, long error_code) +{ + if (user_mode(regs)) { + gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); + return; + } + + if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, VE_FAULT_STR)) + return; + + die_addr(VE_FAULT_STR, regs, error_code, 0); +} + +/* + * Virtualization Exceptions (#VE) are delivered to TDX guests due to + * specific guest actions which may happen in either user space or the + * kernel: + * + * * Specific instructions (WBINVD, for example) + * * Specific MSR accesses + * * Specific CPUID leaf accesses + * * Access to unmapped pages (EPT violation) + * + * In the settings that Linux will run in, virtualization exceptions are + * never generated on accesses to normal, TD-private memory that has been + * accepted. + * + * Syscall entry code has a critical window where the kernel stack is not + * yet set up. Any exception in this window leads to hard to debug issues + * and can be exploited for privilege escalation. Exceptions in the NMI + * entry code also cause issues. Returning from the exception handler with + * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. + * + * For these reasons, the kernel avoids #VEs during the syscall gap and + * the NMI entry code. Entry code paths do not access TD-shared memory, + * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves + * that might generate #VE. VMM can remove memory from TD at any point, + * but access to unaccepted (or missing) private memory leads to VM + * termination, not to #VE. + * + * Similarly to page faults and breakpoints, #VEs are allowed in NMI + * handlers once the kernel is ready to deal with nested NMIs. + * + * During #VE delivery, all interrupts, including NMIs, are blocked until + * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads + * the VE info. + * + * If a guest kernel action which would normally cause a #VE occurs in + * the interrupt-disabled region before TDGETVEINFO, a #DF (fault + * exception) is delivered to the guest which will result in an oops. + */ +DEFINE_IDTENTRY(exc_virtualization_exception) +{ + struct ve_info ve; + + /* + * NMIs/Machine-checks/Interrupts will be in a disabled state + * till TDGETVEINFO TDCALL is executed. This ensures that VE + * info cannot be overwritten by a nested #VE. + */ + tdx_get_ve_info(&ve); + + cond_local_irq_enable(regs); + + /* + * If tdx_handle_virt_exception() could not process + * it successfully, treat it as #GP(0) and handle it. + */ + if (!tdx_handle_virt_exception(regs, &ve)) + ve_raise_fault(regs, 0); + + cond_local_irq_disable(regs); +} + +#endif + #ifdef CONFIG_X86_32 DEFINE_IDTENTRY_SW(iret_error) { --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB48CC433EF for ; Thu, 24 Feb 2022 15:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236780AbiBXP52 (ORCPT ); Thu, 24 Feb 2022 10:57:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236724AbiBXP5G (ORCPT ); Thu, 24 Feb 2022 10:57:06 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E398712764 for ; Thu, 24 Feb 2022 07:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718193; x=1677254193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EDcsdaa3CooVKW3VeAd7SwKOoBvqieWwTDQ5K+cpg/U=; b=CiWPajI+jDxF8/UHQ0mVtGMpT5wg6i09fX3YDCZ00wDMRT0R66bXTq4p qefXJ5qcODNrD5QEUsEPUDPlEU+LhK7GP4VRodgm2Mn2WrQnOC54RGFhI D04LmEh1g/Z86DbkhajJiAVG2zH2JLD6XEeuIi9OCtX0tXxWVK+2h+Hd8 +JGgyKqqObYF77zDio5VaO9LKy8gHhhN3eoe2IIz/cXzZfDm4xzakVatl 9vGaG15pWK5G9uYAVJ4Yp9UoZYnQijK8sQPdbbLIQWgGvVGmQF9MT8kw1 5GYY+yFeuBPUAhe2ogCvo1fCriklqdj9rANoS/xwvGDnIrp9YfyYdO93K A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="251094346" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="251094346" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628512993" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 8AB627FA; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 08/30] x86/tdx: Add HLT support for TDX guests Date: Thu, 24 Feb 2022 18:56:08 +0300 Message-Id: <20220224155630.52734-9-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The HLT instruction is a privileged instruction, executing it stops instruction execution and places the processor in a HALT state. It is used in kernel for cases like reboot, idle loop and exception fixup handlers. For the idle case, interrupts will be enabled (using STI) before the HLT instruction (this is also called safe_halt()). To support the HLT instruction in TDX guests, it needs to be emulated using TDVMCALL (hypercall to VMM). More details about it can be found in Intel Trust Domain Extensions (Intel TDX) Guest-Host-Communication Interface (GHCI) specification, section TDVMCALL[Instruction.HLT]. In TDX guests, executing HLT instruction will generate a #VE, which is used to emulate the HLT instruction. But #VE based emulation will not work for the safe_halt() flavor, because it requires STI instruction to be executed just before the TDCALL. Since idle loop is the only user of safe_halt() variant, handle it as a special case. To avoid *safe_halt() call in the idle function, define the tdx_guest_idle() and use it to override the "x86_idle" function pointer for a valid TDX guest. Alternative choices like PV ops have been considered for adding safe_halt() support. But it was rejected because HLT paravirt calls only exist under PARAVIRT_XXL, and enabling it in TDX guest just for safe_halt() use case is not worth the cost. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/coco/tdcall.S | 13 ++++++++ arch/x86/coco/tdx.c | 66 ++++++++++++++++++++++++++++++++++++-- arch/x86/include/asm/tdx.h | 4 +++ arch/x86/kernel/process.c | 4 +++ 4 files changed, 85 insertions(+), 2 deletions(-) diff --git a/arch/x86/coco/tdcall.S b/arch/x86/coco/tdcall.S index c4dd9468e7d9..3c35a056974d 100644 --- a/arch/x86/coco/tdcall.S +++ b/arch/x86/coco/tdcall.S @@ -138,6 +138,19 @@ SYM_FUNC_START(__tdx_hypercall) =20 movl $TDVMCALL_EXPOSE_REGS_MASK, %ecx =20 + /* + * For the idle loop STI needs to be called directly before the TDCALL + * that enters idle (EXIT_REASON_HLT case). STI instruction enables + * interrupts only one instruction later. If there is a window between + * STI and the instruction that emulates the HALT state, there is a + * chance for interrupts to happen in this window, which can delay the + * HLT operation indefinitely. Since this is the not the desired + * result, conditionally call STI before TDCALL. + */ + testq $TDX_HCALL_ISSUE_STI, %rsi + jz .Lskip_sti + sti +.Lskip_sti: tdcall =20 /* diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 86a2f35e7308..0a2e6be0cdae 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -7,6 +7,7 @@ #include #include #include +#include =20 /* TDX module Call Leaf IDs */ #define TDX_GET_INFO 1 @@ -59,6 +60,62 @@ static void get_info(void) td_info.attributes =3D out.rdx; } =20 +static u64 __cpuidle __halt(const bool irq_disabled, const bool do_sti) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_HLT, + .r12 =3D irq_disabled, + }; + + /* + * Emulate HLT operation via hypercall. More info about ABI + * can be found in TDX Guest-Host-Communication Interface + * (GHCI), section 3.8 TDG.VP.VMCALL. + * + * The VMM uses the "IRQ disabled" param to understand IRQ + * enabled status (RFLAGS.IF) of the TD guest and to determine + * whether or not it should schedule the halted vCPU if an + * IRQ becomes pending. E.g. if IRQs are disabled, the VMM + * can keep the vCPU in virtual HLT, even if an IRQ is + * pending, without hanging/breaking the guest. + */ + return __tdx_hypercall(&args, do_sti ? TDX_HCALL_ISSUE_STI : 0); +} + +static bool handle_halt(void) +{ + /* + * Since non safe halt is mainly used in CPU offlining + * and the guest will always stay in the halt state, don't + * call the STI instruction (set do_sti as false). + */ + const bool irq_disabled =3D irqs_disabled(); + const bool do_sti =3D false; + + if (__halt(irq_disabled, do_sti)) + return false; + + return true; +} + +void __cpuidle tdx_safe_halt(void) +{ + /* + * For do_sti=3Dtrue case, __tdx_hypercall() function enables + * interrupts using the STI instruction before the TDCALL. So + * set irq_disabled as false. + */ + const bool irq_disabled =3D false; + const bool do_sti =3D true; + + /* + * Use WARN_ONCE() to report the failure. + */ + if (__halt(irq_disabled, do_sti)) + WARN_ONCE(1, "HLT instruction emulation failed\n"); +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; @@ -98,8 +155,13 @@ static bool virt_exception_user(struct pt_regs *regs, s= truct ve_info *ve) /* Handle the kernel #VE */ static bool virt_exception_kernel(struct pt_regs *regs, struct ve_info *ve) { - pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); - return false; + switch (ve->exit_reason) { + case EXIT_REASON_HLT: + return handle_halt(); + default: + pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); + return false; + } } =20 bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 34cf998ad534..e6e23ade53a6 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -13,6 +13,7 @@ #define TDX_HYPERCALL_STANDARD 0 =20 #define TDX_HCALL_HAS_OUTPUT BIT(0) +#define TDX_HCALL_ISSUE_STI BIT(1) =20 #define TDX_SEAMCALL_VMFAILINVALID 0x8000FF00FFFF0000ULL =20 @@ -79,9 +80,12 @@ void tdx_get_ve_info(struct ve_info *ve); =20 bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve); =20 +void tdx_safe_halt(void); + #else =20 static inline void tdx_early_init(void) { }; +static inline void tdx_safe_halt(void) { }; =20 #endif /* CONFIG_INTEL_TDX_GUEST */ =20 diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index e131d71b3cae..2e90d57cf86e 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -46,6 +46,7 @@ #include #include #include +#include =20 #include "process.h" =20 @@ -873,6 +874,9 @@ void select_idle_routine(const struct cpuinfo_x86 *c) } else if (prefer_mwait_c1_over_halt(c)) { pr_info("using mwait in idle threads\n"); x86_idle =3D mwait_idle; + } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { + pr_info("using TDX aware idle routine\n"); + x86_idle =3D tdx_safe_halt; } else x86_idle =3D default_idle; } --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6913CC433EF for ; Thu, 24 Feb 2022 15:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236484AbiBXP7E (ORCPT ); Thu, 24 Feb 2022 10:59:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236878AbiBXP5u (ORCPT ); Thu, 24 Feb 2022 10:57:50 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBD61FEB34 for ; Thu, 24 Feb 2022 07:57:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718224; x=1677254224; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I9uK/HGgxs+4LApXPKoF4d7SoeHV8nK2K+EnhCg+LAs=; b=h7NcFLmNPN4HxrYthGKrCYFcA2RDTC+WUWLadppJptOsbTccjp1Tboxn iHD8TDZc4sOuxZDOOonQMZ64dr/LjSdOoXWh71xxDmcE0hHAYj6vQ0Len fYGHfVZ26f4K1+SOgkjw+zHRnEk15YSA8pfmgYqjumszjrDufaWD+xE6T Sqb8PQniy1Lyauq6d9hB8SiSOXTxMTHaeEViHxJLzvr20zIRexOaL8wmR QLUTqP80tsb0jWvtbD/0R0dlFKo86/UJt9slm4fDC+0F3NnIxoNbegP4i ppiyZ5jLOJuRox0Pv0FtwLhlit68jsJmjflBtHIERtkzQ8O74Obu30drc g==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="276893921" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="276893921" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="506362057" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2022 07:56:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 9808188D; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 09/30] x86/tdx: Add MSR support for TDX guests Date: Thu, 24 Feb 2022 18:56:09 +0300 Message-Id: <20220224155630.52734-10-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use hypercall to emulate MSR read/write for the TDX platform. There are two viable approaches for doing MSRs in a TD guest: 1. Execute the RDMSR/WRMSR instructions like most VMs and bare metal do. Some will succeed, others will cause a #VE. All of those that cause a #VE will be handled with a TDCALL. 2. Use paravirt infrastructure. The paravirt hook has to keep a list of which MSRs would cause a #VE and use a TDCALL. All other MSRs execute RDMSR/WRMSR instructions directly. The second option can be ruled out because the list of MSRs was challenging to maintain. That leaves option #1 as the only viable solution for the minimal TDX support. For performance-critical MSR writes (like TSC_DEADLINE), future patches will replace the WRMSR/#VE sequence with the direct TDCALL. RDMSR and WRMSR specification details can be found in Guest-Host-Communication Interface (GHCI) for Intel Trust Domain Extensions (Intel TDX) specification, sec titled "TDG.VP. VMCALL" and "TDG.VP.VMCALL". Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/coco/tdx.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 0a2e6be0cdae..89992593a209 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -116,6 +116,44 @@ void __cpuidle tdx_safe_halt(void) WARN_ONCE(1, "HLT instruction emulation failed\n"); } =20 +static bool read_msr(struct pt_regs *regs) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_MSR_READ, + .r12 =3D regs->cx, + }; + + /* + * Emulate the MSR read via hypercall. More info about ABI + * can be found in TDX Guest-Host-Communication Interface + * (GHCI), section titled "TDG.VP.VMCALL". + */ + if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT)) + return false; + + regs->ax =3D lower_32_bits(args.r11); + regs->dx =3D upper_32_bits(args.r11); + return true; +} + +static bool write_msr(struct pt_regs *regs) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_MSR_WRITE, + .r12 =3D regs->cx, + .r13 =3D (u64)regs->dx << 32 | regs->ax, + }; + + /* + * Emulate the MSR write via hypercall. More info about ABI + * can be found in TDX Guest-Host-Communication Interface + * (GHCI) section titled "TDG.VP.VMCALL". + */ + return !__tdx_hypercall(&args, 0); +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; @@ -158,6 +196,10 @@ static bool virt_exception_kernel(struct pt_regs *regs= , struct ve_info *ve) switch (ve->exit_reason) { case EXIT_REASON_HLT: return handle_halt(); + case EXIT_REASON_MSR_READ: + return read_msr(regs); + case EXIT_REASON_MSR_WRITE: + return write_msr(regs); default: pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); return false; --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC75DC433F5 for ; Thu, 24 Feb 2022 15:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236742AbiBXP5Z (ORCPT ); Thu, 24 Feb 2022 10:57:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236680AbiBXP5F (ORCPT ); Thu, 24 Feb 2022 10:57:05 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D288B33C for ; Thu, 24 Feb 2022 07:56:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718191; x=1677254191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iAKapfo2TJyc613nnXWyeTmHnGckX06XMzYOp7xRyi0=; b=ByzT/3p267MaiBGeuCWtUmOzuXZOAGutBuyMA7JfP6ibtqJdI17cw0Yt BTEykOrrYommW807hCAjHd9RCXazw2SFrBwCVKM3+CaycAJNjD9moju75 +XpP6w6K+9HNar4YxWef1ZYoy/zP3P8/2bLYFO4E4IvuxOKn/hE2G/j9P zH3WOWO0p2jVTmXcx/Z4g/M/S1xNMjmQwNHzB93A/Ki4aJ9tmyaGHvnNa SPUUxKtc6d7Dh8VbTJwDVJI9CRdZBju3vpmfEbhk/ckZnBZPZ5WfQtXuz vvtRBnck7UMD4CCr92CbHea2fx/SJAE+Zn4vbj2OJxlLdSvZgIG7j7URJ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="232889946" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="232889946" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="543744455" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 24 Feb 2022 07:56:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id A5F5D924; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 10/30] x86/tdx: Handle CPUID via #VE Date: Thu, 24 Feb 2022 18:56:10 +0300 Message-Id: <20220224155630.52734-11-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In TDX guests, most CPUID leaf/sub-leaf combinations are virtualized by the TDX module while some trigger #VE. Implement the #VE handling for EXIT_REASON_CPUID by handing it through the hypercall, which in turn lets the TDX module handle it by invoking the host VMM. More details on CPUID Virtualization can be found in the TDX module specification, the section titled "CPUID Virtualization". Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 89992593a209..fd78b81a951d 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -154,6 +154,36 @@ static bool write_msr(struct pt_regs *regs) return !__tdx_hypercall(&args, 0); } =20 +static bool handle_cpuid(struct pt_regs *regs) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_CPUID, + .r12 =3D regs->ax, + .r13 =3D regs->cx, + }; + + /* + * Emulate the CPUID instruction via a hypercall. More info about + * ABI can be found in TDX Guest-Host-Communication Interface + * (GHCI), section titled "VP.VMCALL". + */ + if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT)) + return false; + + /* + * As per TDX GHCI CPUID ABI, r12-r15 registers contain contents of + * EAX, EBX, ECX, EDX registers after the CPUID instruction execution. + * So copy the register contents back to pt_regs. + */ + regs->ax =3D args.r12; + regs->bx =3D args.r13; + regs->cx =3D args.r14; + regs->dx =3D args.r15; + + return true; +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; @@ -186,8 +216,13 @@ void tdx_get_ve_info(struct ve_info *ve) */ static bool virt_exception_user(struct pt_regs *regs, struct ve_info *ve) { - pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); - return false; + switch (ve->exit_reason) { + case EXIT_REASON_CPUID: + return handle_cpuid(regs); + default: + pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); + return false; + } } =20 /* Handle the kernel #VE */ @@ -200,6 +235,8 @@ static bool virt_exception_kernel(struct pt_regs *regs,= struct ve_info *ve) return read_msr(regs); case EXIT_REASON_MSR_WRITE: return write_msr(regs); + case EXIT_REASON_CPUID: + return handle_cpuid(regs); default: pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); return false; --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAC6C433F5 for ; Thu, 24 Feb 2022 15:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230283AbiBXP7J (ORCPT ); Thu, 24 Feb 2022 10:59:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236883AbiBXP5u (ORCPT ); Thu, 24 Feb 2022 10:57:50 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DFFA10613B for ; Thu, 24 Feb 2022 07:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718226; x=1677254226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ORgePUWcm66xMeSMj3u7P4jbgOrAJFy3rSEvBDqNVqk=; b=FSHPJdPVVU2uol2BaALFmu+Ow9fUeRbHdG7mwDEUtn4HE+MNXPeBxQr0 d3xReQM3p90iUfZxNcLcXFupWCIbveNQbyUnORLAJJAl2UzDkiXEP83mW uxBfz+TA4oLuH6u/In4PJ/iCRXZ9DStudXfJSdFqa3ituYY+aVT+s9Dp0 DuctAG2KTsYK/VRsJC6887Tp59OM2+raoAfmykRhDe2DJ31lHCCjx4mzi O8GTw20gzgb5ZmvXgOwTh5eYFtV/PWYIsig0ObigmdEqi1bhGI3FJ3vL2 kT51oSvP0LqpWPrA07tBqr86b/SmUqp9nfO2y80Fw9gR11OMb0PFc2shK Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487674" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487674" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="592128077" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 24 Feb 2022 07:56:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id B40859D9; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 11/30] x86/tdx: Handle in-kernel MMIO Date: Thu, 24 Feb 2022 18:56:11 +0300 Message-Id: <20220224155630.52734-12-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In non-TDX VMs, MMIO is implemented by providing the guest a mapping which will cause a VMEXIT on access and then the VMM emulating the instruction that caused the VMEXIT. That's not possible for TDX VM. To emulate an instruction an emulator needs two things: - R/W access to the register file to read/modify instruction arguments and see RIP of the faulted instruction. - Read access to memory where instruction is placed to see what to emulate. In this case it is guest kernel text. Both of them are not available to VMM in TDX environment: - Register file is never exposed to VMM. When a TD exits to the module, it saves registers into the state-save area allocated for that TD. The module then scrubs these registers before returning execution control to the VMM, to help prevent leakage of TD state. - Memory is encrypted a TD-private key. The CPU disallows software other than the TDX module and TDs from making memory accesses using the private key. In TDX the MMIO regions are instead configured to trigger a #VE exception in the guest. The guest #VE handler then emulates the MMIO instruction inside the guest and converts it into a controlled hypercall to the host. MMIO addresses can be used with any CPU instruction that accesses memory. Address only MMIO accesses done via io.h helpers, such as 'readl()' or 'writeq()'. readX()/writeX() helpers limit the range of instructions which can trigger MMIO. It makes MMIO instruction emulation feasible. Raw access to a MMIO region allows the compiler to generate whatever instruction it wants. Supporting all possible instructions is a task of a different scope. MMIO access with anything other than helpers from io.h may result in MMIO_DECODE_FAILED and an oops. AMD SEV has the same limitations to MMIO handling. =3D=3D=3D Potential alternative approaches =3D=3D=3D =3D=3D Paravirtualizing all MMIO =3D=3D An alternative to letting MMIO induce a #VE exception is to avoid the #VE in the first place. Similar to the port I/O case, it is theoretically possible to paravirtualize MMIO accesses. Like the exception-based approach offered here, a fully paravirtualized approach would be limited to MMIO users that leverage common infrastructure like the io.h macros. However, any paravirtual approach would be patching approximately 120k call sites. With a conservative overhead estimation of 5 bytes per call site (CALL instruction), it leads to bloating code by 600k. Many drivers will never be used in the TDX environment and the bloat cannot be justified. =3D=3D Patching TDX drivers =3D=3D Rather than touching the entire kernel, it might also be possible to just go after drivers that use MMIO in TDX guests. Right now, that's limited only to virtio and some x86-specific drivers. All virtio MMIO appears to be done through a single function, which makes virtio eminently easy to patch. This will be implemented in the future, removing the bulk of MMIO #VEs. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx.c | 110 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index fd78b81a951d..15519e498679 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -8,11 +8,17 @@ #include #include #include +#include +#include =20 /* TDX module Call Leaf IDs */ #define TDX_GET_INFO 1 #define TDX_GET_VEINFO 3 =20 +/* MMIO direction */ +#define EPT_READ 0 +#define EPT_WRITE 1 + static struct { unsigned int gpa_width; unsigned long attributes; @@ -184,6 +190,108 @@ static bool handle_cpuid(struct pt_regs *regs) return true; } =20 +static bool mmio_read(int size, unsigned long addr, unsigned long *val) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_EPT_VIOLATION, + .r12 =3D size, + .r13 =3D EPT_READ, + .r14 =3D addr, + .r15 =3D *val, + }; + + if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT)) + return false; + *val =3D args.r11; + return true; +} + +static bool mmio_write(int size, unsigned long addr, unsigned long val) +{ + return !_tdx_hypercall(EXIT_REASON_EPT_VIOLATION, size, EPT_WRITE, + addr, val); +} + +static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve) +{ + char buffer[MAX_INSN_SIZE]; + unsigned long *reg, val; + struct insn insn =3D {}; + enum mmio_type mmio; + int size, extend_size; + u8 extend_val =3D 0; + + if (copy_from_kernel_nofault(buffer, (void *)regs->ip, MAX_INSN_SIZE)) + return false; + + if (insn_decode(&insn, buffer, MAX_INSN_SIZE, INSN_MODE_64)) + return false; + + mmio =3D insn_decode_mmio(&insn, &size); + if (WARN_ON_ONCE(mmio =3D=3D MMIO_DECODE_FAILED)) + return false; + + if (mmio !=3D MMIO_WRITE_IMM && mmio !=3D MMIO_MOVS) { + reg =3D insn_get_modrm_reg_ptr(&insn, regs); + if (!reg) + return false; + } + + ve->instr_len =3D insn.length; + + switch (mmio) { + case MMIO_WRITE: + memcpy(&val, reg, size); + return mmio_write(size, ve->gpa, val); + case MMIO_WRITE_IMM: + val =3D insn.immediate.value; + return mmio_write(size, ve->gpa, val); + case MMIO_READ: + case MMIO_READ_ZERO_EXTEND: + case MMIO_READ_SIGN_EXTEND: + break; + case MMIO_MOVS: + case MMIO_DECODE_FAILED: + return false; + default: + BUG(); + } + + /* Handle reads */ + if (!mmio_read(size, ve->gpa, &val)) + return false; + + switch (mmio) { + case MMIO_READ: + /* Zero-extend for 32-bit operation */ + extend_size =3D size =3D=3D 4 ? sizeof(*reg) : 0; + break; + case MMIO_READ_ZERO_EXTEND: + /* Zero extend based on operand size */ + extend_size =3D insn.opnd_bytes; + break; + case MMIO_READ_SIGN_EXTEND: + /* Sign extend based on operand size */ + extend_size =3D insn.opnd_bytes; + if (size =3D=3D 1 && val & BIT(7)) + extend_val =3D 0xFF; + else if (size > 1 && val & BIT(15)) + extend_val =3D 0xFF; + break; + case MMIO_MOVS: + case MMIO_DECODE_FAILED: + return false; + default: + BUG(); + } + + if (extend_size) + memset(reg, extend_val, extend_size); + memcpy(reg, &val, size); + return true; +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; @@ -237,6 +345,8 @@ static bool virt_exception_kernel(struct pt_regs *regs,= struct ve_info *ve) return write_msr(regs); case EXIT_REASON_CPUID: return handle_cpuid(regs); + case EXIT_REASON_EPT_VIOLATION: + return handle_mmio(regs, ve); default: pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); return false; --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 207F6C433F5 for ; Thu, 24 Feb 2022 15:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236948AbiBXP7M (ORCPT ); Thu, 24 Feb 2022 10:59:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236881AbiBXP5u (ORCPT ); Thu, 24 Feb 2022 10:57:50 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8715D106631 for ; Thu, 24 Feb 2022 07:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718226; x=1677254226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P4wu+0Vfy/0DVkPV+vTcGhj54csZkZ48XAXLCZxu7N8=; b=hn010HXKgjFNORYgrRIQ9rmyOeQhKxYyZhrU0rXWQhiwv4CyA6CMeRgm sy/VkdUDXbuPWtLFHxvaWVH2X2mTfpPGZ41QLNKHdb3HzCYTCtPlj0rcG MYccIS92FfzvYKpyA/9JHsTMDsVTSMrz09uIQ1allVXW0LnQg7V+R38nt jdM9+ZGLZSLpiHvA7z+sfAJ8wOAeZUlt+nmOb/qR8ROneHeNh9cLX4KpZ f72T6i3+P39fLs06M7ZyKMjusT3cx5voyz/NFdyJTDGnqJO7hVhhYrobD UEviZoiVXYQH8l3VEPj+zXHVI9BUO1h0dQ/C8PRL09iZkymeEaAA0WXLn Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487689" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487689" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="592128103" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 24 Feb 2022 07:56:28 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id C1715A16; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 12/30] x86/tdx: Detect TDX at early kernel decompression time Date: Thu, 24 Feb 2022 18:56:12 +0300 Message-Id: <20220224155630.52734-13-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan The early decompression code does port I/O for its console output. But, handling the decompression-time port I/O demands a different approach from normal runtime because the IDT required to support #VE based port I/O emulation is not yet set up. Paravirtualizing I/O calls during the decompression step is acceptable because the decompression code size is small enough and hence patching it will not bloat the image size a lot. To support port I/O in decompression code, TDX must be detected before the decompression code might do port I/O. Detect whether the kernel runs in a TDX guest. Add an early_is_tdx_guest() interface to query the cached TDX guest status in the decompression code. The actual port I/O paravirtualization will come later in the series. Reviewed-by: Tony Luck Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/boot/compressed/Makefile | 1 + arch/x86/boot/compressed/misc.c | 8 ++++++++ arch/x86/boot/compressed/misc.h | 2 ++ arch/x86/boot/compressed/tdx.c | 27 +++++++++++++++++++++++++++ arch/x86/boot/compressed/tdx.h | 15 +++++++++++++++ arch/x86/boot/cpuflags.c | 3 +-- arch/x86/boot/cpuflags.h | 1 + arch/x86/include/asm/shared/tdx.h | 8 ++++++++ arch/x86/include/asm/tdx.h | 4 +--- 9 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 arch/x86/boot/compressed/tdx.c create mode 100644 arch/x86/boot/compressed/tdx.h create mode 100644 arch/x86/include/asm/shared/tdx.h diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/M= akefile index 6115274fe10f..732f6b21ecbd 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -101,6 +101,7 @@ ifdef CONFIG_X86_64 endif =20 vmlinux-objs-$(CONFIG_ACPI) +=3D $(obj)/acpi.o +vmlinux-objs-$(CONFIG_INTEL_TDX_GUEST) +=3D $(obj)/tdx.o =20 vmlinux-objs-$(CONFIG_EFI_MIXED) +=3D $(obj)/efi_thunk_$(BITS).o efi-obj-$(CONFIG_EFI_STUB) =3D $(objtree)/drivers/firmware/efi/libstub/lib= .a diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/mis= c.c index a4339cb2d247..2b1169869b96 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -370,6 +370,14 @@ asmlinkage __visible void *extract_kernel(void *rmode,= memptr heap, lines =3D boot_params->screen_info.orig_video_lines; cols =3D boot_params->screen_info.orig_video_cols; =20 + /* + * Detect TDX guest environment. + * + * It has to be done before console_init() in order to use + * paravirtualized port I/O operations if needed. + */ + early_tdx_detect(); + console_init(); =20 /* diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/mis= c.h index 16ed360b6692..0d8e275a9d96 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -28,6 +28,8 @@ #include #include =20 +#include "tdx.h" + #define BOOT_CTYPE_H #include =20 diff --git a/arch/x86/boot/compressed/tdx.c b/arch/x86/boot/compressed/tdx.c new file mode 100644 index 000000000000..dec68c184358 --- /dev/null +++ b/arch/x86/boot/compressed/tdx.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "../cpuflags.h" +#include "../string.h" + +#include + +static bool tdx_guest_detected; + +bool early_is_tdx_guest(void) +{ + return tdx_guest_detected; +} + +void early_tdx_detect(void) +{ + u32 eax, sig[3]; + + cpuid_count(TDX_CPUID_LEAF_ID, 0, &eax, &sig[0], &sig[2], &sig[1]); + + BUILD_BUG_ON(sizeof(sig) !=3D sizeof(TDX_IDENT) - 1); + if (memcmp(TDX_IDENT, sig, sizeof(sig))) + return; + + /* Cache TDX guest feature status */ + tdx_guest_detected =3D true; +} diff --git a/arch/x86/boot/compressed/tdx.h b/arch/x86/boot/compressed/tdx.h new file mode 100644 index 000000000000..a7bff6ae002e --- /dev/null +++ b/arch/x86/boot/compressed/tdx.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef BOOT_COMPRESSED_TDX_H +#define BOOT_COMPRESSED_TDX_H + +#include + +#ifdef CONFIG_INTEL_TDX_GUEST +void early_tdx_detect(void); +bool early_is_tdx_guest(void); +#else +static inline void early_tdx_detect(void) { }; +static inline bool early_is_tdx_guest(void) { return false; } +#endif + +#endif /* BOOT_COMPRESSED_TDX_H */ diff --git a/arch/x86/boot/cpuflags.c b/arch/x86/boot/cpuflags.c index a0b75f73dc63..a83d67ec627d 100644 --- a/arch/x86/boot/cpuflags.c +++ b/arch/x86/boot/cpuflags.c @@ -71,8 +71,7 @@ int has_eflag(unsigned long mask) # define EBX_REG "=3Db" #endif =20 -static inline void cpuid_count(u32 id, u32 count, - u32 *a, u32 *b, u32 *c, u32 *d) +void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d) { asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif \n\t" "cpuid \n\t" diff --git a/arch/x86/boot/cpuflags.h b/arch/x86/boot/cpuflags.h index 2e20814d3ce3..475b8fde90f7 100644 --- a/arch/x86/boot/cpuflags.h +++ b/arch/x86/boot/cpuflags.h @@ -17,5 +17,6 @@ extern u32 cpu_vendor[3]; =20 int has_eflag(unsigned long mask); void get_cpuflags(void); +void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d); =20 #endif diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h new file mode 100644 index 000000000000..8209ba9ffe1a --- /dev/null +++ b/arch/x86/include/asm/shared/tdx.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_SHARED_TDX_H +#define _ASM_X86_SHARED_TDX_H + +#define TDX_CPUID_LEAF_ID 0x21 +#define TDX_IDENT "IntelTDX " + +#endif /* _ASM_X86_SHARED_TDX_H */ diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index e6e23ade53a6..d4c28b9f2fbc 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -6,9 +6,7 @@ #include #include #include - -#define TDX_CPUID_LEAF_ID 0x21 -#define TDX_IDENT "IntelTDX " +#include =20 #define TDX_HYPERCALL_STANDARD 0 =20 --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 192FBC433F5 for ; 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X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="235773407" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="235773407" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="684315440" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 24 Feb 2022 07:56:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id CE8A4A3F; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 13/30] x86: Adjust types used in port I/O helpers Date: Thu, 24 Feb 2022 18:56:13 +0300 Message-Id: <20220224155630.52734-14-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Change port I/O helpers to use u8/u16/u32 instead of unsigned char/short/int for values. Use u16 instead of int for port number. It aligns the helpers with implementation in boot stub in preparation for consolidation. Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/include/asm/io.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index f6d91ecb8026..638c1a2a82e0 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -258,37 +258,37 @@ static inline void slow_down_io(void) #endif =20 #define BUILDIO(bwl, bw, type) \ -static inline void out##bwl(unsigned type value, int port) \ +static inline void out##bwl(type value, u16 port) \ { \ asm volatile("out" #bwl " %" #bw "0, %w1" \ : : "a"(value), "Nd"(port)); \ } \ \ -static inline unsigned type in##bwl(int port) \ +static inline type in##bwl(u16 port) \ { \ - unsigned type value; \ + type value; \ asm volatile("in" #bwl " %w1, %" #bw "0" \ : "=3Da"(value) : "Nd"(port)); \ return value; \ } \ \ -static inline void out##bwl##_p(unsigned type value, int port) \ +static inline void out##bwl##_p(type value, u16 port) \ { \ out##bwl(value, port); \ slow_down_io(); \ } \ \ -static inline unsigned type in##bwl##_p(int port) \ +static inline type in##bwl##_p(u16 port) \ { \ - unsigned type value =3D in##bwl(port); \ + type value =3D in##bwl(port); \ slow_down_io(); \ return value; \ } \ \ -static inline void outs##bwl(int port, const void *addr, unsigned long cou= nt) \ +static inline void outs##bwl(u16 port, const void *addr, unsigned long cou= nt) \ { \ if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ - unsigned type *value =3D (unsigned type *)addr; \ + type *value =3D (type *)addr; \ while (count) { \ out##bwl(*value, port); \ value++; \ @@ -301,10 +301,10 @@ static inline void outs##bwl(int port, const void *ad= dr, unsigned long count) \ } \ } \ \ -static inline void ins##bwl(int port, void *addr, unsigned long count) \ +static inline void ins##bwl(u16 port, void *addr, unsigned long count) \ { \ if (cc_platform_has(CC_ATTR_GUEST_UNROLL_STRING_IO)) { \ - unsigned type *value =3D (unsigned type *)addr; \ + type *value =3D (type *)addr; \ while (count) { \ *value =3D in##bwl(port); \ value++; \ @@ -317,9 +317,9 @@ static inline void ins##bwl(int port, void *addr, unsig= ned long count) \ } \ } =20 -BUILDIO(b, b, char) -BUILDIO(w, w, short) -BUILDIO(l, , int) +BUILDIO(b, b, u8) +BUILDIO(w, w, u16) +BUILDIO(l, , u32) =20 #define inb inb #define inw inw --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28E19C433F5 for ; Thu, 24 Feb 2022 15:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236758AbiBXP5p (ORCPT ); Thu, 24 Feb 2022 10:57:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236735AbiBXP5P (ORCPT ); Thu, 24 Feb 2022 10:57:15 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BC2DBC35 for ; Thu, 24 Feb 2022 07:56:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718197; x=1677254197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q+/r8F1XDpTWhhoX3MZMSCevaK2OCR1Drl1YYmHJWuo=; b=nFIaytt13pbDo2M2D0eTpAiNFiedIdjOEH6tvj9qwz0qi1lyr5xO2sXR 6cmRC/Ja6qcQyf68pHwv0Oct+m1fE88hY8Z93/W/0R/lfaa3XcYxOTcnC 5AOSum1bSmo9NTVowh45Xdqt0OpAg6WsoHINGpQIpTj7FMbxAnhYt7uLH aqOTDQAqERn7O7k1+1twv7W+kLm8yfyPvT+ZOBD1ZVRQQnRxTV5FERpdH UweKALfehEBGuXklVM5az47aaYAhfyb3/gapjuIUoAIc8nt6jnZo20Ell opn1rmFs9UkPV+BD8h+xhSp3z1DsQ48mYeH6AuQclTK20qQhIYfUQc+QQ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="251094352" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="251094352" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628512999" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id DB665A4C; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 14/30] x86: Consolidate port I/O helpers Date: Thu, 24 Feb 2022 18:56:14 +0300 Message-Id: <20220224155630.52734-15-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are two implementations of port I/O helpers: one in the kernel and one in the boot stub. Move the helpers required for both to and use the one implementation everywhere. Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner --- arch/x86/boot/boot.h | 35 +------------------------------- arch/x86/boot/compressed/misc.h | 2 +- arch/x86/include/asm/io.h | 22 ++------------------ arch/x86/include/asm/shared/io.h | 34 +++++++++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 55 deletions(-) create mode 100644 arch/x86/include/asm/shared/io.h diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index 34c9dbb6a47d..22a474c5b3e8 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -23,6 +23,7 @@ #include #include #include +#include #include "bitops.h" #include "ctype.h" #include "cpuflags.h" @@ -35,40 +36,6 @@ extern struct boot_params boot_params; =20 #define cpu_relax() asm volatile("rep; nop") =20 -/* Basic port I/O */ -static inline void outb(u8 v, u16 port) -{ - asm volatile("outb %0,%1" : : "a" (v), "dN" (port)); -} -static inline u8 inb(u16 port) -{ - u8 v; - asm volatile("inb %1,%0" : "=3Da" (v) : "dN" (port)); - return v; -} - -static inline void outw(u16 v, u16 port) -{ - asm volatile("outw %0,%1" : : "a" (v), "dN" (port)); -} -static inline u16 inw(u16 port) -{ - u16 v; - asm volatile("inw %1,%0" : "=3Da" (v) : "dN" (port)); - return v; -} - -static inline void outl(u32 v, u16 port) -{ - asm volatile("outl %0,%1" : : "a" (v), "dN" (port)); -} -static inline u32 inl(u16 port) -{ - u32 v; - asm volatile("inl %1,%0" : "=3Da" (v) : "dN" (port)); - return v; -} - static inline void io_delay(void) { const u16 DELAY_PORT =3D 0x80; diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/mis= c.h index 0d8e275a9d96..8a253e85f990 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -22,11 +22,11 @@ #include #include #include -#include #include #include #include #include +#include =20 #include "tdx.h" =20 diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 638c1a2a82e0..a1eb218a49f8 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -44,6 +44,7 @@ #include #include #include +#include =20 #define build_mmio_read(name, size, type, reg, barrier) \ static inline type name(const volatile void __iomem *addr) \ @@ -258,20 +259,6 @@ static inline void slow_down_io(void) #endif =20 #define BUILDIO(bwl, bw, type) \ -static inline void out##bwl(type value, u16 port) \ -{ \ - asm volatile("out" #bwl " %" #bw "0, %w1" \ - : : "a"(value), "Nd"(port)); \ -} \ - \ -static inline type in##bwl(u16 port) \ -{ \ - type value; \ - asm volatile("in" #bwl " %w1, %" #bw "0" \ - : "=3Da"(value) : "Nd"(port)); \ - return value; \ -} \ - \ static inline void out##bwl##_p(type value, u16 port) \ { \ out##bwl(value, port); \ @@ -320,10 +307,8 @@ static inline void ins##bwl(u16 port, void *addr, unsi= gned long count) \ BUILDIO(b, b, u8) BUILDIO(w, w, u16) BUILDIO(l, , u32) +#undef BUILDIO =20 -#define inb inb -#define inw inw -#define inl inl #define inb_p inb_p #define inw_p inw_p #define inl_p inl_p @@ -331,9 +316,6 @@ BUILDIO(l, , u32) #define insw insw #define insl insl =20 -#define outb outb -#define outw outw -#define outl outl #define outb_p outb_p #define outw_p outw_p #define outl_p outl_p diff --git a/arch/x86/include/asm/shared/io.h b/arch/x86/include/asm/shared= /io.h new file mode 100644 index 000000000000..6707cd555f0c --- /dev/null +++ b/arch/x86/include/asm/shared/io.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_SHARED_IO_H +#define _ASM_X86_SHARED_IO_H + +#include + +#define BUILDIO(bwl, bw, type) \ +static inline void out##bwl(type value, u16 port) \ +{ \ + asm volatile("out" #bwl " %" #bw "0, %w1" \ + : : "a"(value), "Nd"(port)); \ +} \ + \ +static inline type in##bwl(u16 port) \ +{ \ + type value; \ + asm volatile("in" #bwl " %w1, %" #bw "0" \ + : "=3Da"(value) : "Nd"(port)); \ + return value; \ +} + +BUILDIO(b, b, u8) +BUILDIO(w, w, u16) +BUILDIO(l, , u32) +#undef BUILDIO + +#define inb inb +#define inw inw +#define inl inl +#define outb outb +#define outw outw +#define outl outl + +#endif --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C346C433FE for ; Thu, 24 Feb 2022 15:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236836AbiBXP5s (ORCPT ); Thu, 24 Feb 2022 10:57:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236743AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1326712AAA for ; Thu, 24 Feb 2022 07:56:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718198; x=1677254198; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GSdloKmIAyBmUCQpEwXGIuKeooTJrRF6nd3afu9lyIs=; b=m3TrnCp8kelEBgqFr4ZYDTtbu672lsaIHaknIIf9POaL1MK+YOl2LgYa xpJYfLxVxbMuDUFAMJoospJ+WE5hvwiTz+apHeDOeo/zzrdJkLXYFScXQ PddfTpP0muBLsyYRW8outgnMlvmMJe3lSkaiA9Jn4G0wlVBrAhFfzT8oA wPGZ976vZHRAP1k29dUR6QUUyCzdQ1niJr2gB0wacuW7oekzabo1+Aglx AYTUCuoQmFTTa9rwMZylC3GDl6j0a7NhVQwO3W1ydE4zUW6H5dn4wBhhq Z/YcPzMc8DObGjzmynjK1TT71MqlTraW7bww8WpG7bgrDbklXivBstwUk A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="249849319" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="249849319" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628513009" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:31 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id E91A7A86; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 15/30] x86/boot: Allow to hook up alternative port I/O helpers Date: Thu, 24 Feb 2022 18:56:15 +0300 Message-Id: <20220224155630.52734-16-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Port I/O instructions trigger #VE in the TDX environment. In response to the exception, kernel emulates these instructions using hypercalls. But during early boot, on the decompression stage, it is cumbersome to deal with #VE. It is cleaner to go to hypercalls directly, bypassing #VE handling. Add a way to hook up alternative port I/O helpers in the boot stub. Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/boot/a20.c | 14 +++++++------- arch/x86/boot/boot.h | 2 +- arch/x86/boot/compressed/misc.c | 18 ++++++++++++------ arch/x86/boot/compressed/misc.h | 2 +- arch/x86/boot/early_serial_console.c | 28 ++++++++++++++-------------- arch/x86/boot/io.h | 28 ++++++++++++++++++++++++++++ arch/x86/boot/main.c | 4 ++++ arch/x86/boot/pm.c | 10 +++++----- arch/x86/boot/tty.c | 4 ++-- arch/x86/boot/video-vga.c | 6 +++--- arch/x86/boot/video.h | 8 +++++--- arch/x86/realmode/rm/wakemain.c | 14 +++++++++----- 12 files changed, 91 insertions(+), 47 deletions(-) create mode 100644 arch/x86/boot/io.h diff --git a/arch/x86/boot/a20.c b/arch/x86/boot/a20.c index a2b6b428922a..7f6dd5cc4670 100644 --- a/arch/x86/boot/a20.c +++ b/arch/x86/boot/a20.c @@ -25,7 +25,7 @@ static int empty_8042(void) while (loops--) { io_delay(); =20 - status =3D inb(0x64); + status =3D pio_ops.inb(0x64); if (status =3D=3D 0xff) { /* FF is a plausible, but very unlikely status */ if (!--ffs) @@ -34,7 +34,7 @@ static int empty_8042(void) if (status & 1) { /* Read and discard input data */ io_delay(); - (void)inb(0x60); + (void)pio_ops.inb(0x60); } else if (!(status & 2)) { /* Buffers empty, finished! */ return 0; @@ -99,13 +99,13 @@ static void enable_a20_kbc(void) { empty_8042(); =20 - outb(0xd1, 0x64); /* Command write */ + pio_ops.outb(0xd1, 0x64); /* Command write */ empty_8042(); =20 - outb(0xdf, 0x60); /* A20 on */ + pio_ops.outb(0xdf, 0x60); /* A20 on */ empty_8042(); =20 - outb(0xff, 0x64); /* Null command, but UHCI wants it */ + pio_ops.outb(0xff, 0x64); /* Null command, but UHCI wants it */ empty_8042(); } =20 @@ -113,10 +113,10 @@ static void enable_a20_fast(void) { u8 port_a; =20 - port_a =3D inb(0x92); /* Configuration port A */ + port_a =3D pio_ops.inb(0x92); /* Configuration port A */ port_a |=3D 0x02; /* Enable A20 */ port_a &=3D ~0x01; /* Do not reset machine */ - outb(port_a, 0x92); + pio_ops.outb(port_a, 0x92); } =20 /* diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index 22a474c5b3e8..bd8f640ca15f 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -23,10 +23,10 @@ #include #include #include -#include #include "bitops.h" #include "ctype.h" #include "cpuflags.h" +#include "io.h" =20 /* Useful macros */ #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/mis= c.c index 2b1169869b96..c0711b18086a 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -47,6 +47,8 @@ void *memmove(void *dest, const void *src, size_t n); */ struct boot_params *boot_params; =20 +struct port_io_ops pio_ops; + memptr free_mem_ptr; memptr free_mem_end_ptr; =20 @@ -103,10 +105,12 @@ static void serial_putchar(int ch) { unsigned timeout =3D 0xffff; =20 - while ((inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && --timeout) + while ((pio_ops.inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && + --timeout) { cpu_relax(); + } =20 - outb(ch, early_serial_base + TXR); + pio_ops.outb(ch, early_serial_base + TXR); } =20 void __putstr(const char *s) @@ -152,10 +156,10 @@ void __putstr(const char *s) boot_params->screen_info.orig_y =3D y; =20 pos =3D (x + cols * y) * 2; /* Update cursor position */ - outb(14, vidport); - outb(0xff & (pos >> 9), vidport+1); - outb(15, vidport); - outb(0xff & (pos >> 1), vidport+1); + pio_ops.outb(14, vidport); + pio_ops.outb(0xff & (pos >> 9), vidport+1); + pio_ops.outb(15, vidport); + pio_ops.outb(0xff & (pos >> 1), vidport+1); } =20 void __puthex(unsigned long value) @@ -370,6 +374,8 @@ asmlinkage __visible void *extract_kernel(void *rmode, = memptr heap, lines =3D boot_params->screen_info.orig_video_lines; cols =3D boot_params->screen_info.orig_video_cols; =20 + init_io_ops(); + /* * Detect TDX guest environment. * diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/mis= c.h index 8a253e85f990..ea71cf3d64e1 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -26,7 +26,6 @@ #include #include #include -#include =20 #include "tdx.h" =20 @@ -35,6 +34,7 @@ =20 #define BOOT_BOOT_H #include "../ctype.h" +#include "../io.h" =20 #ifdef CONFIG_X86_64 #define memptr long diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_ser= ial_console.c index 023bf1c3de8b..03e43d770571 100644 --- a/arch/x86/boot/early_serial_console.c +++ b/arch/x86/boot/early_serial_console.c @@ -28,17 +28,17 @@ static void early_serial_init(int port, int baud) unsigned char c; unsigned divisor; =20 - outb(0x3, port + LCR); /* 8n1 */ - outb(0, port + IER); /* no interrupt */ - outb(0, port + FCR); /* no fifo */ - outb(0x3, port + MCR); /* DTR + RTS */ + pio_ops.outb(0x3, port + LCR); /* 8n1 */ + pio_ops.outb(0, port + IER); /* no interrupt */ + pio_ops.outb(0, port + FCR); /* no fifo */ + pio_ops.outb(0x3, port + MCR); /* DTR + RTS */ =20 divisor =3D 115200 / baud; - c =3D inb(port + LCR); - outb(c | DLAB, port + LCR); - outb(divisor & 0xff, port + DLL); - outb((divisor >> 8) & 0xff, port + DLH); - outb(c & ~DLAB, port + LCR); + c =3D pio_ops.inb(port + LCR); + pio_ops.outb(c | DLAB, port + LCR); + pio_ops.outb(divisor & 0xff, port + DLL); + pio_ops.outb((divisor >> 8) & 0xff, port + DLH); + pio_ops.outb(c & ~DLAB, port + LCR); =20 early_serial_base =3D port; } @@ -104,11 +104,11 @@ static unsigned int probe_baud(int port) unsigned char lcr, dll, dlh; unsigned int quot; =20 - lcr =3D inb(port + LCR); - outb(lcr | DLAB, port + LCR); - dll =3D inb(port + DLL); - dlh =3D inb(port + DLH); - outb(lcr, port + LCR); + lcr =3D pio_ops.inb(port + LCR); + pio_ops.outb(lcr | DLAB, port + LCR); + dll =3D pio_ops.inb(port + DLL); + dlh =3D pio_ops.inb(port + DLH); + pio_ops.outb(lcr, port + LCR); quot =3D (dlh << 8) | dll; =20 return BASE_BAUD / quot; diff --git a/arch/x86/boot/io.h b/arch/x86/boot/io.h new file mode 100644 index 000000000000..8a53947ef70e --- /dev/null +++ b/arch/x86/boot/io.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef BOOT_IO_H +#define BOOT_IO_H + +#include + +struct port_io_ops { + u8 (*inb)(u16 port); + u16 (*inw)(u16 port); + u32 (*inl)(u16 port); + void (*outb)(u8 v, u16 port); + void (*outw)(u16 v, u16 port); + void (*outl)(u32 v, u16 port); +}; + +extern struct port_io_ops pio_ops; + +static inline void init_io_ops(void) +{ + pio_ops.inb =3D inb; + pio_ops.inw =3D inw; + pio_ops.inl =3D inl; + pio_ops.outb =3D outb; + pio_ops.outw =3D outw; + pio_ops.outl =3D outl; +} + +#endif diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c index e3add857c2c9..447a797891be 100644 --- a/arch/x86/boot/main.c +++ b/arch/x86/boot/main.c @@ -17,6 +17,8 @@ =20 struct boot_params boot_params __attribute__((aligned(16))); =20 +struct port_io_ops pio_ops; + char *HEAP =3D _end; char *heap_end =3D _end; /* Default end of heap =3D no heap */ =20 @@ -133,6 +135,8 @@ static void init_heap(void) =20 void main(void) { + init_io_ops(); + /* First, copy the boot header into the "zeropage" */ copy_boot_params(); =20 diff --git a/arch/x86/boot/pm.c b/arch/x86/boot/pm.c index 40031a614712..4180b6a264c9 100644 --- a/arch/x86/boot/pm.c +++ b/arch/x86/boot/pm.c @@ -25,7 +25,7 @@ static void realmode_switch_hook(void) : "eax", "ebx", "ecx", "edx"); } else { asm volatile("cli"); - outb(0x80, 0x70); /* Disable NMI */ + pio_ops.outb(0x80, 0x70); /* Disable NMI */ io_delay(); } } @@ -35,9 +35,9 @@ static void realmode_switch_hook(void) */ static void mask_all_interrupts(void) { - outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */ + pio_ops.outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */ io_delay(); - outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ + pio_ops.outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ io_delay(); } =20 @@ -46,9 +46,9 @@ static void mask_all_interrupts(void) */ static void reset_coprocessor(void) { - outb(0, 0xf0); + pio_ops.outb(0, 0xf0); io_delay(); - outb(0, 0xf1); + pio_ops.outb(0, 0xf1); io_delay(); } =20 diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c index f7eb976b0a4b..ee8700682801 100644 --- a/arch/x86/boot/tty.c +++ b/arch/x86/boot/tty.c @@ -29,10 +29,10 @@ static void __section(".inittext") serial_putchar(int c= h) { unsigned timeout =3D 0xffff; =20 - while ((inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && --timeout) + while ((pio_ops.inb(early_serial_base + LSR) & XMTRDY) =3D=3D 0 && --time= out) cpu_relax(); =20 - outb(ch, early_serial_base + TXR); + pio_ops.outb(ch, early_serial_base + TXR); } =20 static void __section(".inittext") bios_putchar(int ch) diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c index 4816cb9cf996..17baac542ee7 100644 --- a/arch/x86/boot/video-vga.c +++ b/arch/x86/boot/video-vga.c @@ -131,7 +131,7 @@ static void vga_set_80x43(void) /* I/O address of the VGA CRTC */ u16 vga_crtc(void) { - return (inb(0x3cc) & 1) ? 0x3d4 : 0x3b4; + return (pio_ops.inb(0x3cc) & 1) ? 0x3d4 : 0x3b4; } =20 static void vga_set_480_scanlines(void) @@ -148,10 +148,10 @@ static void vga_set_480_scanlines(void) out_idx(0xdf, crtc, 0x12); /* Vertical display end */ out_idx(0xe7, crtc, 0x15); /* Vertical blank start */ out_idx(0x04, crtc, 0x16); /* Vertical blank end */ - csel =3D inb(0x3cc); + csel =3D pio_ops.inb(0x3cc); csel &=3D 0x0d; csel |=3D 0xe2; - outb(csel, 0x3c2); + pio_ops.outb(csel, 0x3c2); } =20 static void vga_set_vertical_end(int lines) diff --git a/arch/x86/boot/video.h b/arch/x86/boot/video.h index 04bde0bb2003..87a5f726e731 100644 --- a/arch/x86/boot/video.h +++ b/arch/x86/boot/video.h @@ -15,6 +15,8 @@ =20 #include =20 +#include "boot.h" + /* * This code uses an extended set of video mode numbers. These include: * Aliases for standard modes @@ -96,13 +98,13 @@ extern int graphic_mode; /* Graphics mode with linear f= rame buffer */ /* Accessing VGA indexed registers */ static inline u8 in_idx(u16 port, u8 index) { - outb(index, port); - return inb(port+1); + pio_ops.outb(index, port); + return pio_ops.inb(port+1); } =20 static inline void out_idx(u8 v, u16 port, u8 index) { - outw(index+(v << 8), port); + pio_ops.outw(index+(v << 8), port); } =20 /* Writes a value to an indexed port and then reads the port again */ diff --git a/arch/x86/realmode/rm/wakemain.c b/arch/x86/realmode/rm/wakemai= n.c index 1d6437e6d2ba..b49404d0d63c 100644 --- a/arch/x86/realmode/rm/wakemain.c +++ b/arch/x86/realmode/rm/wakemain.c @@ -17,18 +17,18 @@ static void beep(unsigned int hz) } else { u16 div =3D 1193181/hz; =20 - outb(0xb6, 0x43); /* Ctr 2, squarewave, load, binary */ + pio_ops.outb(0xb6, 0x43); /* Ctr 2, squarewave, load, binary */ io_delay(); - outb(div, 0x42); /* LSB of counter */ + pio_ops.outb(div, 0x42); /* LSB of counter */ io_delay(); - outb(div >> 8, 0x42); /* MSB of counter */ + pio_ops.outb(div >> 8, 0x42); /* MSB of counter */ io_delay(); =20 enable =3D 0x03; /* Turn on speaker */ } - inb(0x61); /* Dummy read of System Control Port B */ + pio_ops.inb(0x61); /* Dummy read of System Control Port B */ io_delay(); - outb(enable, 0x61); /* Enable timer 2 output to speaker */ + pio_ops.outb(enable, 0x61); /* Enable timer 2 output to speaker */ io_delay(); } =20 @@ -62,8 +62,12 @@ static void send_morse(const char *pattern) } } =20 +struct port_io_ops pio_ops; + void main(void) { + init_io_ops(); + /* Kill machine if structures are wrong */ if (wakeup_header.real_magic !=3D 0x12345678) while (1) --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51911C4332F for ; Thu, 24 Feb 2022 15:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236789AbiBXP64 (ORCPT ); Thu, 24 Feb 2022 10:58:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236882AbiBXP5u (ORCPT ); Thu, 24 Feb 2022 10:57:50 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0A00106B08 for ; Thu, 24 Feb 2022 07:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718226; x=1677254226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5JtqWAS+h8SauINe/7rnE+HKw6JahRrP4ll/Fgbp2mk=; b=D8BFrOSYmk5t7VSkf8LsMRDHApG/gnH59heixJSoqqHDkKD0ELKJzJWV 6ga+3znLEPxcX0aJ1nWENl5T8rc0PnN96QL4PuNpHdWI/4B1QM25A/A8X 0lKvdVSTB6yQsYucK0xI5CL5vp4U8M+sSL63GwHIYBAagvBSL/kCSWPI5 K4wiqoIBT7NROrLMXSU+/bdwBW6L1V49Y4Mm9ML5V7covQFr//zSTf1iK UBzsWDfIB8o5wJ3v794svu0Do+CvpS4rXqmB+4H5CHnrqGlPYKO/0XUuw pemuy99d6QgTaFw4smxCDn4YLyRep5uWr77FTDhuZszTgbXdvBNWKyOoZ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487707" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487707" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="607458092" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 24 Feb 2022 07:56:31 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 0172BA8C; Thu, 24 Feb 2022 17:56:34 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 16/30] x86/boot/compressed: Support TDX guest port I/O at decompression time Date: Thu, 24 Feb 2022 18:56:16 +0300 Message-Id: <20220224155630.52734-17-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Port I/O instructions trigger #VE in the TDX environment. In response to the exception, kernel emulates these instructions using hypercalls. But during early boot, on the decompression stage, it is cumbersome to deal with #VE. It is cleaner to go to hypercalls directly, bypassing #VE handling. Hook up TDX-specific port I/O helpers if booting in TDX environment. Signed-off-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/boot/compressed/Makefile | 2 +- arch/x86/boot/compressed/tdcall.S | 3 ++ arch/x86/boot/compressed/tdx.c | 71 +++++++++++++++++++++++++++++++ arch/x86/include/asm/shared/tdx.h | 29 +++++++++++++ arch/x86/include/asm/tdx.h | 24 ----------- 5 files changed, 104 insertions(+), 25 deletions(-) create mode 100644 arch/x86/boot/compressed/tdcall.S diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/M= akefile index 732f6b21ecbd..8fd0e6ae2e1f 100644 --- a/arch/x86/boot/compressed/Makefile +++ b/arch/x86/boot/compressed/Makefile @@ -101,7 +101,7 @@ ifdef CONFIG_X86_64 endif =20 vmlinux-objs-$(CONFIG_ACPI) +=3D $(obj)/acpi.o -vmlinux-objs-$(CONFIG_INTEL_TDX_GUEST) +=3D $(obj)/tdx.o +vmlinux-objs-$(CONFIG_INTEL_TDX_GUEST) +=3D $(obj)/tdx.o $(obj)/tdcall.o =20 vmlinux-objs-$(CONFIG_EFI_MIXED) +=3D $(obj)/efi_thunk_$(BITS).o efi-obj-$(CONFIG_EFI_STUB) =3D $(objtree)/drivers/firmware/efi/libstub/lib= .a diff --git a/arch/x86/boot/compressed/tdcall.S b/arch/x86/boot/compressed/t= dcall.S new file mode 100644 index 000000000000..59b80ab6b41c --- /dev/null +++ b/arch/x86/boot/compressed/tdcall.S @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "../../coco/tdcall.S" diff --git a/arch/x86/boot/compressed/tdx.c b/arch/x86/boot/compressed/tdx.c index dec68c184358..499ccbd71312 100644 --- a/arch/x86/boot/compressed/tdx.c +++ b/arch/x86/boot/compressed/tdx.c @@ -2,6 +2,10 @@ =20 #include "../cpuflags.h" #include "../string.h" +#include "../io.h" + +#include +#include =20 #include =20 @@ -12,6 +16,66 @@ bool early_is_tdx_guest(void) return tdx_guest_detected; } =20 +static inline unsigned int tdx_io_in(int size, u16 port) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_IO_INSTRUCTION, + .r12 =3D size, + .r13 =3D 0, + .r14 =3D port, + }; + + if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT)) + return UINT_MAX; + + return args.r11; +} + +static inline void tdx_io_out(int size, u16 port, u32 value) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_IO_INSTRUCTION, + .r12 =3D size, + .r13 =3D 1, + .r14 =3D port, + .r15 =3D value, + }; + + __tdx_hypercall(&args, 0); +} + +static inline u8 tdx_inb(u16 port) +{ + return tdx_io_in(1, port); +} + +static inline u16 tdx_inw(u16 port) +{ + return tdx_io_in(2, port); +} + +static inline u32 tdx_inl(u16 port) +{ + return tdx_io_in(4, port); +} + +static inline void tdx_outb(u8 value, u16 port) +{ + tdx_io_out(1, port, value); +} + +static inline void tdx_outw(u16 value, u16 port) +{ + tdx_io_out(2, port, value); +} + +static inline void tdx_outl(u32 value, u16 port) +{ + tdx_io_out(4, port, value); +} + void early_tdx_detect(void) { u32 eax, sig[3]; @@ -24,4 +88,11 @@ void early_tdx_detect(void) =20 /* Cache TDX guest feature status */ tdx_guest_detected =3D true; + + pio_ops.inb =3D tdx_inb; + pio_ops.inw =3D tdx_inw; + pio_ops.inl =3D tdx_inl; + pio_ops.outb =3D tdx_outb; + pio_ops.outw =3D tdx_outw; + pio_ops.outl =3D tdx_outl; } diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 8209ba9ffe1a..51bce6351124 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -2,7 +2,36 @@ #ifndef _ASM_X86_SHARED_TDX_H #define _ASM_X86_SHARED_TDX_H =20 +#include +#include + +#define TDX_HYPERCALL_STANDARD 0 + +#define TDX_HCALL_HAS_OUTPUT BIT(0) +#define TDX_HCALL_ISSUE_STI BIT(1) + #define TDX_CPUID_LEAF_ID 0x21 #define TDX_IDENT "IntelTDX " =20 +#ifndef __ASSEMBLY__ + +/* + * Used in __tdx_hypercall() to pass down and get back registers' values of + * the TDCALL instruction when requesting services from the VMM. + * + * This is a software only structure and not part of the TDX module/VMM AB= I. + */ +struct tdx_hypercall_args { + u64 r10; + u64 r11; + u64 r12; + u64 r13; + u64 r14; + u64 r15; +}; + +/* Used to request services from the VMM */ +u64 __tdx_hypercall(struct tdx_hypercall_args *args, unsigned long flags); + +#endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_SHARED_TDX_H */ diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index d4c28b9f2fbc..54803cb6ccf5 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -3,16 +3,10 @@ #ifndef _ASM_X86_TDX_H #define _ASM_X86_TDX_H =20 -#include #include #include #include =20 -#define TDX_HYPERCALL_STANDARD 0 - -#define TDX_HCALL_HAS_OUTPUT BIT(0) -#define TDX_HCALL_ISSUE_STI BIT(1) - #define TDX_SEAMCALL_VMFAILINVALID 0x8000FF00FFFF0000ULL =20 #ifndef __ASSEMBLY__ @@ -32,21 +26,6 @@ struct tdx_module_output { u64 r11; }; =20 -/* - * Used in __tdx_hypercall() to pass down and get back registers' values of - * the TDCALL instruction when requesting services from the VMM. - * - * This is a software only structure and not part of the TDX module/VMM AB= I. - */ -struct tdx_hypercall_args { - u64 r10; - u64 r11; - u64 r12; - u64 r13; - u64 r14; - u64 r15; -}; - /* * Used by the #VE exception handler to gather the #VE exception * info from the TDX module. This is a software only structure @@ -71,9 +50,6 @@ void __init tdx_early_init(void); u64 __tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r9, struct tdx_module_output *out); =20 -/* Used to request services from the VMM */ -u64 __tdx_hypercall(struct tdx_hypercall_args *args, unsigned long flags); - void tdx_get_ve_info(struct ve_info *ve); =20 bool tdx_handle_virt_exception(struct pt_regs *regs, struct ve_info *ve); --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D55CC433EF for ; Thu, 24 Feb 2022 15:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236850AbiBXP67 (ORCPT ); Thu, 24 Feb 2022 10:58:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236890AbiBXP5u (ORCPT ); Thu, 24 Feb 2022 10:57:50 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6389FE408 for ; Thu, 24 Feb 2022 07:57:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718227; x=1677254227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fpM+R64ZJtHaEddcdRF4eznJG7BpiVFYKcTcY8Y1O6Y=; b=H+dJyArYyeaAKHw2vxAeI/F/HORODTyrweUaNlof+6oC/wKX74HfJEYj WcTjRGUVdwCgLCsSD3t6kz93qJFzZbtn4hOI4oQzAsklpAMDFj05lCppN G/i4jb15Vwdueez1z1VzhWlLBxsQXntidumiShVtGN7EfqkUeeyl4eAis glBcE60JbjUU/X44P3V9rsPoMp7ZAB4f2+0domVhOr9G0I0KXgzmQnpn5 6HZjHClBahYMNp0oMEXJGylaRpGJ5C8uXtMVwrn0WmyNx9Cqn86Qyrt4a U8IUsyHtcyQPqDOApPbvhLQaHpkNGYrTKBuunG09AFUM/BtwoSomPSg95 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="276893950" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="276893950" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="786966451" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga005.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 0EDBEAB1; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 17/30] x86/tdx: Add port I/O emulation Date: Thu, 24 Feb 2022 18:56:17 +0300 Message-Id: <20220224155630.52734-18-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan TDX hypervisors cannot emulate instructions directly. This includes port I/O which is normally emulated in the hypervisor. All port I/O instructions inside TDX trigger the #VE exception in the guest and would be normally emulated there. Use a hypercall to emulate port I/O. Extend the tdx_handle_virt_exception() and add support to handle the #VE due to port I/O instructions. String I/O operations are not supported in TDX. Unroll them by declaring CC_ATTR_GUEST_UNROLL_STRING_IO confidential computing attribute. Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Dan Williams Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/core.c | 7 +++++- arch/x86/coco/tdx.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 9113baebbfd2..5615b75e6fc6 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -18,7 +18,12 @@ static u64 cc_mask __ro_after_init; =20 static bool intel_cc_platform_has(enum cc_attr attr) { - return false; + switch (attr) { + case CC_ATTR_GUEST_UNROLL_STRING_IO: + return true; + default: + return false; + } } =20 /* diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 15519e498679..2e342760b1d2 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -19,6 +19,12 @@ #define EPT_READ 0 #define EPT_WRITE 1 =20 +/* See Exit Qualification for I/O Instructions in VMX documentation */ +#define VE_IS_IO_IN(e) ((e) & BIT(3)) +#define VE_GET_IO_SIZE(e) (((e) & GENMASK(2, 0)) + 1) +#define VE_GET_PORT_NUM(e) ((e) >> 16) +#define VE_IS_IO_STRING(e) ((e) & BIT(4)) + static struct { unsigned int gpa_width; unsigned long attributes; @@ -292,6 +298,52 @@ static bool handle_mmio(struct pt_regs *regs, struct v= e_info *ve) return true; } =20 +/* + * Emulate I/O using hypercall. + * + * Assumes the IO instruction was using ax, which is enforced + * by the standard io.h macros. + * + * Return True on success or False on failure. + */ +static bool handle_io(struct pt_regs *regs, u32 exit_qual) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D TDX_HYPERCALL_STANDARD, + .r11 =3D EXIT_REASON_IO_INSTRUCTION, + }; + int size, port; + u64 mask; + bool in, ret; + + if (VE_IS_IO_STRING(exit_qual)) + return false; + + in =3D VE_IS_IO_IN(exit_qual); + size =3D VE_GET_IO_SIZE(exit_qual); + port =3D VE_GET_PORT_NUM(exit_qual); + mask =3D GENMASK(BITS_PER_BYTE * size, 0); + + args.r12 =3D size; + args.r13 =3D !in; + args.r14 =3D port; + args.r15 =3D in ? 0 : regs->ax; + + /* + * Emulate the I/O read/write via hypercall. More info about + * ABI can be found in TDX Guest-Host-Communication Interface + * (GHCI) section titled "TDG.VP.VMCALL". + */ + ret =3D !__tdx_hypercall(&args, in ? TDX_HCALL_HAS_OUTPUT : 0); + if (!ret || !in) + return ret; + + regs->ax &=3D ~mask; + regs->ax |=3D ret ? args.r11 & mask : UINT_MAX; + + return ret; +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; @@ -347,6 +399,8 @@ static bool virt_exception_kernel(struct pt_regs *regs,= struct ve_info *ve) return handle_cpuid(regs); case EXIT_REASON_EPT_VIOLATION: return handle_mmio(regs, ve); + case EXIT_REASON_IO_INSTRUCTION: + return handle_io(regs, ve->exit_qual); default: pr_warn("Unexpected #VE: %lld\n", ve->exit_reason); return false; --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63EAAC433EF for ; Thu, 24 Feb 2022 15:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234413AbiBXP61 (ORCPT ); Thu, 24 Feb 2022 10:58:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236755AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19A2722BD2 for ; Thu, 24 Feb 2022 07:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718201; x=1677254201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SwPKQO76m89JoirDvi2nnnrqzpm+q2wRGmsqNDkdK+4=; b=WAKMSrUhdXMwnmQuxKHDNT9Pok13nObHvgDoQml9W+2Cf0RJBWRNPFx7 opd4m2kXhDmGi79ttJ0nwRaMccFPDgyT9rq0+BK+VC1nRMjWyGRGCNU6A VinLkOV6MbDZi9nma6s/M8JXJJpWDEgRn77qqjbbMtCJLPKxIiWZ3U+G4 FEPmy2EK+kJTyT69XK90/3RZsLKnZhq/GiGP+yN38xrIxeK/BYuOcyJQv zhndTWjI/xuufq9z5kAD0QUFwly2rWKiN8BA33mELuRaFYMNMXq6itL26 iCXe+n5gJoFkl3DT3UwP82bpqOct5G0hbQ81aj6XCVSe1ouC17rHx6+mz Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="232241507" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="232241507" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="707500703" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 1D16CABE; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 18/30] x86/tdx: Handle early boot port I/O Date: Thu, 24 Feb 2022 18:56:18 +0300 Message-Id: <20220224155630.52734-19-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andi Kleen TDX guests cannot do port I/O directly. The TDX module triggers a #VE exception to let the guest kernel emulate port I/O by converting them into TDCALLs to call the host. But before IDT handlers are set up, port I/O cannot be emulated using normal kernel #VE handlers. To support the #VE-based emulation during this boot window, add a minimal early #VE handler support in early exception handlers. This is similar to what AMD SEV does. This is mainly to support earlyprintk's serial driver, as well as potentially the VGA driver. The early handler only supports I/O-related #VE exceptions. Unhandled or failed exceptions will be handled via early_fixup_exceptions() (like normal exception failures). Signed-off-by: Andi Kleen Reviewed-by: Dan Williams Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner Acked-by: Dave Hansen --- arch/x86/coco/tdx.c | 16 ++++++++++++++++ arch/x86/include/asm/tdx.h | 4 ++++ arch/x86/kernel/head64.c | 3 +++ 3 files changed, 23 insertions(+) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 2e342760b1d2..0d2a4c947a6c 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -344,6 +344,22 @@ static bool handle_io(struct pt_regs *regs, u32 exit_q= ual) return ret; } =20 +/* + * Early #VE exception handler. Only handles a subset of port I/O. + * Intended only for earlyprintk. If failed, return false. + */ +__init bool tdx_early_handle_ve(struct pt_regs *regs) +{ + struct ve_info ve; + + tdx_get_ve_info(&ve); + + if (ve.exit_reason !=3D EXIT_REASON_IO_INSTRUCTION) + return false; + + return handle_io(regs, ve.exit_qual); +} + void tdx_get_ve_info(struct ve_info *ve) { struct tdx_module_output out; diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 54803cb6ccf5..ba0f8c2b185c 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -56,11 +56,15 @@ bool tdx_handle_virt_exception(struct pt_regs *regs, st= ruct ve_info *ve); =20 void tdx_safe_halt(void); =20 +bool tdx_early_handle_ve(struct pt_regs *regs); + #else =20 static inline void tdx_early_init(void) { }; static inline void tdx_safe_halt(void) { }; =20 +static inline bool tdx_early_handle_ve(struct pt_regs *regs) { return fals= e; } + #endif /* CONFIG_INTEL_TDX_GUEST */ =20 #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index 6dff50c3edd6..ecbf50e5b8e0 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -417,6 +417,9 @@ void __init do_early_exception(struct pt_regs *regs, in= t trapnr) trapnr =3D=3D X86_TRAP_VC && handle_vc_boot_ghcb(regs)) return; =20 + if (trapnr =3D=3D X86_TRAP_VE && tdx_early_handle_ve(regs)) + return; + early_fixup_exception(regs, trapnr); } =20 --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04DF3C433EF for ; Thu, 24 Feb 2022 15:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236743AbiBXP6J (ORCPT ); Thu, 24 Feb 2022 10:58:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236746AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DAE06254 for ; Thu, 24 Feb 2022 07:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718199; x=1677254199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xp0xgqqv4QlVaVqygotoWIoNj1oLYlEvw9zIP2LN2X0=; b=VKfYWpZWQJbR4wOrTSJraDvrmGUyuY7MOhzlHvv8u913fLMEjKCLhGCr TyjWoG4ZW+R/2Sfc0LbwejZn5eYEme9Cgca7OHL0FdTpzKkuC1XCt/b6I 7+WeQJ1vysBzJnIvBB0i1hEdIlzMwQW+osJYjvoppHSpQxd5Tm65ms8hr ztIn2j8VmGI91ZeftwuHsSmrWEZ7u9HWJD5m6fkEnPMIAPbslnPijnFF4 t2vjWgLBL0kTrqHkeanJykUhsYbP8S96Or5gTJeWoh4RosMICXH/XgaDV 5KjfaH+V/tRU/cpj6v4nbmxShn4lB8FS9cUf+irIdsngGfBITklAMIloL A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="249849321" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="249849321" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628513011" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 2A0E8ABF; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 19/30] x86/tdx: Wire up KVM hypercalls Date: Thu, 24 Feb 2022 18:56:19 +0300 Message-Id: <20220224155630.52734-20-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan KVM hypercalls use the VMCALL or VMMCALL instructions. Although the ABI is similar, those instructions no longer function for TDX guests. Make vendor-specific TDVMCALLs instead of VMCALL. This enables TDX guests to run with KVM acting as the hypervisor. Among other things, KVM hypercall is used to send IPIs. Since the KVM driver can be built as a kernel module, export tdx_kvm_hypercall() to make the symbols visible to kvm.ko. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner --- arch/x86/coco/tdx.c | 17 +++++++++++++++++ arch/x86/include/asm/kvm_para.h | 22 ++++++++++++++++++++++ arch/x86/include/asm/tdx.h | 11 +++++++++++ 3 files changed, 50 insertions(+) diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 0d2a4c947a6c..6306ef19584f 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -48,6 +48,23 @@ static inline u64 _tdx_hypercall(u64 fn, u64 r12, u64 r1= 3, u64 r14, u64 r15) return __tdx_hypercall(&args, 0); } =20 +#ifdef CONFIG_KVM_GUEST +long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, unsigned long p2, + unsigned long p3, unsigned long p4) +{ + struct tdx_hypercall_args args =3D { + .r10 =3D nr, + .r11 =3D p1, + .r12 =3D p2, + .r13 =3D p3, + .r14 =3D p4, + }; + + return __tdx_hypercall(&args, 0); +} +EXPORT_SYMBOL_GPL(tdx_kvm_hypercall); +#endif + static inline void tdx_module_call(u64 fn, u64 rcx, u64 rdx, u64 r8, u64 r= 9, struct tdx_module_output *out) { diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_par= a.h index 56935ebb1dfe..57bc74e112f2 100644 --- a/arch/x86/include/asm/kvm_para.h +++ b/arch/x86/include/asm/kvm_para.h @@ -7,6 +7,8 @@ #include #include =20 +#include + #ifdef CONFIG_KVM_GUEST bool kvm_check_and_clear_guest_paused(void); #else @@ -32,6 +34,10 @@ static inline bool kvm_check_and_clear_guest_paused(void) static inline long kvm_hypercall0(unsigned int nr) { long ret; + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return tdx_kvm_hypercall(nr, 0, 0, 0, 0); + asm volatile(KVM_HYPERCALL : "=3Da"(ret) : "a"(nr) @@ -42,6 +48,10 @@ static inline long kvm_hypercall0(unsigned int nr) static inline long kvm_hypercall1(unsigned int nr, unsigned long p1) { long ret; + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return tdx_kvm_hypercall(nr, p1, 0, 0, 0); + asm volatile(KVM_HYPERCALL : "=3Da"(ret) : "a"(nr), "b"(p1) @@ -53,6 +63,10 @@ static inline long kvm_hypercall2(unsigned int nr, unsig= ned long p1, unsigned long p2) { long ret; + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return tdx_kvm_hypercall(nr, p1, p2, 0, 0); + asm volatile(KVM_HYPERCALL : "=3Da"(ret) : "a"(nr), "b"(p1), "c"(p2) @@ -64,6 +78,10 @@ static inline long kvm_hypercall3(unsigned int nr, unsig= ned long p1, unsigned long p2, unsigned long p3) { long ret; + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return tdx_kvm_hypercall(nr, p1, p2, p3, 0); + asm volatile(KVM_HYPERCALL : "=3Da"(ret) : "a"(nr), "b"(p1), "c"(p2), "d"(p3) @@ -76,6 +94,10 @@ static inline long kvm_hypercall4(unsigned int nr, unsig= ned long p1, unsigned long p4) { long ret; + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return tdx_kvm_hypercall(nr, p1, p2, p3, p4); + asm volatile(KVM_HYPERCALL : "=3Da"(ret) : "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index ba0f8c2b185c..6a97d42b0de9 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -67,5 +67,16 @@ static inline bool tdx_early_handle_ve(struct pt_regs *r= egs) { return false; } =20 #endif /* CONFIG_INTEL_TDX_GUEST */ =20 +#if defined(CONFIG_KVM_GUEST) && defined(CONFIG_INTEL_TDX_GUEST) +long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, unsigned long p2, + unsigned long p3, unsigned long p4); +#else +static inline long tdx_kvm_hypercall(unsigned int nr, unsigned long p1, + unsigned long p2, unsigned long p3, + unsigned long p4) +{ + return -ENODEV; +} +#endif /* CONFIG_INTEL_TDX_GUEST && CONFIG_KVM_GUEST */ #endif /* !__ASSEMBLY__ */ #endif /* _ASM_X86_TDX_H */ --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0CA5C4321E for ; Thu, 24 Feb 2022 15:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234887AbiBXP55 (ORCPT ); Thu, 24 Feb 2022 10:57:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236744AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E86213F0D for ; Thu, 24 Feb 2022 07:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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24 Feb 2022 07:56:31 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 38296ADD; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, Sean Christopherson , "Kirill A . Shutemov" Subject: [PATCHv4 20/30] x86/boot: Add a trampoline for booting APs via firmware handoff Date: Thu, 24 Feb 2022 18:56:20 +0300 Message-Id: <20220224155630.52734-21-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Historically, x86 platforms have booted secondary processors (APs) using INIT followed by the start up IPI (SIPI) messages. In regular VMs, this boot sequence is supported by the VMM emulation. But such a wakeup model is fatal for secure VMs like TDX in which VMM is an untrusted entity. To address this issue, a new wakeup model was added in ACPI v6.4, in which firmware (like TDX virtual BIOS) will help boot the APs. More details about this wakeup model can be found in ACPI specification v6.4, the section titled "Multiprocessor Wakeup Structure". Since the existing trampoline code requires processors to boot in real mode with 16-bit addressing, it will not work for this wakeup model (because it boots the AP in 64-bit mode). To handle it, extend the trampoline code to support 64-bit mode firmware handoff. Also, extend IDT and GDT pointers to support 64-bit mode hand off. There is no TDX-specific detection for this new boot method. The kernel will rely on it as the sole boot method whenever the new ACPI structure is present. The ACPI table parser for the MADT multiprocessor wake up structure and the wakeup method that uses this structure will be added by the following patch in this series. Signed-off-by: Sean Christopherson Reviewed-by: Andi Kleen Reviewed-by: Dan Williams Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/realmode.h | 1 + arch/x86/kernel/smpboot.c | 12 ++++++-- arch/x86/realmode/rm/header.S | 1 + arch/x86/realmode/rm/trampoline_64.S | 38 ++++++++++++++++++++++++ arch/x86/realmode/rm/trampoline_common.S | 12 +++++++- 6 files changed, 63 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 48067af94678..35006e151774 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -328,6 +328,8 @@ struct apic { =20 /* wakeup_secondary_cpu */ int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); + /* wakeup secondary CPU using 64-bit wakeup point */ + int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); =20 void (*inquire_remote_apic)(int apicid); =20 diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmod= e.h index 331474b150f1..fd6f6e5b755a 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -25,6 +25,7 @@ struct real_mode_header { u32 sev_es_trampoline_start; #endif #ifdef CONFIG_X86_64 + u32 trampoline_start64; u32 trampoline_pgd; #endif /* ACPI S3 wakeup */ diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 617012f4619f..6269dd126dba 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1088,6 +1088,11 @@ static int do_boot_cpu(int apicid, int cpu, struct t= ask_struct *idle, unsigned long boot_error =3D 0; unsigned long timeout; =20 +#ifdef CONFIG_X86_64 + /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ + if (apic->wakeup_secondary_cpu_64) + start_ip =3D real_mode_header->trampoline_start64; +#endif idle->thread.sp =3D (unsigned long)task_pt_regs(idle); early_gdt_descr.address =3D (unsigned long)get_cpu_gdt_rw(cpu); initial_code =3D (unsigned long)start_secondary; @@ -1129,11 +1134,14 @@ static int do_boot_cpu(int apicid, int cpu, struct = task_struct *idle, =20 /* * Wake up a CPU in difference cases: - * - Use the method in the APIC driver if it's defined + * - Use a method from the APIC driver if one defined, with wakeup + * straight to 64-bit mode preferred over wakeup to RM. * Otherwise, * - Use an INIT boot APIC message for APs or NMI for BSP. */ - if (apic->wakeup_secondary_cpu) + if (apic->wakeup_secondary_cpu_64) + boot_error =3D apic->wakeup_secondary_cpu_64(apicid, start_ip); + else if (apic->wakeup_secondary_cpu) boot_error =3D apic->wakeup_secondary_cpu(apicid, start_ip); else boot_error =3D wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, diff --git a/arch/x86/realmode/rm/header.S b/arch/x86/realmode/rm/header.S index 8c1db5bf5d78..2eb62be6d256 100644 --- a/arch/x86/realmode/rm/header.S +++ b/arch/x86/realmode/rm/header.S @@ -24,6 +24,7 @@ SYM_DATA_START(real_mode_header) .long pa_sev_es_trampoline_start #endif #ifdef CONFIG_X86_64 + .long pa_trampoline_start64 .long pa_trampoline_pgd; #endif /* ACPI S3 wakeup */ diff --git a/arch/x86/realmode/rm/trampoline_64.S b/arch/x86/realmode/rm/tr= ampoline_64.S index cc8391f86cdb..ae112a91592f 100644 --- a/arch/x86/realmode/rm/trampoline_64.S +++ b/arch/x86/realmode/rm/trampoline_64.S @@ -161,6 +161,19 @@ SYM_CODE_START(startup_32) ljmpl $__KERNEL_CS, $pa_startup_64 SYM_CODE_END(startup_32) =20 +SYM_CODE_START(pa_trampoline_compat) + /* + * In compatibility mode. Prep ESP and DX for startup_32, then disable + * paging and complete the switch to legacy 32-bit mode. + */ + movl $rm_stack_end, %esp + movw $__KERNEL_DS, %dx + + movl $X86_CR0_PE, %eax + movl %eax, %cr0 + ljmpl $__KERNEL32_CS, $pa_startup_32 +SYM_CODE_END(pa_trampoline_compat) + .section ".text64","ax" .code64 .balign 4 @@ -169,6 +182,20 @@ SYM_CODE_START(startup_64) jmpq *tr_start(%rip) SYM_CODE_END(startup_64) =20 +SYM_CODE_START(trampoline_start64) + /* + * APs start here on a direct transfer from 64-bit BIOS with identity + * mapped page tables. Load the kernel's GDT in order to gear down to + * 32-bit mode (to handle 4-level vs. 5-level paging), and to (re)load + * segment registers. Load the zero IDT so any fault triggers a + * shutdown instead of jumping back into BIOS. + */ + lidt tr_idt(%rip) + lgdt tr_gdt64(%rip) + + ljmpl *tr_compat(%rip) +SYM_CODE_END(trampoline_start64) + .section ".rodata","a" # Duplicate the global descriptor table # so the kernel can live anywhere @@ -182,6 +209,17 @@ SYM_DATA_START(tr_gdt) .quad 0x00cf93000000ffff # __KERNEL_DS SYM_DATA_END_LABEL(tr_gdt, SYM_L_LOCAL, tr_gdt_end) =20 +SYM_DATA_START(tr_gdt64) + .short tr_gdt_end - tr_gdt - 1 # gdt limit + .long pa_tr_gdt + .long 0 +SYM_DATA_END(tr_gdt64) + +SYM_DATA_START(tr_compat) + .long pa_trampoline_compat + .short __KERNEL32_CS +SYM_DATA_END(tr_compat) + .bss .balign PAGE_SIZE SYM_DATA(trampoline_pgd, .space PAGE_SIZE) diff --git a/arch/x86/realmode/rm/trampoline_common.S b/arch/x86/realmode/r= m/trampoline_common.S index 5033e640f957..4331c32c47f8 100644 --- a/arch/x86/realmode/rm/trampoline_common.S +++ b/arch/x86/realmode/rm/trampoline_common.S @@ -1,4 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 */ .section ".rodata","a" .balign 16 -SYM_DATA_LOCAL(tr_idt, .fill 1, 6, 0) + +/* + * When a bootloader hands off to the kernel in 32-bit mode an + * IDT with a 2-byte limit and 4-byte base is needed. When a boot + * loader hands off to a kernel 64-bit mode the base address + * extends to 8-bytes. Reserve enough space for either scenario. + */ +SYM_DATA_START_LOCAL(tr_idt) + .short 0 + .quad 0 +SYM_DATA_END(tr_idt) --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16D9CC433EF for ; Thu, 24 Feb 2022 15:58:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235566AbiBXP6t (ORCPT ); Thu, 24 Feb 2022 10:58:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236792AbiBXP53 (ORCPT ); Thu, 24 Feb 2022 10:57:29 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE3715418C for ; Thu, 24 Feb 2022 07:56:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718208; x=1677254208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EvrY+fLFyt0AjjIeJc3eqvET5iI6uNtGs7idg2+y+vU=; b=IMEor9lgUdDP/LZQmGxceSBuzCo6mLkKIOh96hRlcHpXVE7nBLakvA5n QXpk/HZS0rgl7S5sFQyc8vvaojDVSHDynBB6gFMwQ3o39ohJUzgUgNxO4 o6FvrEuHcsTbLtuDKbV8LNs8y8ZDJhmZ5iDR2NdNvj/g1oSy3kEAZ1fIY KgjNUVrX8mUefOk5uKhS2OtOdo6KrSLR0XKhZG0uWlv+R13JTZJhhn18q Ta0yqVr6F7e47AfbQbEPecyqTUYJ6++R21nvqXjw7gdjicpJJ0KTEtMbG SVHpaYe3Oi37NottHugXq9khZacDtkOXLoVyL3sCRDEGhLkCBqJ+sJBN2 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="252186800" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="252186800" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="684315495" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 49005B0C; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, Sean Christopherson , "Rafael J . Wysocki" , "Kirill A . Shutemov" Subject: [PATCHv4 21/30] x86/acpi, x86/boot: Add multiprocessor wake-up support Date: Thu, 24 Feb 2022 18:56:21 +0300 Message-Id: <20220224155630.52734-22-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan TDX cannot use INIT/SIPI protocol to bring up secondary CPUs because it requires assistance from untrusted VMM. For platforms that do not support SIPI/INIT, ACPI defines a wakeup model (using mailbox) via MADT multiprocessor wakeup structure. More details about it can be found in ACPI specification v6.4, the section titled "Multiprocessor Wakeup Structure". If a platform firmware produces the multiprocessor wakeup structure, then OS may use this new mailbox-based mechanism to wake up the APs. Add ACPI MADT wake structure parsing support for x86 platform and if MADT wake table is present, update apic->wakeup_secondary_cpu_64 with new API which uses MADT wake mailbox to wake-up CPU. Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Reviewed-by: Andi Kleen Reviewed-by: Rafael J. Wysocki Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/apic.h | 5 ++ arch/x86/kernel/acpi/boot.c | 118 ++++++++++++++++++++++++++++++++++++ arch/x86/kernel/apic/apic.c | 10 +++ 3 files changed, 133 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 35006e151774..bd8ae0a7010a 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -490,6 +490,11 @@ static inline unsigned int read_apic_id(void) return apic->get_apic_id(reg); } =20 +#ifdef CONFIG_X86_64 +typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); +extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); +#endif + extern int default_apic_id_valid(u32 apicid); extern int default_acpi_madt_oem_check(char *, char *); extern void default_setup_apic_routing(void); diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 5b6d1a95776f..99518eac2bbc 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -65,6 +65,15 @@ static u64 acpi_lapic_addr __initdata =3D APIC_DEFAULT_P= HYS_BASE; static bool acpi_support_online_capable; #endif =20 +#ifdef CONFIG_X86_64 +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr; +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; +/* Lock to protect mailbox (acpi_mp_wake_mailbox) from parallel access */ +static DEFINE_SPINLOCK(mailbox_lock); +#endif + #ifdef CONFIG_X86_IO_APIC /* * Locks related to IOAPIC hotplug @@ -336,6 +345,84 @@ acpi_parse_lapic_nmi(union acpi_subtable_headers * hea= der, const unsigned long e return 0; } =20 +#ifdef CONFIG_X86_64 +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static int acpi_wakeup_cpu(int apicid, unsigned long start_ip) +{ + static physid_mask_t apic_id_wakemap =3D PHYSID_MASK_NONE; + u8 timeout; + + /* Remap mailbox memory only for the first call to acpi_wakeup_cpu() */ + if (physids_empty(apic_id_wakemap)) { + acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * According to the ACPI specification r6.4, section titled + * "Multiprocessor Wakeup Structure" the mailbox-based wakeup + * mechanism cannot be used more than once for the same CPU. + * Skip wakeups if they are attempted more than once. + */ + if (physid_isset(apicid, apic_id_wakemap)) { + pr_err("CPU already awake (APIC ID %x), skipping wakeup\n", + apicid); + return -EINVAL; + } + + spin_lock(&mailbox_lock); + + /* + * Mailbox memory is shared between firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, CPU associated with the given apicid will be booted. + * + * The value of apic_id and wakeup_vector has to be set before updating + * the wakeup command. To let compiler preserve order of writes, use + * smp_store_release. + */ + smp_store_release(&acpi_mp_wake_mailbox->apic_id, apicid); + smp_store_release(&acpi_mp_wake_mailbox->wakeup_vector, start_ip); + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * After writing the wakeup command, wait for maximum timeout of 0xFF + * for firmware to reset the command address back zero to indicate + * the successful reception of command. + * NOTE: 0xFF as timeout value is decided based on our experiments. + * + * XXX: Change the timeout once ACPI specification comes up with + * standard maximum timeout value. + */ + timeout =3D 0xFF; + while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + cpu_relax(); + + /* If timed out (timeout =3D=3D 0), return error */ + if (!timeout) { + /* + * XXX: Is there a recovery path after timeout is hit? + * Spec is unclear. Reset command to 0 if timeout is hit. + */ + acpi_mp_wake_mailbox->command =3D 0; + spin_unlock(&mailbox_lock); + return -EIO; + } + + /* + * If the CPU wakeup process is successful, store the + * status in apic_id_wakemap to prevent re-wakeup + * requests. + */ + physid_set(apicid, apic_id_wakemap); + + spin_unlock(&mailbox_lock); + + return 0; +} +#endif #endif /*CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1083,6 +1170,29 @@ static int __init acpi_parse_madt_lapic_entries(void) } return 0; } + +#ifdef CONFIG_X86_64 +static int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_multiproc_wakeup *mp_wake; + + if (!IS_ENABLED(CONFIG_SMP)) + return -ENODEV; + + mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; + if (BAD_MADT_ENTRY(mp_wake, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; + + acpi_wake_cpu_handler_update(acpi_wakeup_cpu); + + return 0; +} +#endif /* CONFIG_X86_64 */ #endif /* CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1278,6 +1388,14 @@ static void __init acpi_process_madt(void) =20 smp_found_config =3D 1; } + +#ifdef CONFIG_X86_64 + /* + * Parse MADT MP Wake entry. + */ + acpi_table_parse_madt(ACPI_MADT_TYPE_MULTIPROC_WAKEUP, + acpi_parse_mp_wake, 1); +#endif } if (error =3D=3D -EINVAL) { /* diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index b70344bf6600..3c8f2c797a98 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2551,6 +2551,16 @@ u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool= extid) } EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); =20 +#ifdef CONFIG_X86_64 +void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) +{ + struct apic **drv; + + for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) + (*drv)->wakeup_secondary_cpu_64 =3D handler; +} +#endif + /* * Override the generic EOI implementation with an optimized version. * Only called during early boot when only one CPU is active and with --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B0B9C433F5 for ; Thu, 24 Feb 2022 15:58:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiBXP71 (ORCPT ); Thu, 24 Feb 2022 10:59:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236909AbiBXP5v (ORCPT ); Thu, 24 Feb 2022 10:57:51 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88BD91323E1 for ; Thu, 24 Feb 2022 07:57:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718231; x=1677254231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XeiDSHDhSk1ZAnWl9C35VO6F89iKjoQMuwzkA1dSo5A=; b=Er6PL2blp4iUxE6EwPpd4NFrnGEiaE1n18gruakgIwM6D5sZm+7gIWrx 0dki3wdfE+R7yfP0JsG2ZGS40+IR3bU9o1lwkNN02tZZQ9laHmwWfyaR4 XzWAxDgEdbNwAkcsamhTw2hQxeZ+pzYhvlSv3l5209A4swOoYAxSHSSY1 GbQPZK8XaCdXCZUVppdJPoO85hSlYOOCKmE/Sk73rrcqj38jZJMy7KVXf QDExb9YOCOI+YnkDi0MzcarALCrGy3XhrGa10rR2+TO5Pr4iVWRQBtc/4 e6OZF8cjWoEMpKHajTiw+U8RBzC0n8g8ycPzflcY0my2+g3sA2+ouQDEh g==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487722" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487722" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="508914554" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga006.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 55F9DB0F; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 22/30] x86/boot: Set CR0.NE early and keep it set during the boot Date: Thu, 24 Feb 2022 18:56:22 +0300 Message-Id: <20220224155630.52734-23-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TDX guest requires CR0.NE to be set. Clearing the bit triggers #GP(0). If CR0.NE is 0, the MS-DOS compatibility mode for handling floating-point exceptions is selected. In this mode, the software exception handler for floating-point exceptions is invoked externally using the processor=E2=80= =99s FERR#, INTR, and IGNNE# pins. Using FERR# and IGNNE# to handle floating-point exception is deprecated. CR0.NE=3D0 also limits newer processors to operate with one logical processor active. Kernel uses CR0_STATE constant to initialize CR0. It has NE bit set. But during early boot kernel has more ad-hoc approach to setting bit in the register. Make CR0 initialization consistent, deriving the initial value of CR0 from CR0_STATE. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/compressed/head_64.S | 7 ++++--- arch/x86/realmode/rm/trampoline_64.S | 8 ++++---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/= head_64.S index fd9441f40457..d0c3d33f3542 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -289,7 +289,7 @@ SYM_FUNC_START(startup_32) pushl %eax =20 /* Enter paged protected Mode, activating Long Mode */ - movl $(X86_CR0_PG | X86_CR0_PE), %eax /* Enable Paging and Protected mode= */ + movl $CR0_STATE, %eax movl %eax, %cr0 =20 /* Jump from 32bit compatibility mode into 64bit mode. */ @@ -662,8 +662,9 @@ SYM_CODE_START(trampoline_32bit_src) pushl $__KERNEL_CS pushl %eax =20 - /* Enable paging again */ - movl $(X86_CR0_PG | X86_CR0_PE), %eax + /* Enable paging again. */ + movl %cr0, %eax + btsl $X86_CR0_PG_BIT, %eax movl %eax, %cr0 =20 lret diff --git a/arch/x86/realmode/rm/trampoline_64.S b/arch/x86/realmode/rm/tr= ampoline_64.S index ae112a91592f..d380f2d1fd23 100644 --- a/arch/x86/realmode/rm/trampoline_64.S +++ b/arch/x86/realmode/rm/trampoline_64.S @@ -70,7 +70,7 @@ SYM_CODE_START(trampoline_start) movw $__KERNEL_DS, %dx # Data segment descriptor =20 # Enable protected mode - movl $X86_CR0_PE, %eax # protected mode (PE) bit + movl $(CR0_STATE & ~X86_CR0_PG), %eax movl %eax, %cr0 # into protected mode =20 # flush prefetch and jump to startup_32 @@ -148,8 +148,8 @@ SYM_CODE_START(startup_32) movl $MSR_EFER, %ecx wrmsr =20 - # Enable paging and in turn activate Long Mode - movl $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax + # Enable paging and in turn activate Long Mode. + movl $CR0_STATE, %eax movl %eax, %cr0 =20 /* @@ -169,7 +169,7 @@ SYM_CODE_START(pa_trampoline_compat) movl $rm_stack_end, %esp movw $__KERNEL_DS, %dx =20 - movl $X86_CR0_PE, %eax + movl $(CR0_STATE & ~X86_CR0_PG), %eax movl %eax, %cr0 ljmpl $__KERNEL32_CS, $pa_startup_32 SYM_CODE_END(pa_trampoline_compat) --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E114C433EF for ; Thu, 24 Feb 2022 15:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233239AbiBXP6C (ORCPT ); Thu, 24 Feb 2022 10:58:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236751AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D90064F8 for ; Thu, 24 Feb 2022 07:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718199; x=1677254199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jw3+L9J/up2HJodxYOGI6M1WsdFVeMG1Qu1QbhliuCY=; b=FGn/A5xCIu/UUyUNhFrVoNn0IzfZOtINmkEfeyOCPQaylKncRE+jT2S9 bDAw8MgjyNB3Y4WhWv0py9wJVBFdczMiORbDGvOZQ/B5PsAOaOSBpnHnu GDCuLr64Nr38zBTrc1VtDV0ntIv0FmE6GttOpJGBxY2V4slW6YDYq/Alb V9xuiyFCamHe8fQ/2vwpAs/sJZpKQ0OnJ2CCuCNQFz/OhMvRNO8nw/CKZ xgcpeNjMPfkBjWYr2UjUlRf76gMGuCmj1B2lVD6v2uGdlU+EATXG7wMqu Qv+qryYoX95A1FTZFcPHFef8VEF5TFvjyvHNNzIOQq8DCTBp9SLf6kzbi w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="252186792" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="252186792" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="684315492" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 637F8B1F; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 23/30] x86/boot: Avoid #VE during boot for TDX platforms Date: Thu, 24 Feb 2022 18:56:23 +0300 Message-Id: <20220224155630.52734-24-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sean Christopherson There are a few MSRs and control register bits that the kernel normally needs to modify during boot. But, TDX disallows modification of these registers to help provide consistent security guarantees. Fortunately, TDX ensures that these are all in the correct state before the kernel loads, which means the kernel does not need to modify them. The conditions to avoid are: * Any writes to the EFER MSR * Clearing CR3.MCE This theoretically makes the guest boot more fragile. If, for instance, EFER was set up incorrectly and a WRMSR was performed, it will trigger early exception panic or a triple fault, if it's before early exceptions are set up. However, this is likely to trip up the guest BIOS long before control reaches the kernel. In any case, these kinds of problems are unlikely to occur in production environments, and developers have good debug tools to fix them quickly. Change the common boot code to work on TDX and non-TDX systems. This should have no functional effect on non-TDX systems. Signed-off-by: Sean Christopherson Reviewed-by: Andi Kleen Reviewed-by: Dan Williams Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 1 + arch/x86/boot/compressed/head_64.S | 20 ++++++++++++++++++-- arch/x86/boot/compressed/pgtable.h | 2 +- arch/x86/kernel/head_64.S | 28 ++++++++++++++++++++++++++-- arch/x86/realmode/rm/trampoline_64.S | 13 ++++++++++++- 5 files changed, 58 insertions(+), 6 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d2f45e58e846..98efb35ed7b1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -886,6 +886,7 @@ config INTEL_TDX_GUEST depends on X86_X2APIC select ARCH_HAS_CC_PLATFORM select DYNAMIC_PHYSICAL_MASK + select X86_MCE help Support running as a guest under Intel TDX. Without this support, the guest kernel can not boot or run under TDX. diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/= head_64.S index d0c3d33f3542..6d903b2fc544 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -643,12 +643,28 @@ SYM_CODE_START(trampoline_32bit_src) movl $MSR_EFER, %ecx rdmsr btsl $_EFER_LME, %eax + /* Avoid writing EFER if no change was made (for TDX guest) */ + jc 1f wrmsr - popl %edx +1: popl %edx popl %ecx =20 +#ifdef CONFIG_X86_MCE + /* + * Preserve CR4.MCE if the kernel will enable #MC support. + * Clearing MCE may fault in some environments (that also force #MC + * support). Any machine check that occurs before #MC support is fully + * configured will crash the system regardless of the CR4.MCE value set + * here. + */ + movl %cr4, %eax + andl $X86_CR4_MCE, %eax +#else + movl $0, %eax +#endif + /* Enable PAE and LA57 (if required) paging modes */ - movl $X86_CR4_PAE, %eax + orl $X86_CR4_PAE, %eax testl %edx, %edx jz 1f orl $X86_CR4_LA57, %eax diff --git a/arch/x86/boot/compressed/pgtable.h b/arch/x86/boot/compressed/= pgtable.h index 6ff7e81b5628..cc9b2529a086 100644 --- a/arch/x86/boot/compressed/pgtable.h +++ b/arch/x86/boot/compressed/pgtable.h @@ -6,7 +6,7 @@ #define TRAMPOLINE_32BIT_PGTABLE_OFFSET 0 =20 #define TRAMPOLINE_32BIT_CODE_OFFSET PAGE_SIZE -#define TRAMPOLINE_32BIT_CODE_SIZE 0x70 +#define TRAMPOLINE_32BIT_CODE_SIZE 0x80 =20 #define TRAMPOLINE_32BIT_STACK_END TRAMPOLINE_32BIT_SIZE =20 diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 9c63fc5988cd..184b7468ea76 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -140,8 +140,22 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) addq $(init_top_pgt - __START_KERNEL_map), %rax 1: =20 +#ifdef CONFIG_X86_MCE + /* + * Preserve CR4.MCE if the kernel will enable #MC support. + * Clearing MCE may fault in some environments (that also force #MC + * support). Any machine check that occurs before #MC support is fully + * configured will crash the system regardless of the CR4.MCE value set + * here. + */ + movq %cr4, %rcx + andl $X86_CR4_MCE, %ecx +#else + movl $0, %ecx +#endif + /* Enable PAE mode, PGE and LA57 */ - movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx + orl $(X86_CR4_PAE | X86_CR4_PGE), %ecx #ifdef CONFIG_X86_5LEVEL testl $1, __pgtable_l5_enabled(%rip) jz 1f @@ -246,13 +260,23 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) /* Setup EFER (Extended Feature Enable Register) */ movl $MSR_EFER, %ecx rdmsr + /* + * Preserve current value of EFER for comparison and to skip + * EFER writes if no change was made (for TDX guest) + */ + movl %eax, %edx btsl $_EFER_SCE, %eax /* Enable System Call */ btl $20,%edi /* No Execute supported? */ jnc 1f btsl $_EFER_NX, %eax btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) -1: wrmsr /* Make changes effective */ =20 + /* Avoid writing EFER if no change was made (for TDX guest) */ +1: cmpl %edx, %eax + je 1f + xor %edx, %edx + wrmsr /* Make changes effective */ +1: /* Setup cr0 */ movl $CR0_STATE, %eax /* Make changes effective */ diff --git a/arch/x86/realmode/rm/trampoline_64.S b/arch/x86/realmode/rm/tr= ampoline_64.S index d380f2d1fd23..e38d61d6562e 100644 --- a/arch/x86/realmode/rm/trampoline_64.S +++ b/arch/x86/realmode/rm/trampoline_64.S @@ -143,11 +143,22 @@ SYM_CODE_START(startup_32) movl %eax, %cr3 =20 # Set up EFER + movl $MSR_EFER, %ecx + rdmsr + /* + * Skip writing to EFER if the register already has desired + * value (to avoid #VE for the TDX guest). + */ + cmp pa_tr_efer, %eax + jne .Lwrite_efer + cmp pa_tr_efer + 4, %edx + je .Ldone_efer +.Lwrite_efer: movl pa_tr_efer, %eax movl pa_tr_efer + 4, %edx - movl $MSR_EFER, %ecx wrmsr =20 +.Ldone_efer: # Enable paging and in turn activate Long Mode. movl $CR0_STATE, %eax movl %eax, %cr0 --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19457C433F5 for ; Thu, 24 Feb 2022 15:57:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236745AbiBXP6N (ORCPT ); Thu, 24 Feb 2022 10:58:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236748AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D40264DB for ; Thu, 24 Feb 2022 07:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718199; x=1677254199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q7UkitiuT+GdBLhgi9ovK3JIVhbOcenWO7329OdQmvk=; b=Nv6d/Dyyt2LP9RlvlxOT9poaM0VSDGZa02nQFrc9o435u29zB6y9UKcw s+yki9cotfDQXj4oTTt/+uCmpSREn2W9NLk85SihLnjMows8NO2QhPHt9 MkzqOthk0a/K5vg0r/QzwqZTwmFEQxIakOPhxHMct78dmwE2F73I3QVgi nR243i6iw9m4AkWWn3AxSH1OsONTLpDPWecTOvEgmlzp9jk2BCoIZIlPT 4m0Lo9q1vV5aAwuAGuwIe4TqFNjAAc92Ewu/GU1eNHoODs16dR4Ps64Q9 JzcvSNQe/2MuzEpDfEzDwyuvD7neqfAlN/2dBSjzea9LkU3473VGAaJYn A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="312983032" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="312983032" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="506362100" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 707DDB30; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 24/30] x86/topology: Disable CPU online/offline control for TDX guests Date: Thu, 24 Feb 2022 18:56:24 +0300 Message-Id: <20220224155630.52734-25-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan Unlike regular VMs, TDX guests use the firmware hand-off wakeup method to wake up the APs during the boot process. This wakeup model uses a mailbox to communicate with firmware to bring up the APs. As per the design, this mailbox can only be used once for the given AP, which means after the APs are booted, the same mailbox cannot be used to offline/online the given AP. More details about this requirement can be found in Intel TDX Virtual Firmware Design Guide, sec titled "AP initialization in OS" and in sec titled "Hotplug Device". Since the architecture does not support any method of offlining the CPUs, disable CPU hotplug support in the kernel. Since this hotplug disable feature can be re-used by other VM guests, add a new CC attribute CC_ATTR_HOTPLUG_DISABLED and use it to disable the hotplug support. With hotplug disabled, /sys/devices/system/cpu/cpuX/online sysfs option will not exist for TDX guests. Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/core.c | 1 + include/linux/cc_platform.h | 10 ++++++++++ kernel/cpu.c | 7 +++++++ 3 files changed, 18 insertions(+) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 5615b75e6fc6..54344122e2fe 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -20,6 +20,7 @@ static bool intel_cc_platform_has(enum cc_attr attr) { switch (attr) { case CC_ATTR_GUEST_UNROLL_STRING_IO: + case CC_ATTR_HOTPLUG_DISABLED: return true; default: return false; diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index efd8205282da..691494bbaf5a 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -72,6 +72,16 @@ enum cc_attr { * Examples include TDX guest & SEV. */ CC_ATTR_GUEST_UNROLL_STRING_IO, + + /** + * @CC_ATTR_HOTPLUG_DISABLED: Hotplug is not supported or disabled. + * + * The platform/OS is running as a guest/virtual machine does not + * support CPU hotplug feature. + * + * Examples include TDX Guest. + */ + CC_ATTR_HOTPLUG_DISABLED, }; =20 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM diff --git a/kernel/cpu.c b/kernel/cpu.c index f39eb0b52dfe..c94f00fa34d3 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 #include #define CREATE_TRACE_POINTS @@ -1185,6 +1186,12 @@ static int __ref _cpu_down(unsigned int cpu, int tas= ks_frozen, =20 static int cpu_down_maps_locked(unsigned int cpu, enum cpuhp_state target) { + /* + * If the platform does not support hotplug, report it explicitly to + * differentiate it from a transient offlining failure. + */ + if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED)) + return -EOPNOTSUPP; if (cpu_hotplug_disabled) return -EBUSY; return _cpu_down(cpu, 0, target); --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33387C433F5 for ; Thu, 24 Feb 2022 15:58:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236954AbiBXP7V (ORCPT ); Thu, 24 Feb 2022 10:59:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236910AbiBXP5v (ORCPT ); Thu, 24 Feb 2022 10:57:51 -0500 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82FF4131F7E for ; Thu, 24 Feb 2022 07:57:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718231; x=1677254231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8/5iP14Tg24GtfulUdmcNudmbOpBuYqe/UqX13ONj68=; b=J6qzH5tLQEOEbF5O+7LHo2IpZLy9O1s19K7C/q5QsPk3fXaIJ6XzRLHW +p4k0KOia2SLEMSDyGzL1+HgJBSnqTfHMGcBParkLR7sqyzZij8gLO8b8 v24X4fZ2MGUlRsU5qTtFcHCNBrPE09nVqyNX4xKpfCsakZjNdfqxv7zQD dE/2DBFrUo8ybP3l+PWa9wGTGkSDb4qe71Ff60yCDzfOeVOVswDrE7Ui2 lm0j1PnQanWyKABzmFg1MoDf6uGP5S8G1xHV39jjZN23UWBfaDmt46/hs bVeoJczaBoxbOyVVjddpaXpobTmGc9uHkMez7G4OtyKkAkD/UTIeB60Di Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="315487715" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="315487715" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="592128137" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 7E86EB34; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 25/30] x86/tdx: Make pages shared in ioremap() Date: Thu, 24 Feb 2022 18:56:25 +0300 Message-Id: <20220224155630.52734-26-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In TDX guests, guest memory is protected from host access. If a guest performs I/O, it needs to explicitly share the I/O memory with the host. Make all ioremap()ed pages that are not backed by normal memory (IORES_DESC_NONE or IORES_DESC_RESERVED) mapped as shared. Since TDX memory encryption support is similar to AMD SEV architecture, reuse the infrastructure from AMD SEV code. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/ioremap.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 026031b3b782..a5d4ec1afca2 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -242,10 +242,15 @@ __ioremap_caller(resource_size_t phys_addr, unsigned = long size, * If the page being mapped is in memory and SEV is active then * make sure the memory encryption attribute is enabled in the * resulting mapping. + * In TDX guests, memory is marked private by default. If encryption + * is not requested (using encrypted), explicitly set decrypt + * attribute in all IOREMAPPED memory. */ prot =3D PAGE_KERNEL_IO; if ((io_desc.flags & IORES_MAP_ENCRYPTED) || encrypted) prot =3D pgprot_encrypted(prot); + else + prot =3D pgprot_decrypted(prot); =20 switch (pcm) { case _PAGE_CACHE_MODE_UC: --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AACBC433F5 for ; Thu, 24 Feb 2022 15:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236853AbiBXP6T (ORCPT ); Thu, 24 Feb 2022 10:58:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236754AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E47E22B38 for ; Thu, 24 Feb 2022 07:56:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718201; x=1677254201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4CAGEue28CSAv5dFniItlUtImlUxHadBv6bonwqT43o=; b=meMp58/xVrf1FjBEWfAu7Wzw8ApyavONxnLL+Q9ETOF3RrTXDaky7bco Crl6e8Imbd0GvOJeODsbJlGEZEZVYN30jet3PUgnqiqbieyZsFu7YuFwW 8ez1dRUp7nrU3HpEPqbPsoXWeGv0b+AFwIBvL0gqvd35cbqAHkh5HOHiY N3ciX0PNsT50Lk6FbuCS3RxwdsZez3lDMyd5O8znWjAEq1yqov4fh4erQ yQjPDmaaEr9h3Ny7QAPGPDOQe3uJX/T8d7sZfuF/ZHtiGd75MTT84RCr3 HC2UQO4JlHPfX6zrB0YHUe8iyLMeWZic+AhRY6HCMX8DQoNs1wtRWB/wg g==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="251094406" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="251094406" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="639761340" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 8C257B83; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 26/30] x86/mm/cpa: Add support for TDX shared memory Date: Thu, 24 Feb 2022 18:56:26 +0300 Message-Id: <20220224155630.52734-27-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel TDX protects guest memory from VMM access. Any memory that is required for communication with the VMM must be explicitly shared. It is a two-step process: the guest sets the shared bit in the page table entry and notifies VMM about the change. The notification happens using MapGPA hypercall. Conversion back to private memory requires clearing the shared bit, notifying VMM with MapGPA hypercall following with accepting the memory with AcceptPage hypercall. Provide a TDX version of x86_platform.guest.* callbacks. It makes __set_memory_enc_pgtable() work right in TDX guest. Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/core.c | 1 + arch/x86/coco/tdx.c | 101 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 54344122e2fe..9778cf4c6901 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -21,6 +21,7 @@ static bool intel_cc_platform_has(enum cc_attr attr) switch (attr) { case CC_ATTR_GUEST_UNROLL_STRING_IO: case CC_ATTR_HOTPLUG_DISABLED: + case CC_ATTR_GUEST_MEM_ENCRYPT: return true; default: return false; diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index 6306ef19584f..da2ae399ea71 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -10,10 +10,15 @@ #include #include #include +#include =20 /* TDX module Call Leaf IDs */ #define TDX_GET_INFO 1 #define TDX_GET_VEINFO 3 +#define TDX_ACCEPT_PAGE 6 + +/* TDX hypercall Leaf IDs */ +#define TDVMCALL_MAP_GPA 0x10001 =20 /* MMIO direction */ #define EPT_READ 0 @@ -456,6 +461,98 @@ bool tdx_handle_virt_exception(struct pt_regs *regs, s= truct ve_info *ve) return ret; } =20 +static bool tdx_tlb_flush_required(bool enc) +{ + /* + * TDX guest is responsible for flushing caches on private->shared + * transition. VMM is responsible for flushing on shared->private. + */ + return !enc; +} + +static bool tdx_cache_flush_required(void) +{ + return true; +} + +static bool accept_page(phys_addr_t gpa, enum pg_level pg_level) +{ + /* + * Pass the page physical address to the TDX module to accept the + * pending, private page. + * + * Bits 2:0 of GPA encode page size: 0 - 4K, 1 - 2M, 2 - 1G. + */ + switch (pg_level) { + case PG_LEVEL_4K: + break; + case PG_LEVEL_2M: + gpa |=3D 1; + break; + case PG_LEVEL_1G: + gpa |=3D 2; + break; + default: + return false; + } + + return !__tdx_module_call(TDX_ACCEPT_PAGE, gpa, 0, 0, 0, NULL); +} + +/* + * Inform the VMM of the guest's intent for this physical page: shared with + * the VMM or private to the guest. The VMM is expected to change its map= ping + * of the page in response. + */ +static bool tdx_enc_status_changed(unsigned long vaddr, int numpages, bool= enc) +{ + phys_addr_t start =3D __pa(vaddr); + phys_addr_t end =3D __pa(vaddr + numpages * PAGE_SIZE); + + if (!enc) { + start |=3D cc_mkdec(0); + end |=3D cc_mkdec(0); + } + + /* + * Notify the VMM about page mapping conversion. More info about ABI + * can be found in TDX Guest-Host-Communication Interface (GHCI), + * section "TDG.VP.VMCALL" + */ + if (_tdx_hypercall(TDVMCALL_MAP_GPA, start, end - start, 0, 0)) + return false; + + /* private->shared conversion requires only MapGPA call */ + if (!enc) + return true; + + /* + * For shared->private conversion, accept the page using + * TDX_ACCEPT_PAGE TDX module call. + */ + while (start < end) { + /* Try if 1G page accept is possible */ + if (!(start & ~PUD_MASK) && end - start >=3D PUD_SIZE && + accept_page(start, PG_LEVEL_1G)) { + start +=3D PUD_SIZE; + continue; + } + + /* Try if 2M page accept is possible */ + if (!(start & ~PMD_MASK) && end - start >=3D PMD_SIZE && + accept_page(start, PG_LEVEL_2M)) { + start +=3D PMD_SIZE; + continue; + } + + if (!accept_page(start, PG_LEVEL_4K)) + return false; + start +=3D PAGE_SIZE; + } + + return true; +} + void __init tdx_early_init(void) { u32 eax, sig[3]; @@ -486,5 +583,9 @@ void __init tdx_early_init(void) */ cc_set_mask(BIT_ULL(td_info.gpa_width - 1)); =20 + x86_platform.guest.enc_cache_flush_required =3D tdx_cache_flush_required; + x86_platform.guest.enc_tlb_flush_required =3D tdx_tlb_flush_required; + x86_platform.guest.enc_status_change_finish =3D tdx_enc_status_changed; + pr_info("Guest detected\n"); } --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EBC6C433EF for ; Thu, 24 Feb 2022 15:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236723AbiBXP63 (ORCPT ); Thu, 24 Feb 2022 10:58:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236756AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34FBC2459A for ; Thu, 24 Feb 2022 07:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718201; x=1677254201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XimhzMtjfzZRQ2oEagC60/R6lppXl0bYHqXI4i6UzHE=; b=NMA/CIpRvnQd4qbXKdNvwaTLFFD4+p8XSOxqjm9zxtOLW/xvSirD70W5 o9/pNueJuTgEUVcgyQrVsdP2rPZEtoNsKhW1m3dICsSJiGS0l4frjJt+y NiGEYPRZ72dR290hwbYoODEVrkWVNq4IHG0kXCnkM2E8stdbG1el9G8MK 2TDC5w+F3HHMnBe1fAJKaomNFQLNzQWX/FvjQ5uo89Uo+x+rSCFHtzfqN gSglJlSGHPQxoZY2Ubg4TZQpS/gGqWWcu5lEvgV4pCbeRUyHXvXoFGyrU p7KEdy8UEhVp7hQAZ8UCGeUVow0T2pqrm0IuBe84kF3J6V603ehPvk1KL w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="232241514" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="232241514" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="707500705" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 99C27BB6; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 27/30] x86/kvm: Use bounce buffers for TD guest Date: Thu, 24 Feb 2022 18:56:27 +0300 Message-Id: <20220224155630.52734-28-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel TDX doesn't allow VMM to directly access guest private memory. Any memory that is required for communication with the VMM must be shared explicitly. The same rule applies for any DMA to and from the TDX guest. All DMA pages have to be marked as shared pages. A generic way to achieve this without any changes to device drivers is to use the SWIOTLB framework. Force SWIOTLB on TD guest and make SWIOTLB buffer shared by generalizing mem_encrypt_init() to cover TDX. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 2 +- arch/x86/coco/core.c | 1 + arch/x86/coco/tdx.c | 3 +++ arch/x86/mm/mem_encrypt.c | 9 ++++++++- 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 98efb35ed7b1..1312cefb927d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -885,7 +885,7 @@ config INTEL_TDX_GUEST depends on X86_64 && CPU_SUP_INTEL depends on X86_X2APIC select ARCH_HAS_CC_PLATFORM - select DYNAMIC_PHYSICAL_MASK + select X86_MEM_ENCRYPT select X86_MCE help Support running as a guest under Intel TDX. Without this support, diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index 9778cf4c6901..b10326f91d4f 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -22,6 +22,7 @@ static bool intel_cc_platform_has(enum cc_attr attr) case CC_ATTR_GUEST_UNROLL_STRING_IO: case CC_ATTR_HOTPLUG_DISABLED: case CC_ATTR_GUEST_MEM_ENCRYPT: + case CC_ATTR_MEM_ENCRYPT: return true; default: return false; diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c index da2ae399ea71..d33f65a58d7b 100644 --- a/arch/x86/coco/tdx.c +++ b/arch/x86/coco/tdx.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "tdx: " fmt =20 #include +#include #include #include #include @@ -587,5 +588,7 @@ void __init tdx_early_init(void) x86_platform.guest.enc_tlb_flush_required =3D tdx_tlb_flush_required; x86_platform.guest.enc_status_change_finish =3D tdx_enc_status_changed; =20 + swiotlb_force =3D SWIOTLB_FORCE; + pr_info("Guest detected\n"); } diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 50d209939c66..10ee40b5204b 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -42,7 +42,14 @@ bool force_dma_unencrypted(struct device *dev) =20 static void print_mem_encrypt_feature_info(void) { - pr_info("AMD Memory Encryption Features active:"); + pr_info("Memory Encryption Features active:"); + + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) { + pr_cont(" Intel TDX\n"); + return; + } + + pr_cont("AMD "); =20 /* Secure Memory Encryption */ if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) { --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E45AC433EF for ; Thu, 24 Feb 2022 15:58:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231845AbiBXP6k (ORCPT ); Thu, 24 Feb 2022 10:58:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236734AbiBXP5V (ORCPT ); Thu, 24 Feb 2022 10:57:21 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9615931523 for ; Thu, 24 Feb 2022 07:56:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718204; x=1677254204; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DW9pAtssQrVzCNn2gqeVtI5pY8kVmDUWj3D0oTCwzJY=; b=jNiFrWbhXil2SIddFuDCusoJ1W/VWMuTEu1aieDHbSxxxcbCn+7pIJIP ccKOJQq0r5VYLt8/yiI/CIIqmLJLe663dn5S+EO+lszJT1T9vcAwPoiGj xpWgBAXdmxeGts4R4m0kZsUXjJSlWa4EwIJk8vTWEeh6V/5suqzmz5hOn BOhZZwgz2X3qvVWaxkDdY0+FA2r6zm0DXCeVK2JdzevIfmszPGxkHpk+T 8mCUov2ZTwDXeuorulccKHqEwQ9HE7tAg95uUlxMj+D6iNl+svBdYg3lf xiNa+hurvPGn9KOzftkINKEwRg0fg4VcI6hbbvmW3iV0VxGn1gAmzevpZ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="232241517" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="232241517" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="592128142" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id A79BFBD6; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, Isaku Yamahata , "Kirill A . Shutemov" Subject: [PATCHv4 28/30] x86/tdx: ioapic: Add shared bit for IOAPIC base address Date: Thu, 24 Feb 2022 18:56:28 +0300 Message-Id: <20220224155630.52734-29-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata The kernel interacts with each bare-metal IOAPIC with a special MMIO page. When running under KVM, the guest's IOAPICs are emulated by KVM. When running as a TDX guest, the guest needs to mark each IOAPIC mapping as "shared" with the host. This ensures that TDX private protections are not applied to the page, which allows the TDX host emulation to work. ioremap()-created mappings such as virtio will be marked as shared by default. However, the IOAPIC code does not use ioremap() and instead uses the fixmap mechanism. Introduce a special fixmap helper just for the IOAPIC code. Ensure that it marks IOAPIC pages as "shared". This replaces set_fixmap_nocache() with __set_fixmap() since __set_fixmap() allows custom 'prot' values. AMD SEV gets IOAPIC pages shared because FIXMAP_PAGE_NOCACHE has _ENC bit clear. TDX has to set bit to share the page with the host. Signed-off-by: Isaku Yamahata Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/apic/io_apic.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index c1bb384935b0..d775f58a3c3e 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -49,6 +49,7 @@ #include #include #include +#include =20 #include #include @@ -65,6 +66,7 @@ #include #include #include +#include =20 #define for_each_ioapic(idx) \ for ((idx) =3D 0; (idx) < nr_ioapics; (idx)++) @@ -2677,6 +2679,15 @@ static struct resource * __init ioapic_setup_resourc= es(void) return res; } =20 +static void io_apic_set_fixmap_nocache(enum fixed_addresses idx, + phys_addr_t phys) +{ + pgprot_t flags =3D FIXMAP_PAGE_NOCACHE; + + flags =3D pgprot_decrypted(flags); + __set_fixmap(idx, phys, flags); +} + void __init io_apic_init_mappings(void) { unsigned long ioapic_phys, idx =3D FIX_IO_APIC_BASE_0; @@ -2709,7 +2720,7 @@ void __init io_apic_init_mappings(void) __func__, PAGE_SIZE, PAGE_SIZE); ioapic_phys =3D __pa(ioapic_phys); } - set_fixmap_nocache(idx, ioapic_phys); + io_apic_set_fixmap_nocache(idx, ioapic_phys); apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys); @@ -2838,7 +2849,7 @@ int mp_register_ioapic(int id, u32 address, u32 gsi_b= ase, ioapics[idx].mp_config.flags =3D MPC_APIC_USABLE; ioapics[idx].mp_config.apicaddr =3D address; =20 - set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); + io_apic_set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); if (bad_ioapic_register(idx)) { clear_fixmap(FIX_IO_APIC_BASE_0 + idx); return -ENODEV; --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83E31C433F5 for ; Thu, 24 Feb 2022 15:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230274AbiBXP6X (ORCPT ); Thu, 24 Feb 2022 10:58:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236723AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1983422BC8 for ; Thu, 24 Feb 2022 07:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718201; x=1677254201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aMt9dMQFnuWJAh9cVzkqMUEeYOnZHiNvm0HEf2p9qHU=; b=lXuCa+iwUVti7N3VDEAB9CS6A1zl4MUIdYHZdwssyjhGO/Xox1UGHF6D 0sgbUD6VHmm8WIa+zIfzo2426FN5fIAgMB9s3JhWBifYallPs+XRyvICs ewAogf3nJTsXYQ1pDDRUdDg5MaNfgD1fAXi2uMiajoc2YUcxvk7ucazKM xzh3DWv83QDRK2DngM2F5A6x4l1BlxIuKS9uYwc3M1PAu+OgmRgjxneHi EOJ2ToiPq1jUnpKo6GDfEiYMkfVL7+43UuMlbQUtDLWE89On95DgGZ4Wb uMlQFkJGkREG+nThCYoxB2XkssUUQp5XeN2Ptxhv6sZRpb/aCvXNGcMLn w==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="312983041" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="312983041" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="506362116" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id B1E38C7E; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 29/30] ACPICA: Avoid cache flush on TDX guest Date: Thu, 24 Feb 2022 18:56:29 +0300 Message-Id: <20220224155630.52734-30-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ACPI_FLUSH_CPU_CACHE() flushes caches on entering sleep states. It is required to prevent data loss. While running inside TDX guest, the kernel can bypass cache flushing. Changing sleep state in a virtual machine doesn't affect the host system sleep state and cannot lead to data loss. The approach can be generalized to all guest kernels, but, to be cautious, let's limit it to TDX for now. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/acenv.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/acenv.h b/arch/x86/include/asm/acenv.h index 9aff97f0de7f..d19deca6dd27 100644 --- a/arch/x86/include/asm/acenv.h +++ b/arch/x86/include/asm/acenv.h @@ -13,7 +13,21 @@ =20 /* Asm macros */ =20 -#define ACPI_FLUSH_CPU_CACHE() wbinvd() +/* + * ACPI_FLUSH_CPU_CACHE() flushes caches on entering sleep states. + * It is required to prevent data loss. + * + * While running inside TDX guest, the kernel can bypass cache flushing. + * Changing sleep state in a virtual machine doesn't affect the host system + * sleep state and cannot lead to data loss. + * + * TODO: Is it safe to generalize this from TDX guests to all guest kernel= s? + */ +#define ACPI_FLUSH_CPU_CACHE() \ +do { \ + if (!cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) \ + wbinvd(); \ +} while (0) =20 int __acpi_acquire_global_lock(unsigned int *lock); int __acpi_release_global_lock(unsigned int *lock); --=20 2.34.1 From nobody Tue Jun 23 22:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84816C433F5 for ; Thu, 24 Feb 2022 15:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236764AbiBXP6Q (ORCPT ); Thu, 24 Feb 2022 10:58:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236718AbiBXP5Q (ORCPT ); Thu, 24 Feb 2022 10:57:16 -0500 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED9DD1D32D for ; Thu, 24 Feb 2022 07:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645718199; x=1677254199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nx39V8by9O+7Km3Oh4t8SlBikR+pt9SMuFh5fskeUTc=; b=EvVM3qTMkNSn1qbLcf09bt6x7dAUI44PV0zTApsPc0lHacOtFsegeqUG 700gnx/o6/9UVW0m5OEPAjpUjcDN5061nXt72tBgbZ6nFvyL/+nl1wwgS Cixv59Dm8LAKpZuWO12QdhzTcZX8wLZOXcTsfHByNPec2Cgci9n+XB7MZ saarN82xh03E6Stc/dvvveqRAX7P+nd3YW5138TEyEY7T8R5WRug0lZCI Fd7rNo+O8yJRM/OtL49605HcJKT8KYOU2wEGqeepm60nsu0vPBab2q8j4 PI6KiQBaVG7x8YI1Oa8w5sLeIZLGsZ8FewRKVBWlUmSmAqVTSnpT6rNrw Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10268"; a="249849330" X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="249849330" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 07:56:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,134,1643702400"; d="scan'208";a="628513019" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2022 07:56:32 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id BCA71C98; Thu, 24 Feb 2022 17:56:35 +0200 (EET) From: "Kirill A. Shutemov" To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com, ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com, hpa@zytor.com, jgross@suse.com, jmattson@google.com, joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org, pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com, tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com, thomas.lendacky@amd.com, brijesh.singh@amd.com, x86@kernel.org, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv4 30/30] Documentation/x86: Document TDX kernel architecture Date: Thu, 24 Feb 2022 18:56:30 +0300 Message-Id: <20220224155630.52734-31-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kuppuswamy Sathyanarayanan Document the TDX guest architecture details like #VE support, shared memory, etc. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov --- Documentation/x86/index.rst | 1 + Documentation/x86/tdx.rst | 196 ++++++++++++++++++++++++++++++++++++ 2 files changed, 197 insertions(+) create mode 100644 Documentation/x86/tdx.rst diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst index f498f1d36cd3..382e53ca850a 100644 --- a/Documentation/x86/index.rst +++ b/Documentation/x86/index.rst @@ -24,6 +24,7 @@ x86-specific Documentation intel-iommu intel_txt amd-memory-encryption + tdx pti mds microcode diff --git a/Documentation/x86/tdx.rst b/Documentation/x86/tdx.rst new file mode 100644 index 000000000000..a0b603ac49ca --- /dev/null +++ b/Documentation/x86/tdx.rst @@ -0,0 +1,196 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Intel Trust Domain Extensions (TDX) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Intel's Trust Domain Extensions (TDX) protect confidential guest VMs +from the host and physical attacks by isolating the guest register +state and by encrypting the guest memory. In TDX, a special TDX module +sits between the host and the guest, and runs in a special mode and +manages the guest/host separation. + +Since the host cannot directly access guest registers or memory, much +normal functionality of a hypervisor (such as trapping MMIO, some MSRs, +some CPUIDs, and some other instructions) has to be moved into the +guest. This is implemented using a Virtualization Exception (#VE) that +is handled by the guest kernel. Some #VEs are handled inside the guest +kernel, but some require the hypervisor (VMM) to be involved. The TD +hypercall mechanism allows TD guests to call TDX module or hypervisor +function. + +#VE Exceptions: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +In TDX guests, #VE Exceptions are delivered to TDX guests in following +scenarios: + +* Execution of certain instructions (see list below) +* Certain MSR accesses. +* CPUID usage (only for certain leaves) +* Shared memory access (including MMIO) + +#VE due to instruction execution +--------------------------------- + +Intel TDX dis-allows execution of certain instructions in non-root +mode. Execution of these instructions would lead to #VE or #GP. + +Details are, + +List of instructions that can cause a #VE is, + +* String I/O (INS, OUTS), IN, OUT +* HLT +* MONITOR, MWAIT +* WBINVD, INVD +* VMCALL + +List of instructions that can cause a #GP is, + +* All VMX instructions: INVEPT, INVVPID, VMCLEAR, VMFUNC, VMLAUNCH, + VMPTRLD, VMPTRST, VMREAD, VMRESUME, VMWRITE, VMXOFF, VMXON +* ENCLS, ENCLV +* GETSEC +* RSM +* ENQCMD + +#VE due to MSR access +---------------------- + +In TDX guest, MSR access behavior can be categorized as, + +* Native supported (also called "context switched MSR") + No special handling is required for these MSRs in TDX guests. +* #GP triggered + Dis-allowed MSR read/write would lead to #GP. +* #VE triggered + All MSRs that are not natively supported or dis-allowed + (triggers #GP) will trigger #VE. To support access to + these MSRs, it needs to be emulated using TDCALL. + +Look Intel TDX Module Specification, sec "MSR Virtualization" for the comp= lete +list of MSRs that fall under the categories above. + +#VE due to CPUID instruction +---------------------------- + +In TDX guests, most of CPUID leaf/sub-leaf combinations are virtualized by +the TDX module while some trigger #VE. Whether the leaf/sub-leaf triggers = #VE +defined in the TDX spec. + +VMM during the TD initialization time (using TDH.MNG.INIT) configures if +a feature bits in specific leaf-subleaf are exposed to TD guest or not. + +#VE on Memory Accesses +---------------------- + +A TD guest is in control of whether its memory accesses are treated as +private or shared. It selects the behavior with a bit in its page table +entries. + +#VE on Shared Pages +------------------- + +Access to shared mappings can cause a #VE. The hypervisor controls whether +access of shared mapping causes a #VE, so the guest must be careful to only +reference shared pages it can safely handle a #VE, avoid nested #VEs. + +Content of shared mapping is not trusted since shared memory is writable +by the hypervisor. Shared mappings are never used for sensitive memory con= tent +like stacks or kernel text, only for I/O buffers and MMIO regions. The ker= nel +will not encounter shared mappings in sensitive contexts like syscall entry +or NMIs. + +#VE on Private Pages +-------------------- + +Some accesses to private mappings may cause #VEs. Before a mapping is +accepted (AKA in the SEPT_PENDING state), a reference would cause a #VE. +But, after acceptance, references typically succeed. + +The hypervisor can cause a private page reference to fail if it chooses +to move an accepted page to a "blocked" state. However, if it does +this, page access will not generate a #VE. It will, instead, cause a +"TD Exit" where the hypervisor is required to handle the exception. + +Linux #VE handler +----------------- + +Both user/kernel #VE exceptions are handled by the tdx_handle_virt_excepti= on() +handler. If successfully handled, the instruction pointer is incremented to +complete the handling process. If failed to handle, it is treated as a reg= ular +exception and handled via fixup handlers. + +In TD guests, #VE nesting (a #VE triggered before handling the current one +or AKA syscall gap issue) problem is handled by TDX module ensuring that +interrupts, including NMIs, are blocked. The hardware blocks interrupts +starting with #VE delivery until TDGETVEINFO is called. + +The kernel must avoid triggering #VE in entry paths: do not touch TD-shared +memory, including MMIO regions, and do not use #VE triggering MSRs, +instructions, or CPUID leaves that might generate #VE. + +MMIO handling: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +In non-TDX VMs, MMIO is usually implemented by giving a guest access to a +mapping which will cause a VMEXIT on access, and then the VMM emulates the +access. That's not possible in TDX guests because VMEXIT will expose the +register state to the host. TDX guests don't trust the host and can't have +their state exposed to the host. + +In TDX the MMIO regions are instead configured to trigger a #VE +exception in the guest. The guest #VE handler then emulates the MMIO +instructions inside the guest and converts them into a controlled TDCALL +to the host, rather than completely exposing the state to the host. + +MMIO addresses on x86 are just special physical addresses. They can be +accessed with any instruction that accesses memory. However, the +introduced instruction decoding method is limited. It is only designed +to decode instructions like those generated by io.h macros. + +MMIO access via other means (like structure overlays) may result in +MMIO_DECODE_FAILED and an oops. + +Shared memory: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Intel TDX doesn't allow the VMM to access guest private memory. Any +memory that is required for communication with VMM must be shared +explicitly by setting the bit in the page table entry. The shared bit +can be enumerated with TDX_GET_INFO. + +After setting the shared bit, the conversion must be completed with +MapGPA hypercall. The call informs the VMM about the conversion between +private/shared mappings. + +set_memory_decrypted() converts a range of pages to shared. +set_memory_encrypted() converts memory back to private. + +Device drivers are the primary user of shared memory, but there's no +need in touching every driver. DMA buffers and ioremap()'ed regions are +converted to shared automatically. + +TDX uses SWIOTLB for most DMA allocations. The SWIOTLB buffer is +converted to shared on boot. + +For coherent DMA allocation, the DMA buffer gets converted on the +allocation. Check force_dma_unencrypted() for details. + +References +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +More details about TDX module (and its response for MSR, memory access, +IO, CPUID etc) can be found at, + +https://www.intel.com/content/dam/develop/external/us/en/documents/tdx-mod= ule-1.0-public-spec-v0.931.pdf + +More details about TDX hypercall and TDX module call ABI can be found +at, + +https://www.intel.com/content/dam/develop/external/us/en/documents/intel-t= dx-guest-hypervisor-communication-interface-1.0-344426-002.pdf + +More details about TDVF requirements can be found at, + +https://www.intel.com/content/dam/develop/external/us/en/documents/tdx-vir= tual-firmware-design-guide-rev-1.01.pdf --=20 2.34.1