From nobody Thu Jun 25 02:04:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD932C433EF for ; Thu, 24 Feb 2022 11:39:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234102AbiBXLj2 (ORCPT ); Thu, 24 Feb 2022 06:39:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233634AbiBXLjL (ORCPT ); Thu, 24 Feb 2022 06:39:11 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AD151A58EA; Thu, 24 Feb 2022 03:38:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1645702721; x=1677238721; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=JrRPEFKeXWcc6jAXtUVnif+wj03hnZPozhAYD5BNe3k=; b=YohyELoDu7SBrBBUmLGrTpRy5yutwrYpT2WQZJ60NTszOPcZxWVp2bCQ Z9DxuP9U23fXk2ZsDp00nLHz9VAXEfX05T6FpTWDBCPhhCXDlTyNGjvBm 5Pwg9l7asUlVynsno3aRM9g/d8g+S2ETY0nejJlfN28274mquFKom2+yY J9RNC5+RTv8p8F/LkegdCBh0Y4MYjDiIVbDudHhpdHZxSPw+OfeLSXTv9 RUiZdpYMM0sD/9dWa6IYaSY7HHVwyjOCKX01CV/RQAgcqwfoNVTKAYHaY 8aPF0s9LVfx9cD7fVKLKPZWFxit6xHQ7KN+94rTreUnul7hYJZ1aPdi3A A==; From: Vincent Whitchurch To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Maxime Coquelin CC: , Vincent Whitchurch , Lars Persson , Srinivas Kandagatla , , , , Subject: [PATCH v2] net: stmmac: only enable DMA interrupts when ready Date: Thu, 24 Feb 2022 12:38:29 +0100 Message-ID: <20220224113829.1092859-1-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In this driver's ->ndo_open() callback, it enables DMA interrupts, starts the DMA channels, then requests interrupts with request_irq(), and then finally enables napi. If RX DMA interrupts are received before napi is enabled, no processing is done because napi_schedule_prep() will return false. If the network has a lot of broadcast/multicast traffic, then the RX ring could fill up completely before napi is enabled. When this happens, no further RX interrupts will be delivered, and the driver will fail to receive any packets. Fix this by only enabling DMA interrupts after all other initialization is complete. Fixes: 523f11b5d4fd72efb ("net: stmmac: move hardware setup for stmmac_open= to new function") Reported-by: Lars Persson Signed-off-by: Vincent Whitchurch --- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 6708ca2aa4f7..43978558d6c0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2260,6 +2260,23 @@ static void stmmac_stop_tx_dma(struct stmmac_priv *p= riv, u32 chan) stmmac_stop_tx(priv, priv->ioaddr, chan); } =20 +static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) +{ + u32 rx_channels_count =3D priv->plat->rx_queues_to_use; + u32 tx_channels_count =3D priv->plat->tx_queues_to_use; + u32 dma_csr_ch =3D max(rx_channels_count, tx_channels_count); + u32 chan; + + for (chan =3D 0; chan < dma_csr_ch; chan++) { + struct stmmac_channel *ch =3D &priv->channel[chan]; + unsigned long flags; + + spin_lock_irqsave(&ch->lock, flags); + stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); + spin_unlock_irqrestore(&ch->lock, flags); + } +} + /** * stmmac_start_all_dma - start all RX and TX DMA channels * @priv: driver private structure @@ -2902,8 +2919,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv= *priv) stmmac_axi(priv, priv->ioaddr, priv->plat->axi); =20 /* DMA CSR Channel configuration */ - for (chan =3D 0; chan < dma_csr_ch; chan++) + for (chan =3D 0; chan < dma_csr_ch; chan++) { stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); + stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); + } =20 /* DMA RX Channel Configuration */ for (chan =3D 0; chan < rx_channels_count; chan++) { @@ -3759,6 +3778,7 @@ static int stmmac_open(struct net_device *dev) =20 stmmac_enable_all_queues(priv); netif_tx_start_all_queues(priv->dev); + stmmac_enable_all_dma_irq(priv); =20 return 0; =20 @@ -6508,8 +6528,10 @@ int stmmac_xdp_open(struct net_device *dev) } =20 /* DMA CSR Channel configuration */ - for (chan =3D 0; chan < dma_csr_ch; chan++) + for (chan =3D 0; chan < dma_csr_ch; chan++) { stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); + stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); + } =20 /* Adjust Split header */ sph_en =3D (priv->hw->rx_csum > 0) && priv->sph; @@ -6570,6 +6592,7 @@ int stmmac_xdp_open(struct net_device *dev) stmmac_enable_all_queues(priv); netif_carrier_on(dev); netif_tx_start_all_queues(dev); + stmmac_enable_all_dma_irq(priv); =20 return 0; =20 @@ -7447,6 +7470,7 @@ int stmmac_resume(struct device *dev) stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); =20 stmmac_enable_all_queues(priv); + stmmac_enable_all_dma_irq(priv); =20 mutex_unlock(&priv->lock); rtnl_unlock(); --=20 2.34.1