From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC3FC4167B for ; Wed, 23 Feb 2022 19:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244399AbiBWTap (ORCPT ); Wed, 23 Feb 2022 14:30:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244388AbiBWTaj (ORCPT ); Wed, 23 Feb 2022 14:30:39 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A3F648306 for ; Wed, 23 Feb 2022 11:30:11 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id 132so21082565pga.5 for ; Wed, 23 Feb 2022 11:30:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aJgvldvrl+SGje7vrvMudPyYsFoVLhwI/Ka2l1gBY/s=; b=nTOsXOYFNaeVYWW9de9YzaPs+KiyjGUOfNXdvHadquxYeYwIpEJdNzVHUd+8yDk0NR 8b5ejz5XpC6YiQ3cEhC2ebi1ty7yAJ7CR8sk5aZvWMl/JC1RiKl5ythybqNLqSh3mgup f45OiV1fDI2T3F2J01nU7IojZXo+pCZF3kEw2UsBNbEb6N7tt8qrn9l3UiukT7mJm2/k gjhzslST8gBJanCE6rXTdIYbyXkB2dAL/pTA+mosSfAAQxi0u10Il6C2QVUVtgFjpOsX Fku5Qe+nb7SRVvMjmxLWVFVmWkGEQ6Z3LmSjZmyj929AX3RAfh+rKslxgHYu9JdlWWSk +fMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aJgvldvrl+SGje7vrvMudPyYsFoVLhwI/Ka2l1gBY/s=; b=4KdM+mY3L0AcAEVrKS4V1VP3buyfm/sd8NMGmgxey9NmMXVjgc+Y1XLWKtsPCCBc2r eU7pDDApQJuKXvIjZCqcfZw5PVvRfLyFqF1m/OW+OjCq+/foJ5RBlOZ56HoHqbSTKvrk C1MH6XbssJR/lNhdevoGyPbOHiR139QYV7QAi3PDYTsBSENFRvDYNs1h6vvwr5xg6vdN MtyOTMklwBIKbdRJCaUx1N63EVGls7ztVnOX0TNvm0AQx3rdaT8CN3i8nW3z0s0bYtac t9RXzy53sLjuSe0f0+oiUP5ZqHUHEWpPPUg9ND6XatSvD3tLni2IygPZsnzQQJ7iyTZE n91A== X-Gm-Message-State: AOAM533Fte6Q8Mm9dr+5/Llo/nylvmd3TVHp9f/cwja4rruZp8nrWY8O yPFaTepUE3+KWDkICo8bLZg5rg== X-Google-Smtp-Source: ABdhPJy8v3lO9IlpWN9arBrpt9H5a+nAzLOyyHuBDoQ7cWercOLLTunpCdmZbfiUQ5Ym7b1qfpvlJQ== X-Received: by 2002:a05:6a00:279e:b0:4ca:91aa:32ce with SMTP id bd30-20020a056a00279e00b004ca91aa32cemr1186844pfb.36.1645644611121; Wed, 23 Feb 2022 11:30:11 -0800 (PST) Received: from localhost.localdomain ([2402:3a80:180f:6b3c:fda0:57e9:7d44:2aa7]) by smtp.gmail.com with ESMTPSA id z10-20020a17090a8b8a00b001b8d20074c8sm3719917pjn.33.2022.02.23.11.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 11:30:10 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Rob Herring Subject: [PATCH 1/6] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC Date: Thu, 24 Feb 2022 00:59:41 +0530 Message-Id: <20220223192946.473172-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to the one used on SM8250. Cc: Lorenzo Pieralisi Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Document= ation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..a023f97daf84 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -14,6 +14,7 @@ - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8150" for sm8150 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 =20 @@ -157,7 +158,7 @@ - "pipe" PIPE clock =20 - clock-names: - Usage: required for sc8180x and sm8250 + Usage: required for sc8180x, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -246,7 +247,7 @@ - "ahb" AHB reset =20 - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8150 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset --=20 2.35.1 From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E332CC433FE for ; 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Wed, 23 Feb 2022 11:30:15 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Rob Herring Subject: [PATCH 2/6] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings Date: Thu, 24 Feb 2022 00:59:42 +0530 Message-Id: <20220223192946.473172-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the following two PCIe PHYs found on SM8150, to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Cc: Rob Herring Signed-off-by: Bhupesh Sharma Acked-by: Rob Herring --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e417cd667997..9e0f60e682c4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -38,6 +38,8 @@ properties: - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm6115-qmp-ufs-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy @@ -333,6 +335,8 @@ allOf: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdx55-qmp-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy --=20 2.35.1 From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1643C4332F for ; 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Wed, 23 Feb 2022 11:30:21 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Vinod Koul Subject: [PATCH 3/6] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Date: Thu, 24 Feb 2022 00:59:43 +0530 Message-Id: <20220223192946.473172-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8150 has multiple (different) PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes Add support for these with relevant init sequence. Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma --- drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy= -qcom-qmp.c index 8ea87c69f463..0805c1bab690 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] =3D= { "aux", "cfg_ahb", "ref", "refgen", }; =20 +/* the pcie phy on sm8150 doesn't have a ref clock */ +static const char * const sm8150_pciephy_clk_l[] =3D { + "aux", "cfg_ahb", "refgen", +}; + static const char * const qmp_v4_phy_clk_l[] =3D { "aux", "ref_clk_src", "ref", "com_aux", }; @@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_c= fg =3D { .pwrdn_delay_max =3D 1005, /* us */ }; =20 +static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 1, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .serdes_tbl_sec =3D sm8250_qmp_gen3x1_pcie_serdes_tbl, + .serdes_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x1_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + +static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg =3D { + .type =3D PHY_TYPE_PCIE, + .nlanes =3D 2, + + .serdes_tbl =3D sm8250_qmp_pcie_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), + .tx_tbl =3D sm8250_qmp_pcie_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), + .tx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_tx_tbl, + .tx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), + .rx_tbl =3D sm8250_qmp_pcie_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), + .rx_tbl_sec =3D sm8250_qmp_gen3x2_pcie_rx_tbl, + .rx_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), + .pcs_tbl =3D sm8250_qmp_pcie_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), + .pcs_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_tbl, + .pcs_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc_tbl =3D sm8250_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num =3D ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), + .pcs_misc_tbl_sec =3D sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num_sec =3D ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), + .clk_list =3D sm8150_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(sm8150_pciephy_clk_l), + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8250_pcie_regs_layout, + + .start_ctrl =3D PCS_START | SERDES_START, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .is_dual_lane_phy =3D true, + .has_pwrdn_delay =3D true, + .pwrdn_delay_min =3D 995, /* us */ + .pwrdn_delay_max =3D 1005, /* us */ +}; + static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg =3D { .type =3D PHY_TYPE_PCIE, .nlanes =3D 1, @@ -6004,6 +6088,12 @@ static const struct of_device_id qcom_qmp_phy_of_mat= ch_table[] =3D { }, { .compatible =3D "qcom,sm6115-qmp-ufs-phy", .data =3D &sm6115_ufsphy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy", + .data =3D &sm8150_qmp_gen3x1_pciephy_cfg, + }, { + .compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy", + .data =3D &sm8150_qmp_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,sm8150-qmp-ufs-phy", .data =3D &sm8150_ufsphy_cfg, --=20 2.35.1 From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC604C4332F for ; Wed, 23 Feb 2022 19:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244427AbiBWTa7 (ORCPT ); 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Wed, 23 Feb 2022 11:30:26 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Vinod Koul Subject: [PATCH 4/6] PCI: qcom: Add SM8150 SoC support Date: Thu, 24 Feb 2022 00:59:44 +0530 Message-Id: <20220223192946.473172-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on SM8250. Hence the support is added reusing the members of ops_2_7_0. Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c19cd506ed3f..66fbc0234888 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 =3D { .config_sid =3D qcom_pcie_config_sid_sm8250, }; =20 +/* Qcom IP rev.: 1.5.0 */ +static const struct qcom_pcie_ops ops_1_5_0 =3D { + .get_resources =3D qcom_pcie_get_resources_2_7_0, + .init =3D qcom_pcie_init_2_7_0, + .deinit =3D qcom_pcie_deinit_2_7_0, + .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, + .post_init =3D qcom_pcie_post_init_2_7_0, + .post_deinit =3D qcom_pcie_post_deinit_2_7_0, + .config_sid =3D qcom_pcie_config_sid_sm8250, +}; + static const struct qcom_pcie_cfg apq8084_cfg =3D { .ops =3D &ops_1_0_0, }; @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg =3D { .ops =3D &ops_2_7_0, }; =20 +static const struct qcom_pcie_cfg sm8150_cfg =3D { + .ops =3D &ops_1_5_0, +}; + static const struct qcom_pcie_cfg sm8250_cfg =3D { .ops =3D &ops_1_9_0, }; @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-ipq4019", .data =3D &ipq4019_cfg }, { .compatible =3D "qcom,pcie-qcs404", .data =3D &ipq4019_cfg }, { .compatible =3D "qcom,pcie-sdm845", .data =3D &sdm845_cfg }, + { .compatible =3D "qcom,pcie-sm8150", .data =3D &sm8150_cfg }, { .compatible =3D "qcom,pcie-sm8250", .data =3D &sm8250_cfg }, { .compatible =3D "qcom,pcie-sc8180x", .data =3D &sm8250_cfg }, { .compatible =3D "qcom,pcie-sc7280", .data =3D &sc7280_cfg }, --=20 2.35.1 From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA5D8C433FE for ; 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Wed, 23 Feb 2022 11:30:32 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org Subject: [PATCH 5/6] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Date: Thu, 24 Feb 2022 00:59:45 +0530 Message-Id: <20220223192946.473172-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add nodes for the two PCIe controllers founds on the SM8150 SoC. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 6012322a5984..b97f04ec9c6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1626,6 +1626,203 @@ system-cache-controller@9200000 { interrupts =3D ; }; =20 + pcie0: pci@1c00000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommus =3D <&apps_smmu 0x1d80 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sm8150-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie0_lane: phy@1c06200 { + reg =3D <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible =3D "qcom,pcie-sm8150", "snps,dw-pcie"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1e00 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + phys =3D <&pcie1_lane>; + phy-names =3D "pciephy"; + + perst-gpio =3D <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible =3D "qcom,sm8150-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c0e000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "refgen"; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie1_lane: phy@1c0e200 { + reg =3D <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default { drive-strength =3D <6>; bias-disable; }; + + pcie0_default_state: pcie0-default { + perst { + pins =3D "gpio35"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio36"; + function =3D "pci_e0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio37"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins =3D "gpio102"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq { + pins =3D "gpio103"; + function =3D "pci_e1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake { + pins =3D "gpio104"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; }; =20 remoteproc_mpss: remoteproc@4080000 { --=20 2.35.1 From nobody Thu Jun 25 05:27:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCDB4C43219 for ; Wed, 23 Feb 2022 19:30:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244454AbiBWTbO (ORCPT ); Wed, 23 Feb 2022 14:31:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244411AbiBWTbG (ORCPT ); Wed, 23 Feb 2022 14:31:06 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A996F47AF2 for ; Wed, 23 Feb 2022 11:30:38 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id u16so16314616pfg.12 for ; Wed, 23 Feb 2022 11:30:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zqsit+rOnmNUmUZtDFG33t7bXRXpX6/2jlTb49W6F6M=; b=f7ydfWcBpxG5L6A2J381iH4HWO+Fp0BYmpu1BDed5ABZxf3XF6oP22Y2AHf1sQ84NC fCHfEbUqyV0eKToUFSRE87ycmYTQ+r2inuCnGkuzGDsyADlZcAYUDOohGDDxfUP+D0FZ lZ3E9/ZVEoeHtClSloT/tJEOgS4Xk3G13zV6+5JML2acxJFI0ijqb1tivgKRgWJ5EGtd KoNUtrClFYCh3XaHnHiua5O+P3lP+t9GOdrrO6b3pG/KuuPyo/Ju7SkVGfi7YlmTEddu /PLB44NIT8UAT1W4be7+Yjr8m2Q/A+UYi74HuvGrttYLUemQbZDa/mhrYM43pqIFaMk2 PNTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zqsit+rOnmNUmUZtDFG33t7bXRXpX6/2jlTb49W6F6M=; b=qpXJDIqIQUYweYBkAYd+DNVUwSENWSWieH3Q/VoWckYojmM4XsF/LdC1iL3QWb9f+G 2ohqLe5YE7adpUmkLuxQNf8aszp4tjzQwi66O6iO/CA40f74krN7shg3UIsLkJrxo5Qu BcHYS0VM2PJSwry39y3X/YVwmr0dDkMzj54/+w9NG7IAW49EP/fIr2MhdzJCQKSXWoas Bb7nedoLqLB9PorNOo/OtduciktY8EepAblRVdbGxg1j6qQCL5R86BBXrRWwNyGBC1kA kNrHChpperswEBvOkcLY+73vhAH08VT5QNe0ykJC8AlYw+JMfBTpDQa/WFfqRoS1lliP m4zw== X-Gm-Message-State: AOAM531yVlAYYvb2QCguOwf0crPyOa8XtkK2GTwMEseWSwJq3RdKZ8bF 82FWh69fVrJzYQtUqOrQu7HrtA== X-Google-Smtp-Source: ABdhPJw53BrQr0n38u/wHZsD3cRkteTWrFt8/b5hq6lDWI5EoJ5nulNAJh28GXAqBXqUQxuAiQuCRA== X-Received: by 2002:a05:6a00:23d5:b0:4e1:7cfb:7e85 with SMTP id g21-20020a056a0023d500b004e17cfb7e85mr1166724pfc.29.1645644638198; Wed, 23 Feb 2022 11:30:38 -0800 (PST) Received: from localhost.localdomain ([2402:3a80:180f:6b3c:fda0:57e9:7d44:2aa7]) by smtp.gmail.com with ESMTPSA id z10-20020a17090a8b8a00b001b8d20074c8sm3719917pjn.33.2022.02.23.11.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 11:30:37 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, Vinod Koul Subject: [PATCH 6/6] arm64: dts: qcom: sa8155: Enable pcie nodes Date: Thu, 24 Feb 2022 00:59:46 +0530 Message-Id: <20220223192946.473172-7-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220223192946.473172-1-bhupesh.sharma@linaro.org> References: <20220223192946.473172-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8155p-adp.dts index 8756c2b25c7e..3f6b3ee404f5 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -387,9 +387,51 @@ &usb_2_qmpphy { vdda-pll-supply =3D <&vdda_usb_ss_dp_core_1>; }; =20 +&pcie0 { + status =3D "okay"; +}; + +&pcie0_phy { + status =3D "okay"; + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l18c_0p88>; + vdda-pll-supply =3D <&vreg_l8c_1p2>; +}; + &tlmm { gpio-reserved-ranges =3D <0 4>; =20 + bt_en_default: bt_en_default { + mux { + pins =3D "gpio172"; + function =3D "gpio"; + }; + + config { + pins =3D "gpio172"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + wlan_en_default: wlan_en_default { + mux { + pins =3D "gpio169"; + function =3D "gpio"; + }; + + config { + pins =3D "gpio169"; + drive-strength =3D <16>; + output-high; + bias-pull-up; + }; + }; + usb2phy_ac_en1_default: usb2phy_ac_en1_default { mux { pins =3D "gpio113"; --=20 2.35.1