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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:23 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Anup Patel , Heiko Stuebner , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 1/6] RISC-V: Correctly print supported extensions Date: Tue, 22 Feb 2022 12:48:06 -0800 Message-Id: <20220222204811.2281949-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by: Anup Patel Tested-by: Heiko Stuebner Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include =20 +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); - for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); --=20 2.30.2 From nobody Thu Jun 25 08:28:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0C07C4332F for ; Tue, 22 Feb 2022 20:48:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235634AbiBVUs6 (ORCPT ); Tue, 22 Feb 2022 15:48:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235588AbiBVUsw (ORCPT ); Tue, 22 Feb 2022 15:48:52 -0500 Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C56DA2F2C for ; Tue, 22 Feb 2022 12:48:27 -0800 (PST) Received: by mail-oo1-xc2f.google.com with SMTP id i10-20020a4aab0a000000b002fccf890d5fso19383651oon.5 for ; Tue, 22 Feb 2022 12:48:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=6a+eX7j3LCyMn7OaC5yvtENFql8mK7SDDMa4RtV1aQ93fAn5DduP6Fgc7zUxkNDPTK 2f5BEhyv8QBUUnYojgoP9I+MJqoziATEH1PvK8x/8t7oxNPO0/tcxhlAJGfxpsv2ELxp nfu2dWei93dbF37AOXHaYScoVk4bCNOoDm8lnsSjeyt2iYjkkidiwnvv/dGi5PNu1x2R 68xEWUesACbG6mjSkozJilU0wLtHje/Ch7BosK/ew81mgyEbv8fsSfyEZnHa/tvVCuWn NihWa3DT/You12J90LfMjxx/hnQY9P/qyn3SO5SeuXy/X83tM5KGyBCAF4sPu+G1sY0j nLbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FsTSrbVAURtuc7icXoc7CnjlReAr0UpIVXQMIlDTc4=; b=cU3tz6v7NdygR1s6iJUzmyoStRiCEyFp79/pb6wflfIfTQExwxie74bMs8YupzXAEe JDfXWAuTWmXqnbfeC5c2iYsZWS/9lYS1Ri0J0JmIRpF9EjkxOtZ/wwV4K1ct6sXCAxBS 5x7/W7zutUsjju5QNDhG06LHeUGLzzmpJLNFljVu/TxySCYgXiXA2euAEODmZSTJKPhO wCeXnOy7tQnSTj+fQlgPdjbOQ58H6RLpUQMIh0+oONRliJuNHh6jYpBJPZN74gljG1Gg JF/GuMKhpKjqomy3pEzUHaedu0H2TwCigMy4wBxPTI5sW30OhFHlK7b9/Vedona0n+oJ l7pA== X-Gm-Message-State: AOAM530XY+sqjCDiJKEpT/C0ocs2XFZLY3/gKUyYCN9q4xeMMKZt9TLV 8wnTvNJqceGTgmJHLpvgVXBAhdd+zA+H0g== X-Google-Smtp-Source: ABdhPJwVNKQnkJZdZ0jgSou92auChtzBu1r7KPJtir+JSZM/M01cC0DkREbbPZe7LjE4CO/652m/yQ== X-Received: by 2002:a05:6870:d88e:b0:d1:359a:29f with SMTP id dv14-20020a056870d88e00b000d1359a029fmr2644172oab.232.1645562906164; Tue, 22 Feb 2022 12:48:26 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:25 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 2/6] RISC-V: Minimal parser for "riscv, isa" strings Date: Tue, 22 Feb 2022 12:48:07 -0800 Message-Id: <20220222204811.2281949-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: Atish Patra [Fixed workaround for QEMU] Signed-off-by: Tsukasa OI Tested-by: Heiko Stuebner Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 72 ++++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dd3d57eb4eea..72c5f6ef56b5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -66,7 +67,7 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - size_t i, j, isa_len; + int i, j; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -92,23 +93,72 @@ void __init riscv_fill_hwcap(void) continue; } =20 - i =3D 0; - isa_len =3D strlen(isa); #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) - i +=3D 4; + isa +=3D 4; #elif IS_ENABLED(CONFIG_64BIT) if (!strncmp(isa, "rv64", 4)) - i +=3D 4; + isa +=3D 4; #endif - for (; i < isa_len; ++i) { - this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + for (; *isa; ++isa) { + const char *ext =3D isa++; + const char *ext_end =3D isa; + bool ext_long =3D false, ext_err =3D false; + + switch (*ext) { + case 's': + /** + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] !=3D '_' && ext[1] =3D=3D 'u') { + ++isa; + ext_err =3D true; + break; + } + fallthrough; + case 'x': + case 'z': + ext_long =3D true; + /* Multi-letter extension must be delimited */ + for (; *isa && *isa !=3D '_'; ++isa) + if (!islower(*isa) && !isdigit(*isa)) + ext_err =3D true; + break; + default: + if (unlikely(!islower(*ext))) { + ext_err =3D true; + break; + } + /* Find next extension */ + if (!isdigit(*isa)) + break; + /* Skip the minor version */ + while (isdigit(*++isa)) + ; + if (*isa !=3D 'p') + break; + if (!isdigit(*++isa)) { + --isa; + break; + } + /* Skip the major version */ + while (isdigit(*++isa)) + ; + break; + } + if (*isa !=3D '_') + --isa; /* - * TODO: X, Y and Z extension parsing for Host ISA - * bitmap will be added in-future. + * TODO: Full version-aware handling including + * multi-letter extensions will be added in-future. */ - if ('a' <=3D isa[i] && isa[i] < 'x') - this_isa |=3D (1UL << (isa[i] - 'a')); + if (ext_err || ext_long) + continue; + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); } =20 /* --=20 2.30.2 From nobody Thu Jun 25 08:28:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47F97C433FE for ; Tue, 22 Feb 2022 20:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235609AbiBVUtB (ORCPT ); Tue, 22 Feb 2022 15:49:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235606AbiBVUsy (ORCPT ); Tue, 22 Feb 2022 15:48:54 -0500 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D233AA2F2C for ; Tue, 22 Feb 2022 12:48:28 -0800 (PST) Received: by mail-oi1-x22b.google.com with SMTP id a6so15938848oid.9 for ; Tue, 22 Feb 2022 12:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=qi2CLkoTpNf+/7KRpxJWRKKedV3ySUp6Hi5CiH/Rl69V/1ZYKrlbplu5LuSaHdhRIr U3qvvNSC3b8wbwX2/jLQsKii0fmBsrukVOjWCg8MHzVUm8SSVTFJXjwemeX/p3d7bn6Q +m87Kf9FB60c/CB+MHLc7aTiHvLqierIr4BTAMkPS7FbbukSEVFc7B/wbjSfrQvOn2Jk E8yxCnUIUCRB+eJ5tkE7gfAvVChYIkBzF1uoQFj7V7qm3IKD0Nr14+iqzwFSYX/sG6p8 N4+OOxN8twd0yzhKVeF35CuuEGVtvYulguhNHU0z+MdnBFRUedC9fBtzQri9+gdN6jNK 01IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c80lDSr4/XrHo4HXuUiUdwW2N5759X0Jr8s3r01G4uw=; b=3cwrRyKIH/huRtEWLKjHhCMDFDloxA9zFuD2/VFgo6B3Ia/zog7NijOpI0zpLTYUr6 otTDldltn/HaER1MdCGmmygn5T+ELrbp7HIg5cBlmw+loArcJb4vbyo3zQ4mnjrbe1qs WuufYnZ40weyOSjBriAJC+kGkAUJ0KaEYr+NFkpMuQUO8KA6tcNbeIZFD21OIcnY9aXG gG2q5fsKh+pxweW5JW3oygd4uvyTgpWVYbkBOq6XHdlfmoZq2VYkrM09uNzfdup/qODa GC9jnpQLDTQBFx7/aZCV7YJrc0YyXwjf9OHWmtq0iH7XVlJ4iaTnkcdJWr35w1n91PWh vzEQ== X-Gm-Message-State: AOAM530qBH0tIpJF5wQpaFkda+qFcTD6mkuxad/jpivwxkH4n8hZlm3C akk1LJHSyyGG4TILBB7s7DsAfuSZo/xdwA== X-Google-Smtp-Source: ABdhPJz2U8KLjdjNRUB//gea/ufjet3hLSc2A6nlzGRCQGTmGSKt0aTPN50GrrZNsqro3BBTDjNyuQ== X-Received: by 2002:a05:6808:2106:b0:2d5:3244:ca43 with SMTP id r6-20020a056808210600b002d53244ca43mr2968470oiw.263.1645562907949; Tue, 22 Feb 2022 12:48:27 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:27 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Heiko Stuebner , Anup Patel , Atish Patra , Albert Ou , Atish Patra , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Date: Tue, 22 Feb 2022 12:48:08 -0800 Message-Id: <20220222204811.2281949-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by: Heiko Stuebner Reviewed-by: Anup Patel Signed-off-by: Tsukasa OI [Improved commit text and comments] Signed-off-by: Atish Patra --- arch/riscv/kernel/cpufeature.c | 35 ++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 72c5f6ef56b5..b0df7eff47f7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -124,8 +124,28 @@ void __init riscv_fill_hwcap(void) ext_long =3D true; /* Multi-letter extension must be delimited */ for (; *isa && *isa !=3D '_'; ++isa) - if (!islower(*isa) && !isdigit(*isa)) + if (unlikely(!islower(*isa) + && !isdigit(*isa))) ext_err =3D true; + /* Parse backwards */ + ext_end =3D isa; + if (unlikely(ext_err)) + break; + if (!isdigit(ext_end[-1])) + break; + /* Skip the minor version */ + while (isdigit(*--ext_end)) + ; + if (ext_end[0] !=3D 'p' + || !isdigit(ext_end[-1])) { + /* Advance it to offset the pre-decrement */ + ++ext_end; + break; + } + /* Skip the major version */ + while (isdigit(*--ext_end)) + ; + ++ext_end; break; default: if (unlikely(!islower(*ext))) { @@ -151,14 +171,13 @@ void __init riscv_fill_hwcap(void) } if (*isa !=3D '_') --isa; - /* - * TODO: Full version-aware handling including - * multi-letter extensions will be added in-future. - */ - if (ext_err || ext_long) + + if (unlikely(ext_err)) continue; - this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + if (!ext_long) { + this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; + this_isa |=3D (1UL << (*ext - 'a')); + } } =20 /* --=20 2.30.2 From nobody Thu Jun 25 08:28:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF670C433EF for ; Tue, 22 Feb 2022 20:48:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235658AbiBVUtE (ORCPT ); Tue, 22 Feb 2022 15:49:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235624AbiBVUs4 (ORCPT ); Tue, 22 Feb 2022 15:48:56 -0500 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4865A41BB for ; Tue, 22 Feb 2022 12:48:30 -0800 (PST) Received: by mail-ot1-x331.google.com with SMTP id j9-20020a9d7d89000000b005ad5525ba09so8209992otn.10 for ; Tue, 22 Feb 2022 12:48:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7jxshT1pWA/8RZp0d4XCT2f4zJBopPI7Okk1zgrv3jU=; b=rcW/NJ3twEXUjUwMjHFOr2n4rYJi5TW0BSWPqI5ZoOTC69sMiCT7h39r/USkVKIYHO 0J2flxYvVc4S5GlpKiyqWPWZ12NjMFEZGGXqZRYLd8u4IZRM3jsapeRiUNIB4Kz4YNRJ vsGUv/doyie+sOOkt9MyiQT0aCPc58B6+vDRtK7Yssu/yQahgZlZSKXETmW/M9H5q/mt 1iZCAQKnBPTdewg+SDGiRZcm49aAaAXE2pJsqwZxZPvb/9VFXrTEfSbspTuz4j/rAm0C UizPz/QaiZZRMKTsJoQ2BABJCcmgTTyz82uJGl8xZhvsrVXCxkwaDOh75iEcoNCtrPVY DzPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7jxshT1pWA/8RZp0d4XCT2f4zJBopPI7Okk1zgrv3jU=; b=LW+tNpVFWg5MmlsiM8ILPm5/LQX/ty4RBbqS2FYei/HQt8ne0D81SELIDev79oKHW6 Za82JF66AtepY8FZiU5tr4YyZQiD1egU5T+BaMaPhXCaMz2SsII4UhLk5UjURloMuHf5 VNvKwtroTBZzQRJ6g9lx6rWSGZa3DtsAgA41XapSDFFnrvP3z/0CW2yEk3qvPcbD+j5E kvkSkHZ3aobpuDfhppHzyijNbzDMzBkHfT2xh3JFhlEM6WiPKGLJZxflauUuPFtGal3Z HWeG5lzfBMppMYzoHhP2pzDKiRdvLNkRS8blzpZIP7TZJcts0OPivuuuQwyvXvyOTog2 u3fw== X-Gm-Message-State: AOAM533zlzV0vJyPTPr2qQ724KupJ6jdFmq1RR8oTTd31FLiOYAJUHAU ehnmYcqDZ/WKPDJ+8haO/4Bo2/csoHXyog== X-Google-Smtp-Source: ABdhPJziqVBxNlzDAcUXnP8ghiwG6ffgujh/J8VzWwqr8QmDfZL1gilLS0gYfHzMF0NzxkkbF/GKGQ== X-Received: by 2002:a05:6830:410b:b0:5af:432e:e375 with SMTP id w11-20020a056830410b00b005af432ee375mr3276695ott.191.1645562909675; Tue, 22 Feb 2022 12:48:29 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:29 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 4/6] RISC-V: Implement multi-letter ISA extension probing framework Date: Tue, 22 Feb 2022 12:48:09 -0800 Message-Id: <20220222204811.2281949-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 18 ++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..170bd80da520 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -34,7 +34,25 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') =20 +/* + * Increse this to higher value as kernel support more ISA extensions. + */ #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +/* The base ID for multi-letter ISA extensions */ +#define RISCV_ISA_EXT_BASE 26 + +/* + * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed + * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter + * extensions while all the multi-letter extensions should define the next + * available logical extension id. + */ +enum riscv_isa_ext_id { + RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +}; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b0df7eff47f7..c6693873e95c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -83,7 +83,7 @@ void __init riscv_fill_hwcap(void) =20 for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; - unsigned long this_isa =3D 0; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -100,6 +100,7 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; @@ -172,12 +173,22 @@ void __init riscv_fill_hwcap(void) if (*isa !=3D '_') --isa; =20 +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + set_bit(bit, this_isa); \ + pr_info("Found ISA extension %s", name);\ + } \ + } while (false) \ + if (unlikely(ext_err)) continue; if (!ext_long) { this_hwcap |=3D isa2hwcap[(unsigned char)(*ext)]; - this_isa |=3D (1UL << (*ext - 'a')); + set_bit(*ext - 'a', this_isa); } +#undef SET_ISA_EXT_MAP } =20 /* @@ -190,10 +201,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap =3D this_hwcap; =20 - if (riscv_isa[0]) - riscv_isa[0] &=3D this_isa; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else - riscv_isa[0] =3D this_isa; + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } =20 /* We don't support systems with F but without D, so mask those out @@ -207,7 +219,7 @@ void __init riscv_fill_hwcap(void) for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); - pr_info("riscv: ISA extensions %s\n", print_str); + pr_info("riscv: base ISA extensions %s\n", print_str); =20 memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) --=20 2.30.2 From nobody Thu Jun 25 08:28:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D829C4167B for ; Tue, 22 Feb 2022 20:48:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235663AbiBVUtK (ORCPT ); Tue, 22 Feb 2022 15:49:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235633AbiBVUs6 (ORCPT ); Tue, 22 Feb 2022 15:48:58 -0500 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B74C2A41A3 for ; Tue, 22 Feb 2022 12:48:32 -0800 (PST) Received: by mail-oi1-x231.google.com with SMTP id j2so15953471oie.7 for ; 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Date: Tue, 22 Feb 2022 12:48:10 -0800 Message-Id: <20220222204811.2281949-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kernel/cpufeature.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6693873e95c..f3a4b0619aa0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + const char *temp; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) continue; } =20 + temp =3D isa; #if IS_ENABLED(CONFIG_32BIT) if (!strncmp(isa, "rv32", 4)) isa +=3D 4; @@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void) if (!strncmp(isa, "rv64", 4)) isa +=3D 4; #endif + /* The riscv,isa DT property must start with rv64 or rv32 */ + if (temp =3D=3D isa) + continue; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; --=20 2.30.2 From nobody Thu Jun 25 08:28:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E6A8C433EF for ; Tue, 22 Feb 2022 20:48:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235669AbiBVUtN (ORCPT ); Tue, 22 Feb 2022 15:49:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235660AbiBVUtI (ORCPT ); Tue, 22 Feb 2022 15:49:08 -0500 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D94BA644D for ; Tue, 22 Feb 2022 12:48:34 -0800 (PST) Received: by mail-oi1-x231.google.com with SMTP id z7so12955551oid.4 for ; Tue, 22 Feb 2022 12:48:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8URXe1loYhEkYqA2mgPstYxk0kAqAk7osNiGz1KzfP4=; b=tkekYg+ui1gZE9tvXRPYNaXdnHSqvcZXJR3E2Vm5fQodbde1h2KEXdYVPBeSbBJrKE tZITXpUaJDk67Z/a7izDd9M3gsdIhhNTMcdTj6S8CxQsNWqSdzP/jKbyNPXB2oJu3avO 3Zk4Jzm23rDMqdxFIbyWksIRJgMYHe95vMZ4pU0NzJ4BWBMvSQ1mHfq53uAu7WYa6PEM +utp42+TYOdOY+tnl0KO6BUIuJx91baW39b4LLo7XR8xTBndLIkdHIwQHVU5hXpmXZsc ZJOLoy8uvivgGGcYyqXtIuEtIJ/Cze3eAL876RuQ9h20mvCPEdnfU11wF41bvhGTyTig senQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8URXe1loYhEkYqA2mgPstYxk0kAqAk7osNiGz1KzfP4=; b=OtaV98MNSjPr+OoDzj5IIQNsuGAYml7Sxrughk6XF6XfGExLpHYQouks7bOUZgPEmB LIbn9G4xzELaXFNaAx0ck1ab/F7AMtHSfuNb7fNomKXE//qUNw9YDXh6SEaApTRWbgrL kjSNBUcFhFFV8EdNxpE7pKBvDSGk2BCpmxUtKCGayIKAOLK+pHQCjfiZ4taOS6b3KZwr OttU0++FdoGevmhjfQ0ezTIueBh3GvDFCCWmexGhCPPI/3I6dHbJa2HJQFGfDhpbSXTO ppoXNlgvrvRqhF727DCzfoxBX8tORqGzqbMSnfdiWB1fDrYzuiZ67tG4oh7hvtw9Ytn2 AMLg== X-Gm-Message-State: AOAM531NrxVAdcOlHH5U363vYEDpJVC6DXPw2CulQFC0cOeZt/A4JlI1 rrf/YEzhA0+9BBE0sljs/6d54e5kxZgryQ== X-Google-Smtp-Source: ABdhPJwB9rW8JuhYMN3o1Zy+a756u4qrYvSc4u5fAhxI6ME+4kF0AoSQeiNHi0jhT+ZAJKpoKp4vFQ== X-Received: by 2002:aca:5b85:0:b0:2d3:fe13:177f with SMTP id p127-20020aca5b85000000b002d3fe13177fmr2847716oib.59.1645562913488; Tue, 22 Feb 2022 12:48:33 -0800 (PST) Received: from rivos-atish.. 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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id o14sm16508197oaq.37.2022.02.22.12.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 12:48:33 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v5 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Tue, 22 Feb 2022 12:48:11 -0800 Message-Id: <20220222204811.2281949-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220222204811.2281949-1-atishp@rivosinc.com> References: <20220222204811.2281949-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Same goes for the single letter extensions as well which prints the entire ISA string. Some of they may not be valid ISA extensions as well (e.g 'su') Parse only the valid & enabled ISA extension and print them. Tested-by: Heiko Stuebner Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/hwcap.h | 7 +++++ arch/riscv/kernel/cpu.c | 51 ++++++++++++++++++++++++++++++++-- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..031ad15a059f 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -63,12 +64,57 @@ int riscv_of_parent_hartid(struct device_node *node) } =20 #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] =3D { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i =3D 0, arr_sz; + + arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <=3D 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i =3D 0; i <=3D arr_sz; i++) { + edata =3D &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} + +/** + * These are the only valid base (single letter) ISA extensions as per the= spec. + * It also specifies the canonical order in which it appears in the spec. + * Some of the extension may just be a place holder for now (B, K, P, J). + * This should be updated once corresponding extensions are ratified. + */ +static const char base_riscv_exts[13] =3D "imafdqcbkjpvh"; =20 static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + int i; + seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + /* Print the rv[64/32] part */ + seq_write(f, isa, 4); + for (i =3D 0; i < sizeof(base_riscv_exts); i++) { + if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) + /* Print only enabled the base ISA extensions */ + seq_write(f, &base_riscv_exts[i], 1); + } seq_puts(f, "\n"); } =20 @@ -115,6 +161,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) --=20 2.30.2